Commit Graph

232853 Commits

Author SHA1 Message Date
Vedant Kumar 7f5200162b Trim some spaces (NFC)
llvm-svn: 271681
2016-06-03 15:58:59 +00:00
Reid Kleckner a8d5740757 [codeview] Add basic record type translation
This only translates data members for now. Translating overloaded
methods is complicated, so I stopped short of doing that.

Reviewers: aaboud

Differential Revision: http://reviews.llvm.org/D20924

llvm-svn: 271680
2016-06-03 15:58:20 +00:00
Sjoerd Meijer 9bc93f6298 Code size optimisation: do not inline memcpy if this expansion results
in more instructions than the libary call.

Differential Revision: http://reviews.llvm.org/D20958

llvm-svn: 271678
2016-06-03 15:38:55 +00:00
Chad Rosier 2d658703e1 [AArch64] Spot SBFX-compatbile code expressed with sign_extend_inreg.
We were assuming all SBFX-like operations would have the shl/asr form, but often
when the field being extracted is an i8 or i16, we end up with a
SIGN_EXTEND_INREG acting on a shift instead.

This is a port of r213754 from ARM to AArch64.

llvm-svn: 271677
2016-06-03 15:00:09 +00:00
Sanjay Patel 6cf18af1c5 [InstCombine] look through bitcasts to find selects
There was concern that creating bitcasts for the simpler potential select pattern:

define <2 x i64> @vecBitcastOp1(<4 x i1> %cmp, <2 x i64> %a) {
  %a2 = add <2 x i64> %a, %a
  %sext = sext <4 x i1> %cmp to <4 x i32>
  %bc = bitcast <4 x i32> %sext to <2 x i64>
  %and = and <2 x i64> %a2, %bc
  ret <2 x i64> %and
}

might lead to worse code for some targets, so this patch is matching the larger
patterns seen in the test cases.

The motivating example for this patch is this IR produced via SSE intrinsics in C:

define <2 x i64> @gibson(<2 x i64> %a, <2 x i64> %b) {
  %t0 = bitcast <2 x i64> %a to <4 x i32>
  %t1 = bitcast <2 x i64> %b to <4 x i32>
  %cmp = icmp sgt <4 x i32> %t0, %t1
  %sext = sext <4 x i1> %cmp to <4 x i32>
  %t2 = bitcast <4 x i32> %sext to <2 x i64>
  %and = and <2 x i64> %t2, %a
  %neg = xor <4 x i32> %sext, <i32 -1, i32 -1, i32 -1, i32 -1>
  %neg2 = bitcast <4 x i32> %neg to <2 x i64>
  %and2 = and <2 x i64> %neg2, %b
  %or = or <2 x i64> %and, %and2
  ret <2 x i64> %or
}

For an AVX target, this is currently:

vpcmpgtd  %xmm1, %xmm0, %xmm2
vpand     %xmm0, %xmm2, %xmm0
vpandn    %xmm1, %xmm2, %xmm1
vpor      %xmm1, %xmm0, %xmm0
retq

With this patch, it becomes:

vpmaxsd   %xmm1, %xmm0, %xmm0

Differential Revision: http://reviews.llvm.org/D20774

llvm-svn: 271676
2016-06-03 14:42:07 +00:00
Artem Tamazov f88397c84c [test/AMDGPU] Square-braced-syntax for registers: add macro test/example.
Test added as per discussion in http://reviews.llvm.org/D20588.
The macro is just a demonstration, useless in practice.
Coding style fixes.

Differential Revision: http://reviews.llvm.org/D20797

llvm-svn: 271675
2016-06-03 14:41:17 +00:00
Zachary Turner 71f725735c [pdb] Add string table offsets to check output.
llvm-svn: 271674
2016-06-03 14:22:46 +00:00
Simon Pilgrim ff35eecd90 [X86][AVX512] Fixed 512-bit vector nontemporal load alignment
llvm-svn: 271673
2016-06-03 14:12:43 +00:00
Sjoerd Meijer ba7a16ff33 RAS extensions are part of ARMv8.2.
This patch enables +ras +noras to AArch64 in clang.

Patch by: Roger Ferrer Ibanez and Oliver Stannard

Differential Revision: http://reviews.llvm.org/D20283

llvm-svn: 271672
2016-06-03 14:08:20 +00:00
Benjamin Kramer b53452b2b1 [include-fixer] Be smarter about inserting symbols for a prefix.
If prefix search finds something where nothing can be nested under (e.g.
a variable or macro) don't add it to the result.

This is for cases like:
header.h:
  extern int a;

file.cc:
namespace a {
  SOME_MACRO
}

We will look up a::SOME_MACRO, which doesn't have any results. Then we
look up 'a' and find something before we ever look up just 'SOME_MACRO'.
With some basic filtering we can avoid this case.

Differential Revision: http://reviews.llvm.org/D20960

llvm-svn: 271671
2016-06-03 14:07:38 +00:00
Sjoerd Meijer d906bf1369 RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
new instruction to ARM and AArch64 targets and several system registers.

Patch by: Roger Ferrer Ibanez and Oliver Stannard

Differential Revision: http://reviews.llvm.org/D20282

llvm-svn: 271670
2016-06-03 14:03:27 +00:00
Ben Craig 60adb9229c Adding reserve and capacity methods to FoldingSet
http://reviews.llvm.org/D20930

llvm-svn: 271669
2016-06-03 13:54:48 +00:00
Simon Pilgrim f92d175a78 [X86][AVX512] Added 512-bit vector nontemporal load tests
llvm-svn: 271668
2016-06-03 13:42:49 +00:00
Sjoerd Meijer 9da258d8e5 ARM target does not use printAliasInstr machinery which
forces having special checks in ArmInstPrinter::printInstruction. This
patch addresses this issue.

Not all special checks could be removed: either they involve elaborated
conditions under which the alias is emitted (e.g. ldm/stm on sp may be
pop/push but only if the number of registers is >= 2) or the number
of registers is multivalued (like happens again with ldm/stm) and they
do not match the InstAlias pattern which assumes single-valued operands
in the pattern.

Patch by: Roger Ferrer Ibanez

Differential Revision: http://reviews.llvm.org/D20237

llvm-svn: 271667
2016-06-03 13:19:43 +00:00
Sjoerd Meijer 3c2f785769 AsmWriterEmitter.cpp assumes that all operands of a printed alias
will appear after a blank. This assumption does not hold in the ARM
target.

Patch by: Roger Ferrer Ibanez

Differential Revision: http://reviews.llvm.org/D20234

llvm-svn: 271666
2016-06-03 13:17:37 +00:00
Sjoerd Meijer 84e2f69245 Currently AsmWriterEmiter.cpp (used by tblgen -gen-asm-writer) does not
consider the Predicates attached to InstAlias when generating printAliasInstr.
This forces users of printAliasInstr to check those predicates beforehand.

This commit adds them in the condition set of the IAPrinter object.

Patch by: Roger Ferrer Ibanez

Differential Revision: http://reviews.llvm.org/D20233

llvm-svn: 271665
2016-06-03 13:14:19 +00:00
Eric Liu 303baf53b1 [clang-format] skip empty lines and comments in the top of the code when inserting new headers.
Summary:
[clang-format] skip empty lines and comments in the top of the code when inserting new headers.

Pair-programmed with @hokein

Reviewers: djasper

Subscribers: ioeric, cfe-commits, hokein, klimek

Differential Revision: http://reviews.llvm.org/D20898

llvm-svn: 271664
2016-06-03 12:52:59 +00:00
Dmitry Vyukov 0f7e949a42 tsan: rely on AnnotateRWLockCreateStatic to detect linker-initialized mutexes
The new annotation was added a while ago, but was not actually used.
Use the annotation to detect linker-initialized mutexes instead
of the broken IsGlobalVar which has both false positives and false
negatives. Remove IsGlobalVar mess.

llvm-svn: 271663
2016-06-03 11:48:27 +00:00
Sam Kolton a4a99ad1bc [AMDGPU] Assembler: More tests for SDWA instructions. Fix for SDWA float modifiers.
Summary: Depends on D20625

Reviewers: tstellarAMD, vpykhtin, artem.tamazov

Subscribers: arsenm, kzhuravl

Differential Revision: http://reviews.llvm.org/D20674

llvm-svn: 271662
2016-06-03 11:43:09 +00:00
Haojian Wu 9c6cb035f3 [include-fixer] Don't add missing header if the unindentified symbol isn't from the main file.
Summary:
The further solution is to add the missing header to the file where the
symbol comes from.

Reviewers: bkramer

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D20950

llvm-svn: 271660
2016-06-03 11:26:02 +00:00
Simon Pilgrim a6022c9a63 [X86][SSE] Added nontemporal load tests
These currently all lower to regular loads, generic nontemporal load support will be added in a future patch

llvm-svn: 271659
2016-06-03 11:00:55 +00:00
Daniel Sanders 43750eab82 [mips] EABI CodeGen is completely untested and seems to have bitrotted. Remove it.
Summary:
There are no tests*, no EABI buildbots, and simple test cases do not work.

* There is a single MIPS16 test using a mips*-gnueabi triple but this test
  doesn't test EABI and the triple doesn't cause EABI to be used.

Reviewers: sdardis

Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20906

llvm-svn: 271658
2016-06-03 10:38:09 +00:00
Benjamin Kramer cdaf62684e Revert "[LPM] Replace the CALL_ONCE_... macro in the legacy pass manager with the new llvm::call_once facility."
Fallback path doesn't compile. This reverts commit r271652.

llvm-svn: 271657
2016-06-03 10:36:10 +00:00
Simon Pilgrim 960ca812ed [X86] Added nontemporal scalar store tests
llvm-svn: 271656
2016-06-03 10:30:54 +00:00
Sam Kolton 05ef1c940f [AMDGPU] Assembler: Custom converters for SDWA instructions. Support for _dpp and _sdwa suffixes in mnemonics.
Summary:
Added custom converters for SDWA instruction to support optional operands and modifiers.
Support for _dpp and _sdwa suffixes that allows to force DPP or SDWA encoding for instructions.

Reviewers: tstellarAMD, vpykhtin, artem.tamazov

Subscribers: arsenm, kzhuravl

Differential Revision: http://reviews.llvm.org/D20625

llvm-svn: 271655
2016-06-03 10:27:37 +00:00
Simon Pilgrim 02284541b2 [X86][SSE] Regenerated nontemporal vector store tests and added extra target types
llvm-svn: 271654
2016-06-03 10:24:24 +00:00
Daniel Sanders 7b09493bff [mips] Remove CPU-only triples from llvm-objdump commands.
Summary: They aren't necessary since llvm-objdump can auto-detect the architecture.

Reviewers: sdardis

Subscribers: jfb, dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20904

llvm-svn: 271653
2016-06-03 10:22:22 +00:00
Chandler Carruth 0bc1515a03 [LPM] Replace the CALL_ONCE_... macro in the legacy pass manager with
the new llvm::call_once facility.

This facility matches the standard APIs and when the platform supports
it actually directly uses the standard provided functionality. This is
both more efficient on some platforms and much more TSan friendly.

The only remaining user of the cas_flag and home-rolled atomics is the
fallback implementation of call_once. I have a patch that removes them
entirely, but it needs a Windows patch to land first.

This alone substantially cleans up the macros for the legacy pass
manager, and should subsume some of the work Mehdi was doing to clear
the path for TSan testing of ThinLTO, a really important step to have
reliable upstream testing of ThinLTO in all forms.

llvm-svn: 271652
2016-06-03 10:20:02 +00:00
Simon Pilgrim 38b4661b1b [X86] Regenerated nontemporal store tests and added tests for all 128-bit vector types
llvm-svn: 271651
2016-06-03 10:15:36 +00:00
Chandler Carruth 9ac86efd4d Remove bogus initialization of the PPC and Hexagon SelectionDAGISel
subclasses. These are not passes proper. We don't support registering
them, they can't be constructed with default arguments, and the ID is
actually in a base class.

Only these two targets even had any boiler plate to try to do this, and
it had to be munged out of the INITIALIZE_PASS macros to work. What's
worse, the boiler plate has rotted and the "name" of the pass is
actually the description string now!!! =/ All of this is completely
unnecessary. No other target bothers, and nothing breaks if you don't
initialize them because CodeGen has an entirely separate initialization
path that is somewhat more durable than relying on the implicit
initialization the way the 'opt' tool does for registered passes.

llvm-svn: 271650
2016-06-03 10:13:31 +00:00
Chandler Carruth d474144a7a Use the standard INITIALIZE_PASS macro rather than hand rolling a (not
entirely correct) version of its contents.

llvm-svn: 271649
2016-06-03 10:13:29 +00:00
Chandler Carruth 990111e4d8 Reformat the macros in Passes.h with clang-format before editting them.
No functionality changed here.

llvm-svn: 271648
2016-06-03 10:13:26 +00:00
Daniel Sanders 55e4069702 [mips] Slightly simplify MipsTargetInfo::setDataLayout(). NFC.
Summary:

Reviewers: atanasyan

Subscribers: atanasyan, cfe-commits

Differential Revision: http://reviews.llvm.org/D20680

llvm-svn: 271647
2016-06-03 10:11:01 +00:00
Simon Pilgrim 205f65f62f [X86][AVX2] Relaxed alignment on nontemporal store tests
llvm-svn: 271646
2016-06-03 10:06:59 +00:00
Simon Pilgrim 8ea8940677 [X86][AVX2] Regenerated nontemporal store tests and added tests for all 256-bit vector types
llvm-svn: 271645
2016-06-03 09:56:24 +00:00
Daniel Sanders 6ba3dd6b71 [mips] Implement 'la' macro in PIC mode for O32.
Summary:
N32 support will follow in a later patch since the symbol version of 'la'
incorrectly believes N32 to have 64-bit pointers and rejects it early.

This fixes the three incorrectly expanded 'la' macros found in bionic.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20820

llvm-svn: 271644
2016-06-03 09:53:06 +00:00
Eric Liu 5bc39ab592 [include-fixer] fixed a wrong header mapping.
llvm-svn: 271638
2016-06-03 09:33:22 +00:00
Eric Liu 1ebb7cf052 [include-fixer] added GNU symbols hardcoded header mapping.
Summary: [include-fixer] added GNU symbols hardcoded header mapping.

Reviewers: klimek, bkramer

Subscribers: cfe-commits, hokein

Differential Revision: http://reviews.llvm.org/D20902

llvm-svn: 271637
2016-06-03 09:25:03 +00:00
Sjoerd Meijer b3b8147e1e Add a few missing Clang regression tests for Cortex-A53, Cortex-A57, Cortex-A72
Differential Revision: http://reviews.llvm.org/D20908

llvm-svn: 271636
2016-06-03 08:47:56 +00:00
Chandler Carruth 345d225da2 Run clang-format over PassSupport.h, mostly to get the macros all
formatted fancily.

I'm working on rewriting these macros to use the new call_once stuff,
but really want to have clang-format work on the edits, so just
re-baselining the entire file here. No changes other than clang-format.

llvm-svn: 271635
2016-06-03 08:46:16 +00:00
Asiri Rathnayake 1f077f6b2b [libcxx] Fix thread join.pass.cpp segfault after r271475
Some pthread implementations do not like being called pthead_join()
with the pthread_t argument set to 0, and causes a segfault. This
patch fixes this issue by validating the pthread_t argument before
invoking pthread_join().

NFC.

Differential revision: http://reviews.llvm.org/D20929

Change-Id: Ief817c57bd0e1f43cbaa03061e02417d6a180c38
Reviewers: EricWF
llvm-svn: 271634
2016-06-03 08:45:26 +00:00
Simon Pilgrim e85506b6e0 [X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructions
This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage.

The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls.

Mask decoding/target shuffle support will be added in future patches.

Differential Revision: http://reviews.llvm.org/D20049

llvm-svn: 271633
2016-06-03 08:06:03 +00:00
Haojian Wu d80c7c4808 [clang-tidy] Ignore function context in misc-unused-using-decls.
Summary: Make the check's behavior more correct when handling using-decls in multiple scopes.

Reviewers: alexfh

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D20909

llvm-svn: 271632
2016-06-03 08:05:11 +00:00
Craig Topper 5e3d314488 [X86] Fix some isel patterns to remove an operand from some multiclasses. NFC
llvm-svn: 271631
2016-06-03 05:58:52 +00:00
Zachary Turner 3df1bfaaec [pdb] Print out file names instead of file offsets.
When printing line information and file checksums, we were printing
the file offset field from the struct header.  This teaches
llvm-pdbdump how to turn those numbers into the filename.  In the
case of file checksums, this is done by looking in the global
string table.  In the case of line contributions, this is done
by indexing into the file names buffer of the DBI stream.  Why
they use a different technique I don't know.

llvm-svn: 271630
2016-06-03 05:52:57 +00:00
Craig Topper e7ae106147 [AVX512] Ensure EVEX vpshufd, vpshuflw, and vpshufhw have isel priority over the VEX encoded ones.
llvm-svn: 271629
2016-06-03 05:31:04 +00:00
Craig Topper 01f53b1773 [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW.
llvm-svn: 271628
2016-06-03 05:31:00 +00:00
Craig Topper dc70d8a4b7 [X86] Simplify a multiclass to remove a parameter. NFC
llvm-svn: 271627
2016-06-03 05:30:56 +00:00
Derek Bruening a601c2ada2 [esan] Ensure internal_sigaction() bypasses interceptors
Summary:
Implements real_sigaction() which it turns out is required for
internal_sigaction() to bypass the libc interceptors.

Without real_sigaction(), our internal_sigaction() calls during init happen
to work due to the EsanDuringInit check in COMMON_INTERCEPTOR_ENTER (though
even here it does not feel right for an "internal_" call to go through the
interceptor).  The real problem is when we call internal_sigaction() after
we're initialized, which only happens on an unhandled SIGSEGV for which the
app has no handler: then we'll spin in an infinite loop as our attempts to
remove our own handler repeatedly fail.  It's not easy to add a test for
that, unfortunately.

Reviewers: aizatsky

Subscribers: vitalybuka, zhaoqin, kcc, eugenis, llvm-commits, kubabrecka

Differential Revision: http://reviews.llvm.org/D20832

llvm-svn: 271626
2016-06-03 04:30:47 +00:00
Craig Topper 2388b4610a [X86] Remove unnecessary pattern predicates from the vector bit cast patterns. The types have to be legal and there are no alternative patterns. Saves almost 200 bytes in isel table.
llvm-svn: 271625
2016-06-03 04:15:27 +00:00