1738c293b5
Fix the JIT encoding of VSEL
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llvm-svn: 27160
2006-03-27 03:34:17 +00:00
df59d5314c
Fix the JIT encoding of VSPLTI*
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llvm-svn: 27159
2006-03-27 03:28:57 +00:00
793cbcb4fd
Add all of the altivec comparison instructions. Add patterns for the
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non-predicate altivec compare intrinsics.
llvm-svn: 27143
2006-03-26 04:57:17 +00:00
53e07decd7
implement the vsldoi intrinsic.
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llvm-svn: 27139
2006-03-26 00:41:48 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
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llvm-svn: 26935
2006-03-22 01:44:36 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
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llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
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1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
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llvm-svn: 24874
2005-12-20 00:26:01 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
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void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
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hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
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llvm-svn: 24589
2005-12-04 18:42:54 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
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llvm-svn: 24492
2005-11-26 22:39:34 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
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Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
b439dad538
Allow pseudos to have patterns, no functionality change
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llvm-svn: 23988
2005-10-25 20:58:43 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
9f3c26c4ea
Write patterns for the various shl and srl patterns that don't involve
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doing something clever.
llvm-svn: 23824
2005-10-19 18:42:01 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
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llvm-svn: 23740
2005-10-14 23:40:39 +00:00
Chris Lattner