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23 Commits

Author SHA1 Message Date
Richard Barton 0fc56890ba Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures. 
llvm-svn: 155983
 2012-05-02 09:43:18 +00:00
Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints. 
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
 2012-04-27 23:51:36 +00:00
Jim Grosbach 5117ef7453 ARM: improved assembler diagnostics for missing CPU features. 
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

llvm-svn: 155499
 2012-04-24 22:40:08 +00:00
Jim Grosbach c14871cc67 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach 7a49575d7f Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
Jim Grosbach c3fc62b492 Update test for 141010. 
llvm-svn: 141022
 2011-10-03 20:58:08 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC. 
llvm-svn: 138360
 2011-08-23 19:49:10 +00:00
Jim Grosbach 6e546e0725 Thumb parsing and encoding for STR. 
Not including tSTRspi.

llvm-svn: 138347
 2011-08-23 18:33:38 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Jim Grosbach 5507203262 Fix think-o. 
llvm-svn: 138288
 2011-08-22 23:04:26 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Jim Grosbach 1b43828958 ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Jim Grosbach 2c21bf4b43 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00