Commit Graph

5 Commits

Author SHA1 Message Date
Duraid Madina f54c9395e7 remove RET hack, add proper support for rets (watching out for ret voids)
llvm-svn: 25486
2006-01-20 20:24:31 +00:00
Chris Lattner c17b41c3ba Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
llvm-svn: 25324
2006-01-14 22:27:21 +00:00
Duraid Madina 644e7db818 this is a hack, which may or may not hang around. In short:
whimper out of doing things the Right Way, and hack up a generic
'BRCALL' instruction, that gets generated when calls are lowered.
This gets selected by hand in the DAG isel, where it gets turned
into real (i.e. in tablegen) br.call instructions.

BUG: this dies on void calls, but seems to work otherwise?
llvm-svn: 24952
2005-12-22 13:29:14 +00:00
Duraid Madina b1d57fb175 we can't all have brains now, can we
llvm-svn: 24948
2005-12-22 06:41:39 +00:00
Duraid Madina f221c261f3 DAG->DAG instruction selection for ia64! "hello world" works, not much else.
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.

llvm-svn: 24058
2005-10-28 17:46:35 +00:00