llvm-project

Commit Graph

Author	SHA1	Message	Date
Alex Bradbury	d834d8301d	[RISCV] Add RV64F codegen support This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807	2019-01-31 22:48:38 +00:00
Alex Bradbury	d760910d3d	[RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll (fcopysign a, (fneg b)) will be expanded to bitwise operations by DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't legal. Arguably it might be worth doing a combine even if it is legal. llvm-svn: 352240	2019-01-25 21:06:47 +00:00
Alex Bradbury	38c4ec31cb	[RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines This target-independent code won't trigger for cases such as RV32FD where custom SelectionDAG nodes are generated. These new tests demonstrate such cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and fabs.s selection patterns are actually exercised. llvm-svn: 352199	2019-01-25 14:33:08 +00:00

Author

SHA1

Message

Date

Alex Bradbury

d834d8301d

[RISCV] Add RV64F codegen support

This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.

Differential Revision: https://reviews.llvm.org/D53235

llvm-svn: 352807

2019-01-31 22:48:38 +00:00

Alex Bradbury

d760910d3d

[RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll

(fcopysign a, (fneg b)) will be expanded to bitwise operations by
DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't
legal. Arguably it might be worth doing a combine even if it is legal.

llvm-svn: 352240

2019-01-25 21:06:47 +00:00

Alex Bradbury

38c4ec31cb

[RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines

This target-independent code won't trigger for cases such as RV32FD where
custom SelectionDAG nodes are generated. These new tests demonstrate such
cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and
fabs.s selection patterns are actually exercised.

llvm-svn: 352199

2019-01-25 14:33:08 +00:00

3 Commits