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180 Commits

Author SHA1 Message Date
Jim Grosbach 0b20fdaff0 Cosmetic cleanup. No functional change. 
llvm-svn: 104974
 2010-05-28 17:51:20 +00:00
Jim Grosbach 37eb2c24b9 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
llvm-svn: 104967
 2010-05-28 17:37:40 +00:00
Jim Grosbach faa3abbe39 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900
 2010-05-27 23:49:24 +00:00
Jim Grosbach a6897ecbb5 fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
llvm-svn: 104661
 2010-05-26 01:22:21 +00:00
Bob Wilson 4f48499d2c Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. 
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583
 2010-05-25 04:51:47 +00:00
Bob Wilson debbbe3fd9 Fix up instruction classes for Thumb2 RSB instructions to be consistent with 
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582
 2010-05-25 04:43:08 +00:00
Bob Wilson 91b2b8540c Allow Thumb2 MVN instructions to set condition codes. The immediate operand 
version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570
 2010-05-24 22:41:19 +00:00
Bob Wilson 3eb7691858 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531
 2010-05-24 18:44:06 +00:00
Evan Cheng daeca2d156 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
llvm-svn: 104115
 2010-05-19 07:28:01 +00:00
Evan Cheng dd7f566597 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng 2c452fcd14 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
llvm-svn: 104102
 2010-05-19 01:52:25 +00:00
Anton Korobeynikov 497d831966 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
llvm-svn: 103903
 2010-05-16 09:15:36 +00:00
Jim Grosbach 151cd8f159 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach 92d999001c Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Bob Wilson 0106063556 Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets 
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.

llvm-svn: 100892
 2010-04-09 20:41:18 +00:00
Bob Wilson d6243b49d4 Remove the writeback flag from ARM's address mode 4. Now that we have separate 
instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643
 2010-03-16 17:46:45 +00:00
Bob Wilson 947f04bad0 Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
 2010-03-13 01:08:20 +00:00
Johnny Chen c1d1229d78 Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm, 
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.

llvm-svn: 98285
 2010-03-11 21:02:50 +00:00
Johnny Chen f5e81aeba5 Added Thumb2 LDRD/STRD pre/post variants for disassembly only. 
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).

llvm-svn: 98217
 2010-03-11 01:13:36 +00:00
Johnny Chen 9a3e2398ae Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero 
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172
 2010-03-10 18:59:38 +00:00
Johnny Chen 15804db55c MSR (Move to Special Register from ARM core register) requires a mask to specify 
what fields of the CPSR or SPSR are affected.

llvm-svn: 98085
 2010-03-09 21:39:34 +00:00
Bob Wilson 0bfbd9b68c Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit 
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.

llvm-svn: 98001
 2010-03-08 22:56:15 +00:00
Johnny Chen 70e01cd001 Trivial comment change. 
llvm-svn: 97776
 2010-03-05 01:45:46 +00:00
Johnny Chen ece1797542 Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version 
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

llvm-svn: 97760
 2010-03-04 22:24:41 +00:00
Johnny Chen 334db0ce7f Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload 
Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.

llvm-svn: 97731
 2010-03-04 17:40:44 +00:00
Johnny Chen f1e25c7163 Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT, 
and STRHT for disassembly only.

llvm-svn: 97655
 2010-03-03 18:45:36 +00:00
Johnny Chen f1ea86b567 Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG 
for disassembly only.

llvm-svn: 97632
 2010-03-03 02:09:43 +00:00
Evan Cheng d8c50c67dc Eliminate unused instruction classes. 
llvm-svn: 97617
 2010-03-03 00:43:15 +00:00
Johnny Chen 334af68052 Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for 
disassembly only.

llvm-svn: 97614
 2010-03-03 00:16:28 +00:00
Johnny Chen 7041f2cef6 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only. 
llvm-svn: 97595
 2010-03-02 22:11:06 +00:00
Johnny Chen 9dc2105478 Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from 
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582
 2010-03-02 19:38:59 +00:00
Johnny Chen 44908a5e17 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL, 
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
 2010-03-02 18:14:57 +00:00
Johnny Chen 0dae1cbf1c AL is an optional mnemonic extension for always, except in IT instructions. 
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571
 2010-03-02 17:57:15 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Johnny Chen 38e7bb6f34 Added the follwoing 32-bit Thumb instructions for disassembly only: 
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]

llvm-svn: 97276
 2010-02-26 22:04:29 +00:00
Johnny Chen 3adff378cc Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE, 
and SRS.

llvm-svn: 97164
 2010-02-25 20:25:24 +00:00
Johnny Chen 871e5b0926 Added the 32-bit Thumb instructions (BXJ) for disassembly only. 
llvm-svn: 97163
 2010-02-25 19:05:29 +00:00
Johnny Chen e285f70a42 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only. 
llvm-svn: 97159
 2010-02-25 18:46:43 +00:00
Jim Grosbach 3e2cad3b1a 80 column cleanup 
llvm-svn: 96393
 2010-02-16 21:23:02 +00:00
Jim Grosbach fba7fce5be Remove trailing whitespace 
llvm-svn: 96388
 2010-02-16 21:07:46 +00:00
Jim Grosbach 2284ddab56 Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but 
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384
 2010-02-16 20:42:29 +00:00
Jim Grosbach a570d05228 tighten up eh.setjmp sequence a bit. 
llvm-svn: 95603
 2010-02-08 23:22:00 +00:00
Johnny Chen 8487d65ea2 Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field. 
llvm-svn: 95112
 2010-02-02 19:31:58 +00:00
Jim Grosbach 267430f74d Fix PR5694. The CMN instructions set the flags differently from CMP, so they 
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119
 2010-01-22 00:08:13 +00:00
Evan Cheng 6c0fb92c03 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. 
llvm-svn: 93829
 2010-01-19 00:44:15 +00:00
Jim Grosbach 8546ec9c14 Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
 2010-01-18 19:58:49 +00:00
Johnny Chen ab6e6819b2 Minor change, change the order of two "let Inst{...}" stmts within multiclass 
T2I_bin_ii12rs definition.

llvm-svn: 93006
 2010-01-08 17:41:33 +00:00
Johnny Chen 567945636f Undo r92785, it caused test failure. 
llvm-svn: 92796
 2010-01-05 22:37:28 +00:00
Johnny Chen a9f39bdbb6 Add Rt2 to the asm format string for 32-bit Thumb load/store register dual 
instructions.  Thumb does not have the restriction that t2 = t+1.

llvm-svn: 92785
 2010-01-05 21:51:46 +00:00
Jim Grosbach 69461f50c1 Mark STREX* as earlyclobber for the success result register. 
llvm-svn: 91555
 2009-12-16 19:44:06 +00:00