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376 Commits

Author SHA1 Message Date
Akira Hatanaka 33a25af5a8 Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering. 
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.

llvm-svn: 161076
 2012-07-31 20:54:48 +00:00
Akira Hatanaka beda2241a4 When store nodes or memcpy nodes are created to copy the function call 
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.

llvm-svn: 161068
 2012-07-31 18:46:41 +00:00
Akira Hatanaka 4ce7c4060d Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as 
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063
 2012-07-31 18:16:49 +00:00
Akira Hatanaka 97ba7696f8 Pass the correct call frame size to callseq_start node. This is needed to 
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.

llvm-svn: 160841
 2012-07-26 23:27:01 +00:00
Akira Hatanaka 64626fc20f Fix call setup for PIC. 
Patch by Reed Kotler.

llvm-svn: 160774
 2012-07-26 02:24:43 +00:00
Akira Hatanaka 26e9ecb7a3 Add basic ability to setup call frame, and make procedure calls. 
Hello world will compile and execute with this patch.

Patch by Reed Kotler.

llvm-svn: 160651
 2012-07-23 23:45:54 +00:00
Akira Hatanaka b49c68a65d Revert accidental commit. 
llvm-svn: 160598
 2012-07-21 02:20:33 +00:00
Akira Hatanaka f73e362758 Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind. 
Test case will be added later when long branch patch is checked in.

llvm-svn: 160597
 2012-07-21 02:15:19 +00:00
Akira Hatanaka 24cf4e36e5 Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. 
llvm-svn: 160064
 2012-07-11 19:32:27 +00:00
Akira Hatanaka 878ad8b28d Lower RETURNADDR node in Mips backend. 
Patch by Sasa Stankovic.

llvm-svn: 160031
 2012-07-11 00:53:32 +00:00
Akira Hatanaka efff7b763b Make register Mips::RA allocatable if not in mips16 mode. 
llvm-svn: 159971
 2012-07-10 00:19:06 +00:00
Jack Carter b353094f27 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159625
 2012-07-02 23:35:23 +00:00
Eric Christopher dfc3e68c40 Revert " mips32 long long register inline asm constraint support." as 
it appears to be breaking the bots.

This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.

llvm-svn: 159619
 2012-07-02 23:22:25 +00:00
Jack Carter 5c1a01a625 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159610
 2012-07-02 22:39:45 +00:00
Akira Hatanaka 5fd22485a3 Fix coding style violations. Remove white spaces and tabs. 
llvm-svn: 158471
 2012-06-14 21:10:56 +00:00
Akira Hatanaka df5205ef3d Implement a DAGCombine in MipsISelLowering.cpp which transforms the following 
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419
 2012-06-13 20:33:18 +00:00
Akira Hatanaka 1daf8c2a16 Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. 
llvm-svn: 158414
 2012-06-13 19:33:32 +00:00
Akira Hatanaka 9586618c58 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. 
llvm-svn: 158413
 2012-06-13 19:06:08 +00:00
Akira Hatanaka f0273603f5 Implement fastcc calling convention for MIPS. 
llvm-svn: 158410
 2012-06-13 18:06:00 +00:00
Akira Hatanaka 6734685f21 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.

llvm-svn: 157937
 2012-06-04 17:46:29 +00:00
Hans Wennborg 245917b536 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
 2012-06-04 14:02:08 +00:00
Chris Lattner 58268c23ac remove an unused variable. 
llvm-svn: 157872
 2012-06-02 01:03:42 +00:00
Akira Hatanaka 019e592f75 Set operation actions for load/store nodes in the Mips backend. 
llvm-svn: 157866
 2012-06-02 00:04:42 +00:00
Akira Hatanaka 8f1db778a4 Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.

llvm-svn: 157864
 2012-06-02 00:03:49 +00:00
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes. 
llvm-svn: 157863
 2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
 2012-06-02 00:02:45 +00:00
Akira Hatanaka bff8e31d3c Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
 2012-05-31 02:59:44 +00:00
Justin Holewinski aa58397b3c Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
 2012-05-25 16:35:28 +00:00
Akira Hatanaka f542ebd958 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
 2012-05-12 03:19:04 +00:00
Akira Hatanaka 0a8ab718cb Expand 64-bit shifts if target ABI is O32. 
llvm-svn: 156457
 2012-05-09 00:55:21 +00:00
Eric Christopher 0d8c15d20f Add support for the 'x' constraint. 
Patch by Jack Carter.

llvm-svn: 156295
 2012-05-07 06:25:19 +00:00
Eric Christopher 9c492e6ebf Add support for the 'l' constraint. 
Patch by Jack Carter.

llvm-svn: 156294
 2012-05-07 06:25:15 +00:00
Eric Christopher e3c494de82 Add support for the 'c' constraint. 
Patch by Jack Carter.

llvm-svn: 156293
 2012-05-07 06:25:10 +00:00
Eric Christopher c18ae4a3b1 Add support for the 'P' constraint. 
Patch by Jack Carter.

llvm-svn: 156292
 2012-05-07 06:25:02 +00:00
Eric Christopher 470578a91b Add support for the 'O' constraint. 
Patch by Jack Carter.

llvm-svn: 156285
 2012-05-07 05:46:48 +00:00
Eric Christopher e07aa430b8 Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156284
 2012-05-07 05:46:43 +00:00
Eric Christopher 1109b3406d Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156283
 2012-05-07 05:46:37 +00:00
Eric Christopher 3ff88a05b7 Add support for the inline asm constraint 'K'. 
llvm-svn: 156282
 2012-05-07 05:46:29 +00:00
Eric Christopher 7201e1b4b9 Support the 'J' constraint. 
Patch by Jack Carter.

llvm-svn: 156280
 2012-05-07 03:13:42 +00:00
Eric Christopher 1d6c89eea1 Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
 2012-05-07 03:13:32 +00:00
Eric Christopher 58daf04681 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

llvm-svn: 156278
 2012-05-07 03:13:22 +00:00
Eric Christopher cfcd77b0bc When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
 2012-05-07 03:13:16 +00:00
Hans Wennborg aea412008e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi e30303fa86 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
 2012-04-21 15:31:45 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
llvm-svn: 155188
 2012-04-20 07:30:17 +00:00
Akira Hatanaka 47ad674f67 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.

llvm-svn: 154546
 2012-04-11 22:59:08 +00:00
Akira Hatanaka 7f4c9d1429 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
 2012-04-11 22:49:04 +00:00
Akira Hatanaka 4f5c8421b3 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540
 2012-04-11 22:13:04 +00:00
Akira Hatanaka 121342fcc2 Reapply 154038 without the failing test. 
llvm-svn: 154062
 2012-04-04 22:16:36 +00:00
Owen Anderson 4743c6e159 Revert r154038. It was causing make check failures. 
llvm-svn: 154054
 2012-04-04 21:18:58 +00:00