97f6ea9f34
Typo.
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llvm-svn: 161826
2012-08-14 01:09:10 +00:00
245920463d
llvm/test/CodeGen/ARM/floorf.ll: Add explicit -mtriple=arm-unknown-unknown, or it fails on msvc.
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llvm-svn: 161825
2012-08-14 00:56:06 +00:00
a40319b7f1
Add a roundToIntegral method to APFloat, which can be parameterized over various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC.
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llvm-svn: 161807
2012-08-13 23:32:49 +00:00
396b595b92
Transfer weights in transferSuccessorsAndUpdatePHIs().
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llvm-svn: 161805
2012-08-13 23:13:25 +00:00
1dc107a84e
Print out MachineBasicBlock successor weights when available.
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llvm-svn: 161804
2012-08-13 23:13:23 +00:00
8d80452076
LICM uses AliasSet information to hoist and sink instructions. However, other passes, such as LoopRotate
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may invalidate its AliasSet because SSAUpdater does not update the AliasSet properly.
This patch teaches SSAUpdater to notify AliasSet that it made changes.
The testcase in PR12901 is too big to be useful and I could not reduce it to a normal size.
rdar://11872059 PR12901
llvm-svn: 161803
2012-08-13 23:06:54 +00:00
5d4e205874
MemoryDependenceAnalysis attempts to find the first memory dependency for function calls.
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Currently, if GetLocation reports that it did not find a valid pointer (this is the case for volatile load/stores),
we ignore the result. This patch adds code to handle the cases where we did not obtain a valid pointer.
rdar://11872864 PR12899
llvm-svn: 161802
2012-08-13 23:03:43 +00:00
b4e1ba7191
ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.
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These tests weren't actually being run before (missing ':' after CHECK).
llvm-svn: 161800
2012-08-13 22:25:44 +00:00
702bcc3bcf
Remove the TII::scheduleTwoAddrSource() hook.
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It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.
The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.
When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.
llvm-svn: 161794
2012-08-13 21:52:57 +00:00
72baa6eeae
Rename test since it's not linux-specific.
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llvm-svn: 161792
2012-08-13 21:32:42 +00:00
d6c8270eaa
ARM: enable struct byval for AAPCS-VFP.
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This change is to be enabled in clang.
rdar://9877866
llvm-svn: 161789
2012-08-13 21:22:50 +00:00
49aeb5cc5d
Whitespace cleanup.
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llvm-svn: 161788
2012-08-13 21:20:43 +00:00
d0af1d9657
Count triangles and diamonds in early if-conversion.
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llvm-svn: 161783
2012-08-13 21:03:27 +00:00
62a097d134
Delete dead typedef.
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llvm-svn: 161782
2012-08-13 21:03:25 +00:00
83a927d84a
Handle extra Tail predecessors in if-conversion.
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It is still possible to if-convert if the tail block has extra
predecessors, but the tail phis must be rewritten instead of being
removed.
llvm-svn: 161781
2012-08-13 20:49:04 +00:00
0bb7f23cfc
[Hexagon] Don't mark callee saved registers as clobbered by a tail call
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This was causing unnecessary spills/restores of callee saved registers.
Fixes PR13572.
Patch by Pranav Bhandarkar!
llvm-svn: 161778
2012-08-13 19:54:01 +00:00
9746b33e26
Fix failure on Atom bot due to r161769
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llvm-svn: 161777
2012-08-13 19:34:29 +00:00
3a94c545cf
Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISDNode has more than one user.
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rdar://11876519
llvm-svn: 161775
2012-08-13 18:52:44 +00:00
959acb106b
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from
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OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed
to a memory operand.
PR13576
llvm-svn: 161769
2012-08-13 18:29:41 +00:00
7d8b53c1f8
Add support for the %H output modifier.
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Patch by Weiming Zhao.
llvm-svn: 161768
2012-08-13 18:18:52 +00:00
e90e94f117
X86: when auto-detecting the subtarget features, make sure use IsIntel to detect
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Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6.
llvm-svn: 161763
2012-08-13 17:26:46 +00:00
402685a881
Fix a documentation typo.
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llvm-svn: 161758
2012-08-13 15:29:53 +00:00
0f7a80d0c3
[asan] remove the code for --asan-merge-callbacks as it appears to be a bad idea. (partly related to Bug 13225)
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llvm-svn: 161757
2012-08-13 14:08:46 +00:00
8c724a758b
Added test for non-static use of cl::opt (fixed in r160170)
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llvm-svn: 161751
2012-08-13 10:43:36 +00:00
b4abb84d9c
Add test for previous commit correcting NEON load patterns.
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llvm-svn: 161750
2012-08-13 10:38:45 +00:00
5aaa7fde94
Use correct loads for vector types during extending-load operations.
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Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit
accesses being selected, so we need to use an appropriate width load in those
cases.
llvm-svn: 161748
2012-08-13 09:06:31 +00:00
4e5eb72735
Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and putting an a couple if conditions in a better order.
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llvm-svn: 161746
2012-08-13 03:42:38 +00:00
5145a0d967
Refactor code a bit to share commonalities. No functional change intended.
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llvm-svn: 161745
2012-08-13 02:34:03 +00:00
ff6e4d1928
Fix an unused variable warning from r161742.
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llvm-svn: 161743
2012-08-13 01:26:45 +00:00
a7aaa62d54
Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result.
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llvm-svn: 161742
2012-08-13 01:23:55 +00:00
1dcfe449ef
Give this test an explicit triple.
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llvm-svn: 161740
2012-08-12 08:21:27 +00:00
333449cd65
When emitting the PC range in an FDE, use the same data encoding for both ends
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of the range. Fixes PR13581!
llvm-svn: 161739
2012-08-12 08:09:45 +00:00
3d2b271362
Remove call to setOperationAction for SETCC of v4f32. SETCC returns an integer type not an FP type.
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llvm-svn: 161738
2012-08-12 05:31:32 +00:00
498228d089
Remove unnecessary call to setOperationAction for SETCC of v2i64 under SSE42. It was already called for the same under SSE2.
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llvm-svn: 161737
2012-08-12 05:15:16 +00:00
b73da9453c
Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
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architecture
It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.
llvm-svn: 161736
2012-08-12 05:11:56 +00:00
4fa625fda7
Change addTypeForNeon to use MVT instead of EVT so all the calls to getSimpleVT can be removed.
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llvm-svn: 161735
2012-08-12 03:16:37 +00:00
10a8bf3b8c
Make replace many calls to getSizeInBits() with is128BitVector/is256BitVector
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llvm-svn: 161734
2012-08-12 02:23:29 +00:00
03d2787275
Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation actions. Compiles to smaller code.
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llvm-svn: 161733
2012-08-12 00:34:56 +00:00
e7e828fd64
fix PR13577, an issue introduced by r161687
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- FCMOV only supports a subset of X86 conditions. Skip boolean
simplification if X86 condition is not valid for FCMOV.
- add a minimal test case for PR13577.
llvm-svn: 161732
2012-08-11 23:47:06 +00:00
b03a84c13e
Create isXBitVector methods in MVT and call them from EVT. This allows targets to call them with an MVT without needing to convert to EVT.
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llvm-svn: 161731
2012-08-11 23:31:18 +00:00
b5bcf58ba1
Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop since all 256-bit types are supported.
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llvm-svn: 161730
2012-08-11 22:34:26 +00:00
59c8b411e0
MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already.
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llvm-svn: 161729
2012-08-11 20:42:59 +00:00
ef6494f24d
PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.
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This is common e.g. when doing rip-relative addressing on x86_64.
llvm-svn: 161728
2012-08-11 19:05:13 +00:00
490c45c06c
Tidy up indentation. No functional change.
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llvm-svn: 161727
2012-08-11 17:53:00 +00:00
55406d9f78
Fix a cast that was casting away 'const' unnecessarily
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llvm-svn: 161726
2012-08-11 17:46:16 +00:00
22cb0c572b
Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.
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llvm-svn: 161725
2012-08-11 17:44:14 +00:00
1acb6707cd
X86: when we are auto-detecting the subtarget features, make sure we turn on
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FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.
FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.
rdar: 7252306
llvm-svn: 161717
2012-08-10 23:43:32 +00:00
bc55bfde03
Add a proper if-conversion cost model.
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Detect when there is not enough available ILP, so if-conversion can't
speculate instructions for free.
Compute the lengthening of the critical path when inserting a select
instruction that depends on the condition as well as both sides of the
if.
Reject conversions that would stretch the critical path by more than
half a mispredict penalty.
llvm-svn: 161713
2012-08-10 22:27:31 +00:00
a0042acd3b
Give MachineTraceMetrics its own debug tag.
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llvm-svn: 161712
2012-08-10 22:27:29 +00:00
3484420927
Add more trace query functions.
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Trace::getResourceLength() computes the number of cycles required to
execute the trace when ignoring data dependencies. The number can be
compared to the critical path to estimate the trace ILP.
Trace::getPHIDepth() computes the data dependency depth of a PHI in a
trace successor that isn't necessarily part of the trace.
llvm-svn: 161711
2012-08-10 22:27:27 +00:00
Eric Christopher