llvm-project

Commit Graph

Author	SHA1	Message	Date
Elvina Yakubova	b36a3e6140	[llvm-readobj] Update tests because of changes in llvm-readobj behavior This patch updates tests using llvm-readobj and llvm-readelf, because soon reading from stdin will be achievable only via a '-' as described here: https://bugs.llvm.org/show_bug.cgi?id=46400. Patch with changes to llvm-readobj behavior is here: https://reviews.llvm.org/D83704 Differential Revision: https://reviews.llvm.org/D83912 Reviewed by: jhenderson, MaskRay, grimar	2020-07-20 10:39:04 +01:00
Simon Atanasyan	7bed381eae	[mips] Implement Octeon+ `saa` and `saad` instructions `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849	2019-11-07 13:58:50 +03:00
Simon Atanasyan	11766558d7	[mips] Fix relocation record format and ELF header for N32 ABI The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's encoding, and uses ELFCLASS32. This change passes the `IsN32` flag to the `MCAsmBackend` to distinguish usage of N32 ABI. We still do not handle some cases like providing the `-target-abi=o32` command line option with the `mips64` target triple. That's why elf_header.s contains some "FIXME" strings. This case will be fixed in a separate patch. Differential revision: https://reviews.llvm.org/D37960 llvm-svn: 313873	2017-09-21 10:44:26 +00:00

Author

SHA1

Message

Date

Elvina Yakubova

b36a3e6140

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

This patch updates tests using llvm-readobj and llvm-readelf, because
soon reading from stdin will be achievable only via a '-' as described
here: https://bugs.llvm.org/show_bug.cgi?id=46400. Patch with changes to
llvm-readobj behavior is here: https://reviews.llvm.org/D83704

Differential Revision: https://reviews.llvm.org/D83912

Reviewed by: jhenderson, MaskRay, grimar

2020-07-20 10:39:04 +01:00

Simon Atanasyan

7bed381eae

[mips] Implement Octeon+ `saa` and `saad` instructions

`saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

   memory[base] = memory[base] + rt

These instructions are available for "Octeon+" CPU. The patch adds support
for both instructions to MIPS assembler and diassembler and introduces new
CPU type - "octeon+".

Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP`
ISA extension flag support.

Differential Revision: https://reviews.llvm.org/D69849

2019-11-07 13:58:50 +03:00

Simon Atanasyan

11766558d7

[mips] Fix relocation record format and ELF header for N32 ABI

The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's
encoding, and uses ELFCLASS32. This change passes the `IsN32` flag
to the `MCAsmBackend` to distinguish usage of N32 ABI.

We still do not handle some cases like providing the `-target-abi=o32`
command line option with the `mips64` target triple. That's why
elf_header.s contains some "FIXME" strings. This case will be fixed in
a separate patch.

Differential revision: https://reviews.llvm.org/D37960

llvm-svn: 313873

2017-09-21 10:44:26 +00:00

3 Commits