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Author SHA1 Message Date
Andrew Trick 8f6b8a5596 Add missing REQUIRES: asserts in crash.ll. 
llvm-svn: 184576
 2013-06-21 18:47:08 +00:00
Michael Liao 62ebfd8786 Fix PR16360 
When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the
high bits are not cleared. Add 'and' to clear off them.

llvm-svn: 184575
 2013-06-21 18:45:27 +00:00
Andrew Trick 5749b8be01 Update physreg live intervals during remat. 
llvm-svn: 184574
 2013-06-21 18:33:26 +00:00
Ulrich Weigand 91add7dfbf [PowerPC] Support R_PPC_REL16 family of relocations 
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:

  li 1, base-.

This patch adds support for those relocation types in the assembler.

llvm-svn: 184552
 2013-06-21 14:44:37 +00:00
Ulrich Weigand 876a0d0133 [PowerPC] Support various tls-related modifiers 
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code.  This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.

llvm-svn: 184551
 2013-06-21 14:44:15 +00:00
Ulrich Weigand e9126f5534 [PowerPC] Support @higher et.al. modifiers 
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.

llvm-svn: 184550
 2013-06-21 14:43:42 +00:00
Ulrich Weigand 72ddbd656e [PowerPC] Support @toc@h modifier 
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.

llvm-svn: 184549
 2013-06-21 14:43:10 +00:00
Ulrich Weigand e67c565dc1 [PowerPC] Support @h modifier 
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).

This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.

llvm-svn: 184548
 2013-06-21 14:42:49 +00:00
Manuel Klimek a192ea204b Fix an ordering problem in the test. 
The output can be in different orders, which breaks the test in some
situations. I have not yet found out what the root cause of the order
difference is. This fixes our internal build. If it is not the right
solution, feel free to roll back.

llvm-svn: 184535
 2013-06-21 07:23:14 +00:00
Sean Silva c4afa6d7ae [yaml2obj][ELF] Allow expressing undefined symbols. 
Previously we unconditionally enforced that section references in
symbols in the YAML had a name that was a section name present in the
object, and linked the references to that section. Now, permit empty
section names (already the default, if the `Section` key is not
provided) to indicate SHN_UNDEF.

llvm-svn: 184513
 2013-06-21 01:11:48 +00:00
Sean Silva aff5125f88 [yaml2obj][ELF] Don't explicitly set `Binding` with STB_* 
Instead, just have 3 sub-lists, one for each of
{STB_LOCAL,STB_GLOBAL,STB_WEAK}.

This allows us to be a lot more explicit w.r.t. the symbol ordering in
the object file, because if we allowed explicitly setting the STB_*
`Binding` key for the symbol, then we might have ended up having to
shuffle STB_LOCAL symbols to the front of the list, which is likely to
cause confusion and potential for error.

Also, this new approach is simpler ;)

llvm-svn: 184506
 2013-06-21 00:27:50 +00:00
Quentin Colombet 663150f637 ARM: Remove a (false) dependency on the memoryoperand's value as we do not use 
it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.

<rdar://problem/13978317>

llvm-svn: 184492
 2013-06-20 22:51:44 +00:00
Kevin Enderby 35fd79237f Update the X86 disassembler to use xacquire and xrelease when appropriate. 
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859

llvm-svn: 184490
 2013-06-20 22:32:18 +00:00
Tom Stellard 96d38760fc R600/SI: Expand sub for v2i32 and v4i32 for SI 
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184482
 2013-06-20 21:55:37 +00:00
Tom Stellard 043795e818 R600/SI: Expand add for v2i32 and v4i32 
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184481
 2013-06-20 21:55:30 +00:00
Tom Stellard 6ec9e8043c R600: Expand v2i32 load/store instead of custom lowering 
The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184480
 2013-06-20 21:55:23 +00:00
Sean Silva 05001b9f38 [yaml2obj][ELF] Add support for st_value and st_size. 
After this patch, the ELF file produced by
`yaml2obj-elf-symbol-basic.yaml`, when linked and executed on x86_64
(under SysV ABI, obviously; I tested on Linux), produces a working
executable that goes into an infinite loop!

llvm-svn: 184469
 2013-06-20 20:59:47 +00:00
Sean Silva 98186220be [yaml2obj][ELF] Allow symbols to reference sections. 
llvm-svn: 184468
 2013-06-20 20:59:41 +00:00
Rafael Espindola b0c3cac2ed Use only the filename when deciding if a file is a duplicate. 
Matches gnu ar behavior.

llvm-svn: 184448
 2013-06-20 18:30:37 +00:00
Joey Gouly f81d036ea7 This reverts r155000. 
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.

llvm-svn: 184445
 2013-06-20 17:42:36 +00:00
Nadav Rotem 14a89c5428 SLPVectorization: Add a basic support for cross-basic block slp vectorization. 
We collect gather sequences when we vectorize basic blocks. Gather sequences are excellent
hints for vectorization of other basic blocks.

llvm-svn: 184444
 2013-06-20 17:41:45 +00:00
David Blaikie 8300e12991 Give this X86-specific test a triple so it's actually X86-specific. 
llvm-svn: 184443
 2013-06-20 17:31:32 +00:00
Ulrich Weigand d412098f43 [MC] Support @ variants with directional labels 
The assembler parser common code supports recognizing symbol variants
using the @ modifer.  On PowerPC, it should also be possible to use
(some of) those modifiers with directional labels, like "1f@l".

This patch adds support for accepting symbol variants on directional
labels as well.

llvm-svn: 184437
 2013-06-20 16:24:17 +00:00
Ulrich Weigand 96e6578395 [PowerPC] Optimize @ha/@l constructs 
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.

This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions.  However,
those target expression were used only on Darwin targets.

This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.

It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers.  The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
 

llvm-svn: 184436
 2013-06-20 16:23:52 +00:00
Ulrich Weigand 865a1efc13 [PowerPC] Support compare mnemonics with implied CR0 
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+

llvm-svn: 184435
 2013-06-20 16:15:12 +00:00
Rafael Espindola cb4f11696b Make sure ar is creating a new file instead of updating an existing one. 
Should fix the bots that are seeing a corrupted file from a previous run.

llvm-svn: 184424
 2013-06-20 13:44:49 +00:00
Rafael Espindola 789c129a9f Add r184420 back, but also handle long file names. 
Original message:

Don't include directory names in archives.

This matches the behavior of both gnu and os x versions of ar.

llvm-svn: 184423
 2013-06-20 13:41:51 +00:00
Rafael Espindola 73dd376467 Revert "Don't include directory names in archives." 
This reverts commit 184420.
Investigating the bot failures.

llvm-svn: 184421
 2013-06-20 13:23:48 +00:00
Rafael Espindola 2a65c32094 Don't include directory names in archives. 
This matches the behavior of both gnu and os x versions of ar.

llvm-svn: 184420
 2013-06-20 13:16:44 +00:00
Vladimir Medic 8cd1710e50 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
llvm-svn: 184411
 2013-06-20 11:21:49 +00:00
David Blaikie ea2605dc1a DebugInfo: don't use location lists when the location covers the whole function anyway 
Fix up three tests - one that was relying on abbreviation number,
another relying on a location list in this case (& testing raw asm,
changed that to use dwarfdump on the debug_info now that that's where
the location is), and another which was added in r184368 - exposing a
bug in that fix that is exposed when we emit the location inline rather
than through a location list. Fix that bug while I'm here.

llvm-svn: 184387
 2013-06-20 00:25:24 +00:00
David Blaikie 8c3880b907 Spelling correction 
llvm-svn: 184370
 2013-06-19 22:00:13 +00:00
David Blaikie 81a4dc75e9 DebugInfo: PR14763/r183329 correct the location of indirect parameters 
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

llvm-svn: 184368
 2013-06-19 21:55:13 +00:00
David Blaikie b9a18708cc Spell correct (s/begining/beginning/) 
llvm-svn: 184362
 2013-06-19 21:42:05 +00:00
David Blaikie 18e73508c4 llvm-dwarfdump: Add support for dumping the .debug_loc section 
This is a basic implementation - we still don't have any support (that I
know of) for dumping DWARF expressions in a meaningful way, so the
location information itself is just printed as a sequence of bytes as we
do elsewhere.

llvm-svn: 184361
 2013-06-19 21:37:13 +00:00
Ulrich Weigand 64f440518b [MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives 
The compiler occasionally generates multiple .loc directives in a row
(at the same instruction address).  These need to be transformed into
multple actual .debug_line table entries, since they are used to signal
certain information to the debugger (e.g. if the opening brace of a
function body is on the same line as the declaration).

The MCAsmStreamer version of EmitDwarfLocDirective handles this
correctly by emitting a .loc directive every time it is called.
However, the MCObjectStream version simply defaults to recording
the information and emitting only a single table entry later,
e.g. when EmitInstruction is called.

This patch introduces a MCAsmStreamer::EmitDwarfLocDirective
version that emits a line table entry for a .loc directive
that may already be pending before recording the new directive.
(This is similar to how this is handled in GNU as.)

With this patch (and the code alignment factor patch) applied,
I'm now getting identical DWARF .debug sections for all test-suite
object files on PowerPC for the internal and the external assembler.

llvm-svn: 184357
 2013-06-19 21:27:27 +00:00
Matt Arsenault d46fce1141 Move StructurizeCFG out of R600 to generic Transforms. 
Register it with PassManager

llvm-svn: 184343
 2013-06-19 20:18:24 +00:00
Quentin Colombet 145eb97d3a LSR: Fix the parameters used to compute the scaling factor cost. 
Prior to this change, the considered addressing modes may be invalid since the
maximum and minimum offsets were not taking into account.
This was causing an assertion failure.

The added test case exercices that behavior.

<rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal
addressing mode has an illegal cost!")

llvm-svn: 184341
 2013-06-19 19:59:41 +00:00
Nadav Rotem 1e9668ea81 SLPVectorizer: handle scalars that are extracted from vectors (using ExtractElementInst). 
llvm-svn: 184325
 2013-06-19 17:33:16 +00:00
Nadav Rotem 86e848c849 SLPVectorizer: start constructing chains at stores that are not power of two. 
The type <3 x i8> is a common in graphics and we want to be able to vectorize it.

This changes accelerates bullet by 12% and 471_omnetpp by 5%.

llvm-svn: 184317
 2013-06-19 15:57:29 +00:00
Rafael Espindola 3703fd0d6f Remove the 'R' modifier. 
It is not present in GNU or OS X versions and doesn't make a lot of sense
for llvm-ar.

llvm-svn: 184306
 2013-06-19 14:58:16 +00:00
Nadav Rotem e98da7f548 SLPVectorizer: vectorize compares and selects. 
llvm-svn: 184282
 2013-06-19 05:49:52 +00:00
Sean Silva 56137cd483 [yaml2obj][ELF] Beef up this test a bit. 
llvm-svn: 184269
 2013-06-19 00:55:32 +00:00
Sean Silva 8432251a9f [yaml2obj][ELF] Support ELFOSABI_* enum. 
llvm-svn: 184268
 2013-06-19 00:55:28 +00:00
Sean Silva bba8559767 [yaml2obj][ELF] Support st_info through `Binding` and `Type` YAML keys. 
llvm-svn: 184263
 2013-06-19 00:11:59 +00:00
Sean Silva abe18db268 [yaml2obj][ELF] Ensure STN_UNDEF entry is present. 
llvm-svn: 184258
 2013-06-18 23:19:17 +00:00
Sean Silva 6b08388940 [yaml2obj][ELF] Rudimentary symbol table support. 
Currently, we only output the name.

llvm-svn: 184255
 2013-06-18 23:14:03 +00:00
Jim Grosbach a6ed57d8dd ARM: Add optional datatype suffix to NEON mvn asm syntax. 
rdar://14194152

llvm-svn: 184244
 2013-06-18 21:49:21 +00:00
Tim Northover 1806f938b5 AArch64: remove accidental test output file. 
llvm-svn: 184236
 2013-06-18 21:16:53 +00:00
Kevin Enderby c5d0935788 Change the arm assembler to support this from the v7c spec: 
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574

llvm-svn: 184224
 2013-06-18 20:19:24 +00:00