Commit Graph

35746 Commits

Author SHA1 Message Date
Manman Ren 53a54c41d7 CXX_FAST_TLS calling convention: fix issue on x86-64.
%RBP can't be handled explicitly. We generate the following code:
    pushq %rbp
    movq  %rsp, %rbp
    ...
    movq  %rbx, (%rbp)  ## 8-byte Spill
where %rbp will be overwritten by the spilled value.

The fix is to let PEI handle %RBP.
PR26136

llvm-svn: 257997
2016-01-16 16:39:46 +00:00
NAKAMURA Takumi 33ff1dda6a [Cygwin] Use -femulated-tls by default since r257718 introduced the new pass.
FIXME: Add more targets to use emutls into clang/test/Driver/emulated-tls.cpp.
FIXME: Add cygwin tests into llvm/test/CodeGen/X86. Working in progress.
llvm-svn: 257984
2016-01-16 03:44:52 +00:00
Dan Gohman 7f86ca1803 [WebAssembly] Add some more README.txt entries.
llvm-svn: 257969
2016-01-16 00:20:03 +00:00
Kevin B. Smith c831a08fbf [X86]: Make param names in header and body match for isCalleePop.
Differential Revision: http://reviews.llvm.org/D16246

llvm-svn: 257965
2016-01-16 00:08:36 +00:00
Dan Gohman 2f301f3e92 [WebAssembly] Don't create a needless .note.GNU-stack section
WebAssembly's stack will never be executable by default, so it isn't
necessary to declare .note.GNU-stack sections to request a non-executable
stack.

Differential Revision: http://reviews.llvm.org/D15969

llvm-svn: 257962
2016-01-15 23:59:13 +00:00
Artem Belevich 5be0706ebe [NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
llvm-svn: 257961
2016-01-15 23:57:53 +00:00
Manman Ren e5f807f928 CXX_FAST_TLS calling convention: fix issue on ARM.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

PR26136

llvm-svn: 257930
2016-01-15 20:24:11 +00:00
Manman Ren 4632e8e625 CXX_FAST_TLS calling convention: fix issue on AArch64.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

I will commit fixes to other platforms as well.

PR26136

llvm-svn: 257929
2016-01-15 20:13:28 +00:00
Manman Ren 4fe01bd8f9 CXX_FAST_TLS calling convention: fix issue on X86-64.
When we have a single basic block, the explicit copy-back instructions should
be inserted right before the terminator. Before this fix, they were wrongly
placed at the beginning of the basic block.

I will commit fixes to other platforms as well.

PR26136

llvm-svn: 257925
2016-01-15 19:35:42 +00:00
Kyle Butt 132bf36161 Codegen: [PPC] Silence false-positive initialization warning. NFC
Some compilers don't do exhaustive switch checking. For those compilers,
add an initialization to prevent un-initialized variable warnings from
firing. For compilers with exhaustive switch checking, we still get a
guarantee that the switch is exhaustive, and hence the initializations
are redundant, and a non-functional change.

llvm-svn: 257923
2016-01-15 19:20:06 +00:00
Reid Kleckner d4a0d18899 Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline"
This reverts commit r257883.

Somehow this didn't make it into r257916.

llvm-svn: 257919
2016-01-15 18:55:12 +00:00
Reid Kleckner 47f2452da8 # This is a combination of 2 commits.
# The first commit's message is:

Revert "[ARM] Add DSP build attribute and extension targeting"

This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc.

# This is the 2nd commit message:

Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline"

This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5.

llvm-svn: 257916
2016-01-15 18:31:29 +00:00
Krzysztof Parzyszek 2a3b2f9841 [Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
llvm-svn: 257891
2016-01-15 14:08:31 +00:00
Krzysztof Parzyszek 9b7320e621 [Hexagon] Handle DBG_VALUE instructions in copy-to-combine
llvm-svn: 257890
2016-01-15 13:55:57 +00:00
Bradley Smith 48b93e1f21 [ARM] Add DSP build attribute and extension targeting
llvm-svn: 257885
2016-01-15 10:28:25 +00:00
Bradley Smith 42f6e90a43 [ARM] Add new system registers to ARMv8-M Baseline/Mainline
llvm-svn: 257884
2016-01-15 10:28:03 +00:00
Bradley Smith 618712df04 [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/Mainline
llvm-svn: 257883
2016-01-15 10:27:14 +00:00
Bradley Smith 433c22e35c [ARM] Add ARMv8-A semaphore/atomic instructions to ARMv8-M Baseline/Mainline
llvm-svn: 257882
2016-01-15 10:26:51 +00:00
Bradley Smith a1189106d5 [ARM] Add B.W and CBZ instructions to ARMv8-M Baseline
llvm-svn: 257881
2016-01-15 10:26:17 +00:00
Bradley Smith 519563e371 [ARM] Add SDIV/UDIV instructions to ARMv8-M Baseline
llvm-svn: 257880
2016-01-15 10:25:35 +00:00
Bradley Smith d9a99ce53d [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/Mainline
llvm-svn: 257879
2016-01-15 10:25:14 +00:00
Bradley Smith e26f799422 [ARM] Add ARMv8-M Baseline/Mainline LLVM targeting
llvm-svn: 257878
2016-01-15 10:24:39 +00:00
Bradley Smith 4c21cba72b [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate features
llvm-svn: 257877
2016-01-15 10:23:46 +00:00
Jonas Paulsson 5b29e096ac [SystemZ] Fix bad instruction name
SLGBR -> SLBGR

Reviewed by Ulrich Weigand

llvm-svn: 257874
2016-01-15 07:12:09 +00:00
Pete Cooper 835594e627 Delete MCRelocationInfo::createExprForRelocation.
This method has no callers.

Also remove X86ELFRelocationInfo.cpp and X86MachORelocationInfo.cpp
which only existed to provide an implementation of that method.

Ok'd by Rafael and Jim.

llvm-svn: 257859
2016-01-15 02:24:12 +00:00
Weiming Zhao 038393bba0 Fix AArch64ConditionOptimizer
Summary:
This pass may modify the Cmp operands. However, the flag reg may be used by both the branch and CSEL.
Modifying CMP will have side effect on CSEL.

Reviewers: t.p.northover

Subscribers: llvm-commits, aemerson, rengolin

Differential Revision: http://reviews.llvm.org/D16147

llvm-svn: 257844
2016-01-15 00:06:58 +00:00
Krzysztof Parzyszek 0d11212f00 [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
llvm-svn: 257815
2016-01-14 21:59:22 +00:00
Krzysztof Parzyszek 5337a3e965 [Hexagon] Handle HVX registers in bit simplification
llvm-svn: 257811
2016-01-14 21:45:43 +00:00
Rui Ueyama da00f2fdf4 Update to use new name alignTo().
llvm-svn: 257804
2016-01-14 21:06:47 +00:00
Rafael Espindola c897cdde70 Handle offsets larger than 32 bits.
David Majnemer noticed that it was not obvious what the behavior would
be if B.Offset - A.Offset could not fit in an int.

llvm-svn: 257803
2016-01-14 21:03:06 +00:00
Rafael Espindola 56cb2734e3 Assert that a cmp function defines a total order.
Thanks to David Blaikie for noticing it.

llvm-svn: 257796
2016-01-14 20:28:25 +00:00
Krzysztof Parzyszek 237b96132d [Hexagon] Expand pseudo instruction Insert4
llvm-svn: 257771
2016-01-14 15:37:16 +00:00
Krzysztof Parzyszek b28ae10a16 [Hexagon] Handle branches with non-mbb operands
llvm-svn: 257768
2016-01-14 15:05:27 +00:00
Benjamin Kramer fc1f7d893e [ARM] Use the efficient version of BitVector::set and a static_assert.
No functional change intended.

llvm-svn: 257766
2016-01-14 14:33:04 +00:00
Igor Breger fc96331d88 AVX512: VMOVDQA32/64 (load) intrinsic implementation.
Differential Revision: http://reviews.llvm.org/D16142

llvm-svn: 257749
2016-01-14 07:56:04 +00:00
Ahmed Bougacha dfc77357a0 [AArch64] Don't assume extractelt constant index when matching shuffle.
llvm-svn: 257735
2016-01-14 02:12:30 +00:00
JF Bastien d1bd129d00 WebAssembly: mark a few new failures
A recent change introduced this assertion failure in some corner cases.

Repro:
mkdir /s/wasm/torture-out ; time /s/wasm/waterfall/src/compile_torture_tests.py --c /s/llvm/out/bin/clang --cxx /s/llvm/out/bin/clang++ --testsuite /s/gcc/gcc/testsuite --fails /s/llvm/llvm/lib/Target/WebAssembly/known_gcc_test_failures.txt --out /s/wasm/torture-out

Or look on the wasm integration bot:
https://build.chromium.org/p/client.wasm.llvm/console

llvm-svn: 257733
2016-01-14 01:49:22 +00:00
David Majnemer 3463e696fb [X86] Don't alter HasOpaqueSPAdjustment after we've relied on it
We rely on HasOpaqueSPAdjustment not changing after we've calculated
things based on it.  Things like whether or not we can use 'rep;movs' to
copy bytes around, that sort of thing.  If it changes, invariants in the
backend will quietly break.  This situation arose when we had a call to
memcpy *and* a COPY of the FLAGS register where we would attempt to
reference local variables using %esi, a register that was clobbered by
the 'rep;movs'.

This fixes PR26124.

llvm-svn: 257730
2016-01-14 01:20:03 +00:00
JF Bastien 664fd461c2 WebAssembly: fix build break introduced by ELFObjectWriter churn
llvm-svn: 257709
2016-01-13 23:36:00 +00:00
Rafael Espindola 8340f94df1 Convert a few assert failures into proper errors.
Fixes PR25944.

llvm-svn: 257697
2016-01-13 22:56:57 +00:00
Krzysztof Parzyszek a61f7da6ba [Hexagon] Fix the options controlling jump table generation
llvm-svn: 257679
2016-01-13 21:43:13 +00:00
Changpeng Fang c16be00313 AMDGPU/SI: Update ISA version for FIJI
llvm-svn: 257666
2016-01-13 20:39:25 +00:00
Dan Gohman a39ca60126 [WebAssembly] Add an assertion to catch unexpected MCFixupKindInfo flags.
llvm-svn: 257657
2016-01-13 19:31:57 +00:00
Dan Gohman 938ff9f0aa [WebAssembly] MCFixupKindInfo's TargetSize is in bits rather than bytes.
llvm-svn: 257655
2016-01-13 19:29:37 +00:00
Hans Wennborg 81efb6b418 Fix struct/class mismatch for MachineSchedContext
llvm-svn: 257648
2016-01-13 18:59:45 +00:00
Marek Olsak 46dadbfab2 AMDGPU/SI: Fix a GPU hang with POS_W_FLOAT enabled
Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16037

llvm-svn: 257625
2016-01-13 17:23:20 +00:00
Marek Olsak 3c0ebc71f1 AMDGPU/SI: Remove ending s_endpgm from non-void functions
Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16035

llvm-svn: 257623
2016-01-13 17:23:12 +00:00
Marek Olsak 8e9cc63bfb AMDGPU/SI: Add s_waitcnt at the end of non-void functions
Summary:
v2: Make ReturnsVoid private, so that I can another 8 lines of code and
    look more productive.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16034

llvm-svn: 257622
2016-01-13 17:23:09 +00:00
Marek Olsak 8a0f335ad6 AMDGPU/SI: Add support for non-void functions
Summary:
Return values can be stored in SGPRs (i32) and VGPRs (f32).

This will be used by functions which expect some bytecode or other binary to
be appended at the end. It allows defining in which registers the return
values will be stored.

v2: don't do this for compute shaders

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16033

llvm-svn: 257621
2016-01-13 17:23:04 +00:00
Derek Schuff 9c3bf3187a [WebAssemly] Invalidate liveness in CFG stackifier
WebAssemblyCFGStackify does not track liveness for EXPR_STACK, causing
verifier failure if liveness has not already been invalidated.

llvm-svn: 257620
2016-01-13 17:10:28 +00:00