Commit Graph

3865 Commits

Author SHA1 Message Date
Marcin Koscielnicki a46fade624 [Builtin] Make __builtin_thread_pointer target-independent.
This is now supported for ARM, AArch64, PowerPC, SystemZ, SPARC, Mips.

Differential Revision: http://reviews.llvm.org/D19589

llvm-svn: 272893
2016-06-16 13:41:54 +00:00
Sanjay Patel 280cfd1a69 [x86] translate SSE packed FP comparison builtins to IR
As noted in the code comment, a potential follow-on would be to remove
the builtins themselves. Other than ord/unord, this already works as 
expected. Eg:

  typedef float v4sf __attribute__((__vector_size__(16)));
  v4sf fcmpgt(v4sf a, v4sf b) { return a > b; }

Differential Revision: http://reviews.llvm.org/D21268

llvm-svn: 272840
2016-06-15 21:20:04 +00:00
Sanjay Patel 7495ec026e [x86] generate IR for SSE integer min/max builtins
Sibling patch to r272806:
http://reviews.llvm.org/rL272806

llvm-svn: 272807
2016-06-15 17:18:50 +00:00
Ranjeet Singh d48760da64 Reverting r272777 because one of the tests
added in the llvm patch is causing an assertion
to fail.

llvm-svn: 272790
2016-06-15 14:21:28 +00:00
Craig Topper a54c21e742 [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.
llvm-svn: 272787
2016-06-15 14:06:34 +00:00
Ranjeet Singh 8d5ad5bdf2 [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Patch adds intrinsics for mrrc/mrrc2. The
intrinsics for mrrc/mrrc2 return a single
uint64_t to represent two 32 bit values.

The mcrr/mcrr2 intrinsic was changed to
accept a single uint64_t instead of two
32 bit values as the input for consistency.

Differential Revision: http://reviews.llvm.org/D21179

llvm-svn: 272777
2016-06-15 11:32:18 +00:00
Peter Collingbourne bcf909d737 Update clang for D20348
Differential Revision: http://reviews.llvm.org/D20339

llvm-svn: 272710
2016-06-14 21:02:05 +00:00
Hans Wennborg f8b91f8336 s/Intrin.h/intrin.h/, trying to fix the build after r272701
llvm-svn: 272702
2016-06-14 20:14:24 +00:00
Michael Zuckerman c49f6ce3e1 [Clang][avx512][Intrinsics] adding prefetch gather intrinsics
Differential Revision: http://reviews.llvm.org/D21322

llvm-svn: 272667
2016-06-14 13:45:17 +00:00
Michael Zuckerman 223676d2cc [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps
Differential Revision: http://reviews.llvm.org/D20626

llvm-svn: 272658
2016-06-14 12:38:58 +00:00
Artem Belevich 6530a3e73f Test fix -- use captured call result instead of hardcoded %2.
llvm-svn: 272573
2016-06-13 18:44:22 +00:00
David Majnemer d423574fde [immintrin] Reimplement _bit_scan_{forward,reverse}
There is no need to use a target-specific intrinsic to implement
_bit_scan_forward or _bit_scan_reverse, reimplementing them using
generic intrinsics makes it more likely that the middle end will
understand what's going on.

llvm-svn: 272564
2016-06-13 17:26:16 +00:00
Asaf Badouh 880f0c252b [X86][AVX512F] bugfix - sqrtps should get __mask16 as mask parameter
CR: Michael Zuckerman
llvm-svn: 272549
2016-06-13 15:15:57 +00:00
Simon Pilgrim beca5f295c [Clang][X86] Convert non-temporal store builtins to generic __builtin_nontemporal_store in headers
We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp

The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores.

The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load

Differential Revision: http://reviews.llvm.org/D21272

llvm-svn: 272540
2016-06-13 09:57:52 +00:00
Craig Topper fc07498e4a [AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require avx512bw, just avx512vl.
llvm-svn: 272532
2016-06-13 04:15:11 +00:00
Simon Pilgrim 778a7eddb5 [X86][BMI] Improved bmi intrinsics checks
Ready for matching with llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll (to be added shortly)

llvm-svn: 272490
2016-06-11 22:40:01 +00:00
Craig Topper 46422562f5 [AVX512] Use a regular expression instead of checking for a specific name in a CHECK line in test.
llvm-svn: 272470
2016-06-11 13:35:43 +00:00
Craig Topper 7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select.
llvm-svn: 272467
2016-06-11 12:50:19 +00:00
Chandler Carruth c41e081f71 Fix this test to handle NDEBUG builds which don't have a name for the
basic block.

llvm-svn: 272456
2016-06-11 06:32:56 +00:00
Craig Topper 68738332b8 [AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version.
llvm-svn: 272452
2016-06-11 03:31:13 +00:00
Craig Topper d4273a425e [AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics.
llvm-svn: 272451
2016-06-11 03:31:07 +00:00
Pirama Arumuga Nainar 8b788d013c RenderScript support in the Frontend
Summary:

Create a new Frontend LangOpt to specify the renderscript language. It
is enabled by the "-x renderscript" option from the driver.

Add a "kernel" function attribute only for RenderScript (an "ignored
attribute" warning is generated otherwise).

Make the NativeHalfType and NativeHalfArgsAndReturns LangOpts be implied
by the RenderScript LangOpt.

Reviewers: rsmith

Subscribers: cfe-commits, srhines

Differential Revision: http://reviews.llvm.org/D21198

llvm-svn: 272342
2016-06-09 23:34:20 +00:00
Craig Topper 2769bb5753 [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well.
llvm-svn: 272246
2016-06-09 05:15:12 +00:00
Vitaly Buka 9d1b12c091 Specify target in lifetime-asan test.
Summary: Some target platforms -fsanitize=address.

Reviewers: pcc, eugenis

Subscribers: cfe-commits, christof, chapuni, kubabrecka

Differential Revision: http://reviews.llvm.org/D21117

llvm-svn: 272185
2016-06-08 18:18:08 +00:00
Chris Dewhurst ea61147fc7 [Sparc] Complex return value ABI compliance.
According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers:

https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html

This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules.

Differential Review: http://reviews.llvm.org/D20955

llvm-svn: 272148
2016-06-08 14:46:05 +00:00
Igor Breger aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics.
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
2016-06-08 13:59:20 +00:00
Michael Zuckerman c4ae8537cf [Clang][AVX512][BUILTIN]Adding intrinsics for range_round_{sd|ss}
Differential Revision: http://reviews.llvm.org/D21002

llvm-svn: 272123
2016-06-08 08:19:27 +00:00
Michael Zuckerman 96d0399658 [clang][AVX512][Intrinsics] Adding intrinsics reduce_[round]_{ss|sd} to clang
Differential Revision: http://reviews.llvm.org/D21014

llvm-svn: 272012
2016-06-07 14:00:20 +00:00
Craig Topper f51cc07719 [AVX512] Convert masked palignr builtins directly to native IR similar to the other palignr builtins, but with a select to handle masking.
llvm-svn: 271873
2016-06-06 06:13:01 +00:00
Michael Zuckerman 95721ac863 [Clang][AVX512]Adding set4 intrinsics
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
2016-06-05 15:43:30 +00:00
Michael Zuckerman f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
2016-06-05 15:12:52 +00:00
Craig Topper 4d302448ae [AVX512] Remove 512-bit andnot tests from the avx512vl test file.
llvm-svn: 271795
2016-06-04 16:37:38 +00:00
NAKAMURA Takumi 7f74dedb39 Suppress clang/test/CodeGen/lifetime-asan.c for targeting mingw.
clang.EXE: error: unsupported option '-fsanitize=address' for target 'x86_64-w64-windows-gnu'

llvm-svn: 271509
2016-06-02 10:54:45 +00:00
Sjoerd Meijer 90df4a7c31 This adds target support and tests for Cortex-A73
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
2016-06-02 10:48:37 +00:00
Asaf Badouh 89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
2016-06-02 08:11:35 +00:00
Michael Zuckerman 9e7d0a98fa [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_ph
Differential Revision: http://reviews.llvm.org/D20870

llvm-svn: 271498
2016-06-02 07:44:08 +00:00
Vitaly Buka 9d4eb6f389 [asan] Added -fsanitize-address-use-after-scope flag
Summary:
Also emit lifetime markers for -fsanitize-address-use-after-scope.
Asan uses life-time markers for use-after-scope check.

PR27453

Reviewers: kcc, eugenis, aizatsky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20759

llvm-svn: 271451
2016-06-02 00:24:20 +00:00
Simon Pilgrim 00880511b1 [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (clang)
The 'cvtt' truncation (round to zero) conversions can be safely represented as generic __builtin_convertvector (fptosi) calls instead of x86 intrinsics. We already do this (implicitly) for the scalar equivalents.

Note: I looked at updating _mm_cvttpd_epi32 as well but this still requires a lot more backend work to correctly lower (both for debug and optimized builds).

Differential Revision: http://reviews.llvm.org/D20859

llvm-svn: 271436
2016-06-01 21:46:51 +00:00
Michael Zuckerman 6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
2016-06-01 14:41:41 +00:00
Michael Zuckerman e54093fcc0 Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics)
Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
 Their functionality is as described in Intel intrinsics guide:
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32.

 Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc.
  Their functionality is also specified in the Intel intrinsics guide.


Commit on behalf of Omer Paparo Bivas

llvm-svn: 271387
2016-06-01 12:21:00 +00:00
Michael Zuckerman e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
2016-06-01 08:34:03 +00:00
Michael Zuckerman c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
2016-06-01 07:35:44 +00:00
Saleem Abdulrasool 4976634208 CodeGen: tweak CFString emission for COFF targets
The `isa' member was previously not given the correct DLL Storage.  Ensure that
we give the `isa' constant `__CFConstantStringClassReference' the correct DLL
storage.  Default to dllimport unless an explicit specification gives it a
dllexport storage.

llvm-svn: 271361
2016-06-01 04:22:24 +00:00
Matt Arsenault 6dc455fb93 AMDGPU: Update datalayout string
llvm-svn: 271297
2016-05-31 16:58:18 +00:00
Ranjeet Singh 61c47fd86a [ARM] Add load/store co-processor intrinsics.
Differential Revision: http://reviews.llvm.org/D20563

llvm-svn: 271275
2016-05-31 13:31:25 +00:00
Michael Zuckerman 186d86738d [Clang][Intrinsics][avx512] Adding round cvt to clang
Differential Revision: http://reviews.llvm.org/D20790

llvm-svn: 271265
2016-05-31 11:27:34 +00:00
Craig Topper 4b060e31c9 [AVX512] Convert masked load builtins to generic masked load intrinsics instead of the x86 specific ones.
This will allow the x86 intrinsics to be removed from the backend.

llvm-svn: 271253
2016-05-31 06:58:07 +00:00
Craig Topper 6e891fbdd2 [AVX512] Emit generic masked store instrinsics instead of using x86 specific intrinsics.
This will allow us to remove the x86 instrinics from the backend.

llvm-svn: 271246
2016-05-31 01:50:10 +00:00
Simon Pilgrim 0e90936fea [X86] Ensure load/store tests unaligned pointers really are align 1
llvm-svn: 271227
2016-05-30 19:20:55 +00:00
Simon Pilgrim 43439bd33d [X86][SSE] Added missing tests (merge failure)
Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271219
2016-05-30 17:58:38 +00:00
Simon Pilgrim 645e1ad33a [X86][SSE] _mm_store1_ps/_mm_store1_pd should require an aligned pointer
According to the gcc headers, intel intrinsics docs and msdn codegen the _mm_store1_pd (and its _mm_store_pd1 equivalent) should use an aligned pointer - the clang headers are the only implementation I can find that assume non-aligned stores (by storing with _mm_storeu_pd).

Additionally, according to the intel intrinsics docs and msdn codegen the _mm_store1_ps (_mm_store_ps1) requires a similarly aligned pointer.

This patch raises the alignment requirements to match the other implementations by calling _mm_store_ps/_mm_store_pd instead.

I've also added the missing _mm_store_pd1 intrinsic (which maps to _mm_store1_pd like _mm_store_ps1 does to _mm_store1_ps).

As a followup I'll update the llvm fast-isel tests to match this codegen.

Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271218
2016-05-30 17:55:25 +00:00
Craig Topper 09175dab31 [X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code that will compile to a native unaligned store. Remove the builtins since they are no longer used.
Intrinsics will be removed from llvm in a future commit.

llvm-svn: 271214
2016-05-30 17:10:30 +00:00
Saleem Abdulrasool 2460a36f53 test: add explicit targets for some tests
These tests currently expect MachO section names and do not provide a target.
Explicitly provide one.

llvm-svn: 271212
2016-05-30 16:36:48 +00:00
Saleem Abdulrasool f7444e645b CodeGen: tweak CFConstantStrings for COFF and ELF
Adjust the constant CFString emission to emit into more appropriate sections on
ELF and COFF targets.  It would previously try to use MachO section names
irrespective of the file format.

llvm-svn: 271211
2016-05-30 16:23:07 +00:00
Michael Zuckerman 9fcf3552ad [Clang][avx512][builtin] Adding missing intrinsics for cvt
Differential Revision: http://reviews.llvm.org/D20618

llvm-svn: 271205
2016-05-30 13:22:12 +00:00
Rafael Espindola ab3e10a7a0 Mark test as requiring x86-registered-target.
llvm-svn: 271163
2016-05-29 02:36:16 +00:00
Rafael Espindola f8f01c3d59 Handle -Wa,--mrelax-relocations=[no|yes].
llvm-svn: 271162
2016-05-29 02:01:14 +00:00
Saleem Abdulrasool 442b88b9ec CodeGen: support blocks on COFF targets in DLLs
This extends the blocks support to support blocks with a dynamically linked
blocks runtime.  The previous code generation would work only for static builds
of the blocks runtime.  Mark the block "isa" pointers and functions as dllimport
if no explicit declaration marked with __declspec(dllexport) is found.  This
additional check allows for the use of the functionality in the runtime library
if desired.

llvm-svn: 271138
2016-05-28 19:41:35 +00:00
Craig Topper cbdbbac875 [AVX512] Add masked v16i32 and v8i64 unaligned store tests.
llvm-svn: 271134
2016-05-28 18:59:06 +00:00
Simon Pilgrim 91b77ceaed [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (clang)
The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics.

This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics.

Note: We already did this for SSE41 PMOVSX sometime ago.

Differential Revision: http://reviews.llvm.org/D20684

llvm-svn: 271106
2016-05-28 08:12:45 +00:00
David Majnemer e6abf3d29f [CodeGen] Don't crash when sizeof(long) != 4 for some intrins
_InterlockedIncrement and _InterlockedDecrement have 'long' in their
prototypes.  We assumed 'long' was the same size as an i32 which is
incorrect for other targets.

This fixes PR27892.

llvm-svn: 270953
2016-05-27 02:06:19 +00:00
Michael Zuckerman 22c47e606a Adding missing _mm512_castsi512_si256 intrinsic.
llvm-svn: 270851
2016-05-26 14:32:11 +00:00
Simon Pilgrim 1fdfbf6941 [X86][F16C] Improved f16c intrinsics checks
Added checks for upper elements being zero'd in scalar conversions

llvm-svn: 270836
2016-05-26 10:20:25 +00:00
Simon Pilgrim 57446efaa9 [X86][AVX2] Improved checks for float/double mask generation for non-masked gathers
llvm-svn: 270833
2016-05-26 09:56:50 +00:00
Michael Zuckerman eb5f178c4b Fix instrinsics names:
_mm128_cmp_ps_mask-->_mm_cmp_ps_mask
_mm128_mask_cmp_ps_mask-->_mm_mask_cmp_ps_mask
_mm128_cmp_pd_mask-->_mm_cmp_pd_mask
_mm128_mask_cmp_pd_mask-->_mm_mask_cmp_pd_mask

llvm-svn: 270830
2016-05-26 08:10:12 +00:00
Michael Zuckerman 6f08cebf36 [Clang][AVX512][BUILTIN] Adding intrinsics for set1
Differential Revision: http://reviews.llvm.org/D20562

llvm-svn: 270825
2016-05-26 06:54:52 +00:00
Simon Pilgrim f1ad90d509 [X86][AVX2] Full set of AVX2 intrinsics tests
llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll will be synced to this

llvm-svn: 270708
2016-05-25 15:10:49 +00:00
Benjamin Kramer 1f4381f810 [AVX512] Don't rely on value names. They're different in release builds.
llvm-svn: 270704
2016-05-25 14:30:01 +00:00
Michael Zuckerman d5cc6cd262 [Clang][AVX512][BUILTIN] Add missing intrinsics for cast
Differential Revision: http://reviews.llvm.org/D20523

llvm-svn: 270699
2016-05-25 14:04:21 +00:00
Denis Zobnin eebc4af0ed [ms][dll] #26935 Defining a dllimport function should cause it to be exported
If we have some function with dllimport attribute and then we have the function
definition in the same module but without dllimport attribute we should add
dllexport attribute to this function definition.
The same should be done for variables.

Example:
struct __declspec(dllimport) C3 {
  ~C3();
};
C3::~C3() {;} // we should export this definition.

Patch by Andrew V. Tischenko

Differential revision: http://reviews.llvm.org/D18953

llvm-svn: 270686
2016-05-25 11:32:42 +00:00
Simon Pilgrim 7b365bce6f [X86][SSE] Updated _mm_store_ps1 test to match _mm_store1_ps
llvm-svn: 270679
2016-05-25 09:20:08 +00:00
Craig Topper f70a61ff3f [X86] Update test cases to make sure storeu builtins use the storeu instrinsics. We were previously matching on other stores in the IR from this being an -O0 test.
We should probably look into making the storeu builtins just emit a normal store with an alignment of 1.

llvm-svn: 270664
2016-05-25 05:26:23 +00:00
Hans Wennborg 9464491aa7 Rename test/CodeGen/inline-optim.cc to .c and provide a triple
llvm-svn: 270633
2016-05-24 23:37:56 +00:00
Hans Wennborg 7a00888a08 [Driver] Add support for -finline-functions and /Ob2 flags
-finline-functions and /Ob2 are currently ignored by Clang. The only way to
enable inlining is to use the global O flags, which also enable other options,
or to emit LLVM bitcode using Clang, then running opt by hand with the inline
pass.

This patch allows to simply use the -finline-functions flag (same as GCC) or
/Ob2 in clang-cl mode to enable inlining without other optimizations.

This is the first patch of a serie to improve support for the /Ob flags.

Patch by Rudy Pons <rudy.pons@ilod.org>!

Differential Revision: http://reviews.llvm.org/D20576

llvm-svn: 270609
2016-05-24 20:40:51 +00:00
David Majnemer a38c9f1fa5 [MS Volatile] Don't make volatile loads/stores to underaligned objects atomic
Underaligned atomic LValues require libcalls which MSVC doesn't have.
MSVC doesn't seem to consider such operations as requiring a barrier
anyway.

This fixes PR27843.

llvm-svn: 270576
2016-05-24 16:09:25 +00:00
Jacob Baungard Hansen 13a4937404 [Sparc] Add software float option -msoft-float
Summary:
Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option.

The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided.

Reviewers: jyknight, lero_chris

Subscribers: jyknight, cfe-commits

Differential Revision: http://reviews.llvm.org/D20419

llvm-svn: 270538
2016-05-24 08:30:08 +00:00
Simon Pilgrim 90770c7c76 [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
Both the (V)CVTDQ2PD(Y) (i32 to f64) and (V)CVTPS2PD(Y) (f32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the sse2/avx headers - a future patch will deal with removing the llvm intrinsics, but that will require a bit more work.

Differential Revision: http://reviews.llvm.org/D20528

llvm-svn: 270499
2016-05-23 22:13:02 +00:00
Michael Zuckerman f86eb71616 [clang][AVX512][Builtin] adding missing intrinsics for vpmultishiftqb{128|256|512} instruction set .
Differential Revision: http://reviews.llvm.org/D20521

llvm-svn: 270441
2016-05-23 15:04:39 +00:00
Michael Zuckerman e6542002fc [Clang][AVX512][BUILTIN]adding missing intrinsics for movdaq instruction set
Differential Revision: http://reviews.llvm.org/D20514

llvm-svn: 270401
2016-05-23 08:01:48 +00:00
Simon Pilgrim 28666ce778 [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
Ensure _mm256_extract_epi8 and _mm256_extract_epi16 zero extend their i8/i16 result to i32. This matches _mm_extract_epi8 and _mm_extract_epi16.

Fix for PR27594

Differential Revision: http://reviews.llvm.org/D20468

llvm-svn: 270330
2016-05-21 21:14:35 +00:00
Simon Pilgrim 8a8c4e1404 [X86][AVX] Added _mm256_testc_si256/_mm256_testnzc_si256/_mm256_testz_si256 tests
llvm-svn: 270227
2016-05-20 15:49:17 +00:00
Benjamin Kramer f4c520d5d2 Add all the avx512 flavors to __builtin_cpu_supports's list.
This is matching what trunk gcc is accepting. Also adds a missing ssse3
case. PR27779. The amount of duplication here is annoying, maybe it
should be factored into a separate .def file?

llvm-svn: 270224
2016-05-20 15:21:08 +00:00
Krzysztof Parzyszek 89fb44147b [Hexagon] Recognize "s" constraint in inline-asm
llvm-svn: 270216
2016-05-20 13:50:32 +00:00
Simon Pilgrim 4fa8250ad0 [X86][AVX] Added _mm256_extract_epi64 test
llvm-svn: 270212
2016-05-20 12:57:21 +00:00
Simon Pilgrim 94b17773e5 [X86][AVX] Full set of AVX intrinsics tests
llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll will be synced to this

llvm-svn: 270210
2016-05-20 12:41:02 +00:00
Justin Lebar 2e4ecfdebe [CUDA] Implement __ldg using intrinsics.
Summary:
Previously it was implemented as inline asm in the CUDA headers.

This change allows us to use the [addr+imm] addressing mode when
executing ld.global.nc instructions.  This translates into a 1.3x
speedup on some benchmarks that call this instruction from within an
unrolled loop.

Reviewers: tra, rsmith

Subscribers: jhen, cfe-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D19990

llvm-svn: 270150
2016-05-19 22:49:13 +00:00
Benjamin Kramer 504c01cc67 Don't rely on value numbers in test, those are fragile and change in Release (no asserts) builds.
llvm-svn: 270085
2016-05-19 17:57:35 +00:00
Artem Belevich ffa5fc51b8 [CUDA] Allow sm_50,52,53 GPUs
LLVM accepts them since r233575.

Differential Revision: http://reviews.llvm.org/D20405

llvm-svn: 270084
2016-05-19 17:47:47 +00:00
Simon Pilgrim 9b3729b043 [X86][SSE] Sync with llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
sse-builtins.c now just covers SSE1 intrinsics

llvm-svn: 270083
2016-05-19 17:11:31 +00:00
Simon Pilgrim bcf8846be5 [X86][SSE2] Fixed shuffle of results in _mm_cmpnge_sd/_mm_cmpngt_sd tests
llvm-svn: 270079
2016-05-19 16:48:59 +00:00
Ranjeet Singh b631aafee3 [ARM] Fix cdp intrinsic
- Fixed cdp intrinsic to only accept compile time
  constant values previously you could pass in a
  variable to the builtin which would result in
  illegal llvm assembly output

Differential Revision: http://reviews.llvm.org/D20394

llvm-svn: 270058
2016-05-19 13:04:34 +00:00
Michael Zuckerman 178113e8cc [Clang][AVX512][intrinsics] continue completing missing set intrinsics
Differential Revision: http://reviews.llvm.org/D20160

llvm-svn: 270047
2016-05-19 12:07:49 +00:00
Simon Pilgrim 97728dfb39 [X86][SSE2] Added _mm_move_* tests
llvm-svn: 270043
2016-05-19 11:18:49 +00:00
Simon Pilgrim cddcd2bd45 [X86][SSE2] Added _mm_cast* and _mm_set* tests
llvm-svn: 270042
2016-05-19 11:03:48 +00:00
Simon Pilgrim 3f64bb9618 [X86][SSE2] Sync with llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
llvm-svn: 270034
2016-05-19 09:52:59 +00:00
Simon Pilgrim 063c57c1f9 Revert r269967 (SSE2 builtin checks) due to failed buildbots
llvm-svn: 269970
2016-05-18 18:22:20 +00:00
Simon Pilgrim 8beed747ce [X86][SSE2] Sync with llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
llvm-svn: 269967
2016-05-18 18:12:34 +00:00
Michael Zuckerman 2cacc35343 [Clang][AVX512] completing missing intrinsics [pandnd].
Differential Revision: http://reviews.llvm.org/D20101

llvm-svn: 269939
2016-05-18 15:25:53 +00:00
Krzysztof Parzyszek e0026e4e21 [Hexagon] Recognize "q" and "v" in inline-asm as register constraints
Clang follow-up to r269933.

llvm-svn: 269934
2016-05-18 14:56:14 +00:00
Simon Pilgrim a090864762 Removed duplicate SSE42 builtin tests from avx-builtins.c
llvm-svn: 269932
2016-05-18 14:32:16 +00:00
Simon Pilgrim 519c78f3ae [X86][SSE42] Sync with llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
llvm-svn: 269931
2016-05-18 14:29:55 +00:00
Simon Pilgrim 7a4d7d47c9 [X86][SSE41] Sync with llvm/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll
llvm-svn: 269926
2016-05-18 13:47:16 +00:00
Simon Pilgrim 7e148a94a4 [X86][SSE3] Sync with llvm/test/CodeGen/X86/sse3-intrinsics-fast-isel.ll
llvm-svn: 269921
2016-05-18 13:17:39 +00:00
Ashutosh Nema 51c9dd0081 Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and 
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper

Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits

Differential Revision: http://reviews.llvm.org/D19796

llvm-svn: 269907
2016-05-18 11:56:23 +00:00
Craig Topper 39c871038a [X86] Add immediate range checks for many of the builtins.
This time allow -128 to 255 for builtins that use a char type immediate."

llvm-svn: 269878
2016-05-18 03:18:12 +00:00
Simon Pilgrim 2d1decf7cb [X86][SSE] Tidied up MMX/SSE/SSE2 builtin tests to the correct test file
llvm-svn: 269852
2016-05-17 22:03:31 +00:00
Filipe Cabecinhas 09fbfcafc3 Revert "[X86] Add immediate range checks for many of the builtins."
This reverts commit r269619.

llvm-svn: 269765
2016-05-17 14:07:43 +00:00
Craig Topper dbbe4a5542 [AVX512] Fix return types in several test cases to match the intrinsic they're testing.
llvm-svn: 269738
2016-05-17 04:41:32 +00:00
Craig Topper 8ca5373c72 [X86] Fix a few intrinsic tests to use the return type that matches the intrinsic they're testing.
llvm-svn: 269735
2016-05-17 03:42:37 +00:00
Michael Zuckerman bf05a4589e [Clang][AVX512] completing missing intrinsics for [vpabs] instruction set
Differential Revision: http://reviews.llvm.org/D20069

llvm-svn: 269680
2016-05-16 18:57:24 +00:00
Nico Weber 379a1952b3 [ms] Reintroduce feature guards in intrinsic headers in Microsoft mode
Visual Studio's C++ standard library headers include intrin.h, so the intrinsic
headers get included a lot more often in Microsoft mode than elsewhere. The
AVX512 intrinsics are a lot of code (0.7 MB, causing 30% compile time overhead
for small programs including e.g. <string> and 6% compile time overhead for
larger projects like e.g. v8). Since multiversioning can't be relied on in
Microsoft mode (cl.exe doesn't support it), having faster compiles seems like
the much better tradeoff until we have a better intrinsic story going forward
(which we'll need for e.g. PR19898).

Actually using intrinsics on Windows already requires the right /arch:
settings, so this patch should have no big behavior change.

See also thread "The intrinsics headers (especially avx512) are too big. What
to do about it?" on cfe-dev.

http://reviews.llvm.org/D20291

llvm-svn: 269675
2016-05-16 18:14:07 +00:00
Michael Zuckerman cb85677471 [Clang][AVX512] completing missing intrinsics [vsqrt|vrsqrt|vrcp14 ].
Differential Revision: http://reviews.llvm.org/D20068

llvm-svn: 269649
2016-05-16 11:42:01 +00:00
Craig Topper 9c6c85f1ad [AVX512] Add typecasts to some intrinsics to avoid doing operations on the __m512/__m512i/__m512d types.
llvm-svn: 269631
2016-05-16 06:38:36 +00:00
Craig Topper e5cc18054a [AVX512] Use correct types in test case.
llvm-svn: 269622
2016-05-16 01:09:19 +00:00
Craig Topper 0f7ea93541 [X86] Add immediate range checks for many of the builtins.
llvm-svn: 269619
2016-05-15 22:18:00 +00:00
Craig Topper dca1f230ae [AVX512] Add intrinsics for 512-bit insertf32x8/insertf32x4/inserti32x4.
llvm-svn: 269617
2016-05-15 21:26:20 +00:00
Oleg Ranevskyy 7232f66051 [CodeGen] Clang does not choose aapcs-vfp calling convention for ARM bare metal target with hard float (EABIHF)
Summary:
Clang does not detect `aapcs-vfp` for the EABIHF environment. The reason is that only GNUEABIHF is considered while choosing calling convention, EABIHF is ignored.

This causes clang to use `aapcs` for EABIHF and add the `arm_aapcscc` specifier to functions in generated IR.

The modified `arm-cc.c` test checks that no calling convention specifier is added to functions for EABIHF, which means the default one is used (`CallingConv::ARM_AAPCS_VFP`).

Reviewers: rengolin, compnerd, t.p.northover

Subscribers: aemerson, rengolin, asl, cfe-commits

Differential Revision: http://reviews.llvm.org/D20219

llvm-svn: 269419
2016-05-13 14:45:57 +00:00
Filipe Cabecinhas ab731f7e86 [ubsan] Add -fsanitize-undefined-strip-path-components=N
Summary:
This option allows the user to control how much of the file name is
emitted by UBSan. Tuning this option allows one to save space in the
resulting binary, which is helpful for restricted execution
environments.

With a positive N, UBSan skips the first N path components.
With a negative N, UBSan only keeps the last N path components.

Reviewers: rsmith

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D19666

llvm-svn: 269309
2016-05-12 16:51:36 +00:00
Michael Zuckerman 13d3c002df [clang][AVX512] completing missing set intrinsics
Differential Revision: http://reviews.llvm.org/D20099

llvm-svn: 269172
2016-05-11 11:41:29 +00:00
Michael Zuckerman 5e2c6b6200 [clang][AVX512] completing missing intrinsics for [vpermt2d|vptestm] instruction set.
Differential Revision: http://reviews.llvm.org/D20096

llvm-svn: 269170
2016-05-11 11:21:18 +00:00
NAKAMURA Takumi d4fbaef2b0 clang/test/CodeGen/avx512f-builtins.c: Fix for -Asserts.
llvm-svn: 269079
2016-05-10 17:16:12 +00:00
Michael Zuckerman e9e8e573e3 [Clang][AVX512] completing missing intrinsics [load/store]
Differential Revision: http://reviews.llvm.org/D20063

llvm-svn: 269056
2016-05-10 13:13:54 +00:00
Michael Zuckerman de860e5585 [Clang][AVX512] completing missing intrinsics [vmin/vmax]{sd|sq|uq|ud}.
Differential Revision: http://reviews.llvm.org/D20064

llvm-svn: 269042
2016-05-10 11:34:19 +00:00
Michael Zuckerman 2564d2f5fe [Clang][AVX512] completing missing intrinsics [vextractf].
Differential Revision: http://reviews.llvm.org/D20061

llvm-svn: 269037
2016-05-10 10:14:50 +00:00
Michael Zuckerman 7360d8a9cc [Clang][AVX512] completing missing intrinsics [roundscale, ceil, floor]
Differential Revision: http://reviews.llvm.org/D20070

llvm-svn: 269022
2016-05-10 07:30:58 +00:00
George Burgess IV 3dc1669133 [Sema] Fix an overload resolution bug with enable_if.
Currently, if clang::isBetterOverloadCandidate encounters an enable_if
attribute on either candidate that it's inspecting, it will ignore all
lower priority attributes (e.g. pass_object_size). This is problematic
in cases like:

```
void foo(char *c) __attribute__((enable_if(1, "")));
void foo(char *c __attribute__((pass_object_size(0))))
    __attribute__((enable_if(1, "")));
```

...Because we would ignore the pass_object_size attribute in the second
`foo`, and consider any call to `foo` to be ambiguous.

This patch makes overload resolution consult further tiebreakers (e.g.
pass_object_size) if two candidates have equally good enable_if
attributes.

llvm-svn: 269005
2016-05-10 01:59:34 +00:00
Michael Zuckerman f9be3bb1d5 [clang][AVX512] completing missing intrinsics [vmin/vmax].
Differential Revision: http://reviews.llvm.org/D20062

llvm-svn: 268910
2016-05-09 12:38:49 +00:00
Michael Zuckerman f15447537f [Clang][AVX512] completing missing intrinsics [CVT]
Differential Revision: http://reviews.llvm.org/D20056

llvm-svn: 268903
2016-05-09 10:32:51 +00:00
Krzysztof Parzyszek 09ba254f10 [Hexagon] Add a testcase for __builtin_HEXAGON_A2_tfrpi
llvm-svn: 268637
2016-05-05 15:55:54 +00:00
Marcin Koscielnicki b31ee6db11 [SystemZ] Add -mbackchain option.
This option, like the corresponding gcc option, is SystemZ-specific and
enables storing frame backchain links, as specified in the ABI.

Differential Revision: http://reviews.llvm.org/D19891

llvm-svn: 268575
2016-05-04 23:37:40 +00:00
Michael Zuckerman e6f7389b5a [Clang][Builtin][AVX512] Adding intrinsics fot cvt{u}si2s{d|s} cvt{sd|ss}2{ss|sd} instruction set
Differential Revision: http://reviews.llvm.org/D19765

llvm-svn: 268481
2016-05-04 08:55:11 +00:00
Reid Kleckner 8195f696e4 [X86] Add -malign-double support
The -malign-double flag causes i64 and f64 types to have alignment 8
instead of 4. On x86-64, the behavior of -malign-double is enabled by default.

Rebases and cleans phosek's work here: http://reviews.llvm.org/D12860

Patch by Sean Klein

Reviewers: rnk

Subscribers: rnk, jfb, dschuff, phosek

Differential Revision: http://reviews.llvm.org/D19734

llvm-svn: 268473
2016-05-04 02:58:24 +00:00
Pete Cooper 71dfcb42eb Change test to use regex instead of explicit value numbers. NFC.
We were seeing an internal failure when running this test.  I can't
see a good reason for the difference, but the simple fix is to use
%{{.*}} instead of %1.

llvm-svn: 268416
2016-05-03 18:32:01 +00:00
Michael Zuckerman c66770313a [clang][AVX512][BuiltIn] Adding intrinsics for cast{pd|ps|si}128_{pd|ps|si}512 and castsi256_si512 instruction set
Differential Revision: http://reviews.llvm.org/D19858

llvm-svn: 268387
2016-05-03 14:26:52 +00:00
Michael Zuckerman e871785eb6 [Clang][avx512][Builtin] Adding intrinsics for cvtw2mask{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19766

llvm-svn: 268385
2016-05-03 14:12:23 +00:00
Michael Zuckerman 8bfb7776e4 [Clang][AVX512][Builtin] Adding intrinsics for vcvt{ph|ps}2{ps|ph} instruction set
Differential Revision: http://reviews.llvm.org/D19767

llvm-svn: 268376
2016-05-03 12:45:04 +00:00
Michael Zuckerman 138fc5b5a8 [Clang][AVX512][Builtin] Adding intrinsics for vcvttpd2udq instruction set
Differential Revision: http://reviews.llvm.org/D19768

llvm-svn: 268373
2016-05-03 11:05:24 +00:00
Michael Zuckerman 708e759b86 [Clang][AVX512][BUILTIN] Adding intrinsics for compressstore{df|di|sf|si} instruction set.
Differential Revision: http://reviews.llvm.org/D19808

llvm-svn: 268372
2016-05-03 10:42:46 +00:00
Reid Kleckner 0404605dda Expand aggregate arguments more often on 32-bit Windows
Before this change, we would pass all non-HFA record arguments on
Windows with byval. Byval often blocks optimizations and results in bad
code generation. Windows now uses the existing workaround that other
x86_32 platforms use.

I also expanded the workaround to handle C++ records with constructors
on Windows. On non-Windows platforms, we have to keep generating the
same LLVM IR prototypes if we want our bitcode to be ABI compatible.
Otherwise we will encounter mismatch issues like PR21573.

Essentially fixes PR27522 in Clang instead of LLVM.

Reviewers: hans

Differential Revision: http://reviews.llvm.org/D19756

llvm-svn: 268261
2016-05-02 17:41:07 +00:00
Derek Schuff dbd24b4593 [WebAssembly] Rename memory_size intrinsic to current_memory
This follows the recent change in the wasm spec.

llvm-svn: 268256
2016-05-02 17:26:19 +00:00
Michael Zuckerman 5f0e96e56a [CLANG][AVX512][BUILTIN]movap{d|s}{128|256|512}
Differential Revision: http://reviews.llvm.org/D17818

llvm-svn: 268230
2016-05-02 14:02:01 +00:00
Michael Zuckerman d6e68ce75f [Clang][AVX512][BuiltIn] Adding intrinsics for cvtps2pd instruction set
Differential Revision: http://reviews.llvm.org/D19774

llvm-svn: 268217
2016-05-02 09:42:31 +00:00
Michael Zuckerman 6a0e0871db [Clang][avx512][builtin] Adding intrinsics for vexpand{d|q|ps|pd} instrctuon set
Differential Revision: http://reviews.llvm.org/D19467

llvm-svn: 268214
2016-05-02 08:36:41 +00:00
Michael Zuckerman c62f27e3f4 [Clang][BuiltIn][avx512] Adding intrinsics for vpshufd instruction set
Differential Revision: http://reviews.llvm.org/D19580

llvm-svn: 268213
2016-05-02 07:35:27 +00:00
Michael Zuckerman ac1e519944 [clang][Builtin][AVX512] Adding intrinsics for vmovshdup and vmovsldup instruction set
Differential Revision: http://reviews.llvm.org/D19595

llvm-svn: 268196
2016-05-01 14:43:43 +00:00
Michael Zuckerman 0b9d105a16 [clang][BuiltIn][AVX512]Adding intrinsics for cmp{ss|sd} instruction set.
Differential Revision: http://reviews.llvm.org/D19601

llvm-svn: 268028
2016-04-29 11:01:16 +00:00
Michael Zuckerman 41f5a37707 [Clang][AVX512][Builtin] Adding intrinsics for compress instruction set
Differential Revision: http://reviews.llvm.org/D19599

llvm-svn: 268013
2016-04-29 08:52:02 +00:00
Michael Zuckerman de8d3753d3 [clang][AVX512][Builtin] Adding intrinsics for the SAD instruction set.
Differential Revision: http://reviews.llvm.org/D19591

llvm-svn: 267942
2016-04-28 21:21:08 +00:00
Adrian Prantl 06f445d65b Debug info: Apply an artificial debug location to __cyg_profile_func.* calls.
The LLVM Verifier expects all inlinable calls in debuggable functions to
have a location.

rdar://problem/25818489

llvm-svn: 267904
2016-04-28 17:21:56 +00:00
Vassil Vassilev 928c8254a9 Reland r267691 fixing PR27535.
llvm-svn: 267882
2016-04-28 14:13:28 +00:00
Michael Zuckerman 533e065bdc [Clang][BuiltIn][AVX512] Adding intrinsics fot align{d|q} and palignr instruction set
Differential Revision: http://reviews.llvm.org/D19588

llvm-svn: 267876
2016-04-28 12:47:30 +00:00
Silviu Baranga 632fdc5919 PR27216: Only define __ARM_FEATURE_FMA when the target has VFPv4
Summary:
According to the ACLE spec, "__ARM_FEATURE_FMA is defined to 1 if
the hardware floating-point architecture supports fused floating-point
multiply-accumulate".

This changes clang's behaviour from emitting this macro for v7-A and v7-R
cores to only emitting it when the target has VFPv4 (and therefore support
for the floating point multiply-accumulate instruction).

Fixes PR27216

Reviewers: t.p.northover, rengolin

Subscribers: aemerson, rengolin, cfe-commits

Differential Revision: http://reviews.llvm.org/D18963

llvm-svn: 267869
2016-04-28 11:29:08 +00:00
Michael Zuckerman 514f05543f [Clang][Builtin][AVX512] Adding intrisnics for the vpconflict{q|d} instruction set
Differential Revision: http://reviews.llvm.org/D19525

llvm-svn: 267728
2016-04-27 15:35:13 +00:00
Michael Zuckerman 8c2900f44d [Clang][BuiltIn][AVX512] Adding intrinsics without mask for VBROADCAST and VPBROADCAST instruction set .
Differential Revision: http://reviews.llvm.org/D19196

llvm-svn: 267696
2016-04-27 11:43:14 +00:00
Michael Zuckerman 7c85a8cb46 [Clang][BuiltIn][AVX512]Adding intrinsics for vmovntdqa vmovntpd vmovntps instruction set
Differential Revision: http://reviews.llvm.org/D19529

llvm-svn: 267690
2016-04-27 10:44:15 +00:00
Jacques Pienaar e74d91314a [lanai] Update handling of structs in arguments to be passed in registers.
Previously aggregate types were passed byval, change the ABI to pass these in registers instead.

llvm-svn: 267496
2016-04-26 00:09:29 +00:00
Michael Zuckerman fa508e8b6d [Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, KORTEST, KXNOR, KXOR, KUNPACK instruction set.
Differential Revision: http://reviews.llvm.org/D19466

llvm-svn: 267425
2016-04-25 16:42:29 +00:00
Michael Zuckerman edc82fe3ef [Clang][Builtin][AVX512]Adding intrinsics for vfpclass{sd|ss} vfpclass{pd|ps} instruction set
Differential Revision: http://reviews.llvm.org/D19476

llvm-svn: 267414
2016-04-25 14:48:23 +00:00
Michael Zuckerman fcf32c2f00 [Clang][AVX512][BUILTIN] Adding intrinsics for VSCATTERPF{1|0}{DPS|QPS|DPD|QPD} instruction set
Differential Revision: http://reviews.llvm.org/D19313

llvm-svn: 267398
2016-04-25 13:01:40 +00:00
Michael Zuckerman 8938e836c4 [Clang][AVX512][BuiltIn] Adding support to intrinsics of VPERMD and VPERMW instruction set
Differential Revision: http://reviews.llvm.org/D19195

llvm-svn: 267380
2016-04-25 05:32:35 +00:00
Duncan P. N. Exon Smith 383f8413cf DebugInfo: Adapt to loss of DITypeRef in LLVM r267296
LLVM stopped using MDString-based type references, and DIBuilder no
longer fills 'retainedTypes:' with every DICompositeType that has an
'identifier:' field.   There are just minor changes to keep the same
behaviour in CFE.

Leaving 'retainedTypes:' unfilled has a dramatic impact on the output
order of the IR though.  There are a huge number of testcase changes,
which were unfortunately not really scriptable.

llvm-svn: 267297
2016-04-23 21:08:27 +00:00
Krzysztof Parzyszek 4dde0e352a [Hexagon] Add definitions for circular and bit-reverse loads/stores
llvm-svn: 267159
2016-04-22 14:58:46 +00:00
Michael Zuckerman 743d68c3cb [clang][AVX512][Builtin] adding intrinsics for vf{n}madd{ss|sd} and vf{n}sub{ss|sd} instruction set
Differential Revision: http://reviews.llvm.org/D19320

llvm-svn: 267135
2016-04-22 10:56:24 +00:00
Michael Zuckerman a1ceca20b6 [Clang][AVX512][BUILTIN] Adding scalar intrinsics for rsqrt14 ,rcp14, getexp and getmant instruction set
Differential Revision: http://reviews.llvm.org/D19326

llvm-svn: 267129
2016-04-22 10:06:10 +00:00
Renato Golin 1f04213e98 [x86] Force mixes asm syntax test to check for x86
llvm-svn: 266993
2016-04-21 14:40:06 +00:00
Michael Zuckerman 4fa96af4db [Clang][AVX512][BuiltIn] Adding intrinsics of VGATHER{DPS|DPD} , VPGATHER{QD|QQ|DD|DQ} and VGATHERPF{0|1}{DPS|QPS|DPD|QPD} instruction set .
Differential Revision: http://reviews.llvm.org/D19224

llvm-svn: 266983
2016-04-21 12:47:27 +00:00
Denis Zobnin 628b022a0e Correctly parse GCC-style asm line following MS-style asm line.
Quit parsing MS-style inline assembly if the following statement has GCC style.
Enables compilation of code like

void f() {
  __asm mov ebx, ecx
  __asm__("movl %ecx, %edx");
}

Differential Revision: http://reviews.llvm.org/D18652

llvm-svn: 266976
2016-04-21 10:59:18 +00:00
Mandeep Singh Grang d9d3b21c32 [Clang] Remove unwanted --check-prefix=CHECK from unit tests. NFC.
Summary:
    Removed unwanted --check-prefix=CHECK from the following unit tests:
      test/CXX/special/class.copy/implicit-move-def.cpp
      test/CodeGen/cleanup-destslot-simple.c
      test/CodeGen/inline-asm-immediate-ubsan.c
      test/CodeGen/mips-interrupt-attr.c
      test/CodeGenCXX/cfi-stats.cpp
      test/CodeGenCXX/copy-constructor-elim.cpp
      test/CodeGenCXX/microsoft-templ-uuidof.cpp
      test/CodeGenCXX/vtable-linkage.cpp
      test/CodeGenObjC/messages-2.m
      test/Driver/noinline.c
      test/Index/remap-load.c
      test/Index/retain-comments-from-system-headers.c
      test/OpenMP/task_if_codegen.cpp
      test/Preprocessor/comment_save_macro.c

Patch by:  Mandeep Singh Grang (mgrang)

Reviewers: rafael, ABataev, rengolin

Projects: #clang-c

Differential Revision: http://reviews.llvm.org/D19232

llvm-svn: 266843
2016-04-20 01:02:18 +00:00
Marcin Koscielnicki 4005070e1b [AArch64] Fix D19098 fallout.
The intrinsic is now called llvm.thread.pointer, not
llvm.aarch64.thread.pointer.  Also, the code handling it in CGBuiltin.cpp
is dead - it's already covered by GCCBuiltin.  Remove it.

Differential Revision: http://reviews.llvm.org/D19099

llvm-svn: 266817
2016-04-19 20:51:00 +00:00
Ahmed Bougacha 1d9de10130 [ARM NEON] Define vfms_f32 on ARM, and all vfms using vfma.
r259537 added vfma/vfms to armv7, but the builtin was only lowered
on the AArch64 side. Instead of supporting it on ARM, get rid of it.

The vfms builtin lowered to:
  %nb = fsub float -0.0, %b
  %r = @llvm.fma.f32(%a, %nb, %c)

Instead, define the operation in terms of vfma, and swap the
multiplicands. It now lowers to:
  %na = fsub float -0.0, %a
  %r = @llvm.fma.f32(%na, %b, %c)

This matches the instruction more closely, and lets current LLVM
generate the "natural" operand ordering:
  fmls.2s v0, v1, v2
instead of the crooked (but equivalent):
  fmls.2s v0, v2, v1
Except for theses changes, assembly is identical.

LLVM accepts both commutations, and the LLVM tests in:
  test/CodeGen/AArch64/arm64-fmadd.ll
  test/CodeGen/AArch64/fp-dp3.ll
  test/CodeGen/AArch64/neon-fma.ll
  test/CodeGen/ARM/fusedMAC.ll
already check either the new one only, or both.

Also verified against the test-suite unittests.

llvm-svn: 266807
2016-04-19 19:44:45 +00:00
Sanjay Patel 461f2ff445 [builtin_expect] tighten checks, add test, add comments
llvm-svn: 266788
2016-04-19 18:17:34 +00:00
Ahmed Bougacha 40a34c2e2a [CodeGen] Widen non-power-of-2 vector HFA base types.
Currently, for the ppc64--gnu and aarch64 ABIs, we recognize:
  typedef __attribute__((__ext_vector_type__(3))) float v3f32;
  typedef __attribute__((__ext_vector_type__(16))) char v16i8;
  struct HFA {
    v3f32 a;
    v16i8 b;
  };

as an HFA. Since the first type encountered is used as the base type,
we pass the HFA as:
    [2 x <3 x float>]
Which leads to incorrect IR (relying on padding values) when the
second field is used.

Instead, explicitly widen the vector (after size rounding) in
isHomogeneousAggregate.

Differential Revision: http://reviews.llvm.org/D18998

llvm-svn: 266784
2016-04-19 17:54:29 +00:00
Michael Zuckerman 6fa512cecf [Clang][Builtin][AVX512] Adding intrinsics for VGETMANT{PD|PS} and VGETEXP{PD|PS} instruction set
Differential Revision: http://reviews.llvm.org/D19197

llvm-svn: 266763
2016-04-19 17:10:29 +00:00
Michael Zuckerman ef2979af50 [Clang][AVX512][BUILTIN] Adding intrinsics support to VEXTRACT{I|F} and VINSERT{I|F} instruction set
Differential Revision: http://reviews.llvm.org/D19097

llvm-svn: 266745
2016-04-19 15:18:23 +00:00
Krzysztof Parzyszek e2bd2dcc9d [Hexagon] V60/HVX builtin definitions for clang
The builtins already exist in LLVM, but are not exposed to the C/C++
programmers. This patch adds all the information about the builtins
needed for clang, as well as a test for all available intrinsics.

llvm-svn: 266671
2016-04-18 21:27:59 +00:00
Adrian Prantl 80578e7ef0 Update testcase to new debug info metadata format.
llvm-svn: 266447
2016-04-15 16:05:13 +00:00
Adrian Prantl e76bda544b Update to match LLVM changes for PR27284.
(Reverse the ownership between DICompileUnit and DISubprogram.)

http://reviews.llvm.org/D19034
<rdar://problem/25256815>

llvm-svn: 266445
2016-04-15 15:55:45 +00:00
Reid Kleckner e1a16467a3 In vector comparisons, handle scalar LHS just as we handle scalar RHS
Summary: Fixes PR27258

Reviewers: rsmith

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D19123

llvm-svn: 266366
2016-04-14 21:03:38 +00:00
Michael Zuckerman 0a3508a8d3 [Clang][AVX512][BUILTIN] Adding support for intrinsics of vpmov{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19055

llvm-svn: 266280
2016-04-14 07:56:51 +00:00
Michael Zuckerman d871531687 [Clang][AVX512][Builtin] Adding intrinsics of vpmovus{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19050

llvm-svn: 266278
2016-04-14 06:48:09 +00:00
Michael Zuckerman e1680617b0 [Clang][AVX512][Builtin] Adding support to intrinsics of pmovs{d|q}{b|w|d}{128|256|512} instruction set
Differential Revision: http://reviews.llvm.org/D19023

llvm-svn: 266202
2016-04-13 15:02:04 +00:00
Michael Zuckerman c2b6128a8f [Clang][AVX512][Builtin] Adding support for VBROADCAST and VPBROADCASTB/W/D/Q instruction set
Differential Revision: http://reviews.llvm.org/D19012

llvm-svn: 266195
2016-04-13 12:58:01 +00:00
Michael Zuckerman 074edd7c1e [Clang][AVX512][Builtin] Adding supporting to intrinsics of cvt{b|d|q}2mask{128|256|512} and cvtmask2{b|d|q}{128|256|512} instruction set.
Differential Revision: http://reviews.llvm.org/D19009

llvm-svn: 266188
2016-04-13 10:49:37 +00:00
Chuang-Yu Cheng 8eac7ae9ad [PPC64][VSX] Add a couple of new data types for vec_vsx_ld and vec_vsx_st intrinsics and fix incorrect testcases with minor refactoring
New added data types:
  vector double vec_vsx_ld (int, const double *);
  vector float vec_vsx_ld (int, const float *);
  vector bool short vec_vsx_ld (int, const vector bool short *);
  vector bool int vec_vsx_ld (int, const vector bool int *);
  vector signed int vec_vsx_ld (int, const signed int *);
  vector unsigned int vec_vsx_ld (int, const unsigned int *);

  void vec_vsx_st (vector double, int, double *);
  void vec_vsx_st (vector float, int, float *);
  void vec_vsx_st (vector bool short, int, vector bool short *);
  void vec_vsx_st (vector bool short, int, signed short *);
  void vec_vsx_st (vector bool short, int, unsigned short *);
  void vec_vsx_st (vector bool int, int, vector bool int *);
  void vec_vsx_st (vector bool int, int, signed int *);
  void vec_vsx_st (vector bool int, int, unsigned int *);

Also fix testcases which use non-vector argument version of vec_vsx_ld or
vec_vsx_st, but pass incorrect parameter.

llvm-svn: 266166
2016-04-13 05:16:31 +00:00
Eric Christopher d5c75eed44 Add a couple of missing vsx load and store intrinsics.
Patch by Jing Yu!

llvm-svn: 266122
2016-04-12 21:08:54 +00:00
Evgeniy Stepanov b0c887762a Stricter checks in the stack-protector codegen test.
llvm-svn: 266095
2016-04-12 17:51:59 +00:00
Michael Zuckerman 04fb3bc682 [Clang][BuiltIn][avx512] Adding avx512 (shuf,sqrt{ss|sd},rsqrt ) builtin to clang
llvm-svn: 266048
2016-04-12 07:59:39 +00:00
Evgeniy Stepanov 368d3074ba Allow simultaneous safestack and stackprotector attributes.
This is the clang part of http://reviews.llvm.org/D18846.
SafeStack instrumentation pass adds stack protector canaries if both
attributes are present on a function. StackProtector pass will step
back if the function has a safestack attribute.

llvm-svn: 266005
2016-04-11 22:27:55 +00:00
Michael Zuckerman 81f468c859 [Clang][AVX512][BuiltIn] Adding avx512 ( psll{d|q}512,psllv{16si|8di},psra{d|q}512,psrav{16si|8di},pternlog{d|q}{128|256|512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18926

llvm-svn: 265964
2016-04-11 17:04:21 +00:00
Michael Zuckerman 6b5f4d8ad1 [CLANG] [AVX512] [BUILTIN] Adding PSRA{Q|D|QI|DI}{128|256|512} builtin
Differential Revision: http://reviews.llvm.org/D17693

llvm-svn: 265952
2016-04-11 15:46:39 +00:00
Michael Zuckerman 1af947a7b3 [Clang][AVX512][BuiltIn] Adding avx512 ( punpck{h|l}{dq|qdq}{128|256|512},rndscale{ss|sd}, {scalef{ss|sd|pd512|ps512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18929

llvm-svn: 265935
2016-04-11 12:32:31 +00:00
Michael Zuckerman 07525091e6 [Clang][AVX512][BuiltIn] Adding avx512 ( ptest{n}m{b|w}{128|256|512} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18924

llvm-svn: 265928
2016-04-11 10:22:07 +00:00
Dmitry Polukhin 85eda12d09 [GCC] Attribute ifunc support in clang
This patch add support for GCC attribute((ifunc("resolver"))) for
targets that use ELF as object file format. In general ifunc is a
special kind of function alias with type @gnu_indirect_function. LLVM
patch http://reviews.llvm.org/D15525

Differential Revision: http://reviews.llvm.org/D15524

llvm-svn: 265917
2016-04-11 07:48:59 +00:00
Michael Zuckerman d8d2f62107 [Clang][AVX512][BuiltIn] Adding avx512 ( vperm{i|t}2var, vpermil{var}{ps|pd}{256|512} ) builtin to clang.
Differential Revision: http://reviews.llvm.org/D18933

llvm-svn: 265915
2016-04-11 07:15:34 +00:00
Michael Zuckerman 8d16199b7b [Clang][AVX512][BuiltIn] Adding avx512 ( vcvt ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18932

llvm-svn: 265904
2016-04-10 17:24:03 +00:00
Michael Zuckerman cdd54c83d8 Adding avx512 (unpck{h|l}{pd|ps}, rcp14{pd|ps}{128|256},vplzcnt{d|q} ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18931

llvm-svn: 265896
2016-04-10 12:54:23 +00:00
Michael Zuckerman fa7ccc5bcf [Clang][AVX512][BuiltIn] Adding avx512 ( store ) builtin to clang
Differential Revision: http://reviews.llvm.org/D18925

llvm-svn: 265895
2016-04-10 10:51:04 +00:00
Sanjay Patel ae7a9df7bf make __builtin_isfinite more efficient (PR27145)
isinf (is infinite) and isfinite should be implemented with the same function
except we change the comparison operator.

See PR27145 for more details:
https://llvm.org/bugs/show_bug.cgi?id=27145

Ref: forked off of the discussion in D18513.

Differential Revision: http://reviews.llvm.org/D18648

llvm-svn: 265675
2016-04-07 14:29:05 +00:00
Tim Northover 1390b4479e Restore slightly less dodgy diagnostic handler for inline asm
Turns out it was there mostly to prevent Clang asking people to report a bug.
This time we report something to Clang's real diagnostics handler so that it
exits with something approximating a real error and tidies up after itself.

llvm-svn: 265592
2016-04-06 19:58:07 +00:00
Manman Ren 29be7e10ca Update testing cases after backend changes.
llvm-svn: 265488
2016-04-05 23:27:51 +00:00