Commit Graph

4432 Commits

Author SHA1 Message Date
Clement Courbet 41c8af3924 [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.
Summary:
The pfm counters are now in the ExegesisTarget rather than the
MCSchedModel (PR39165).

This also compresses the pfm counter tables (PR37068).

Reviewers: RKSimon, gchatelet

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D52932

llvm-svn: 345243
2018-10-25 07:44:01 +00:00
Daniel Sanders d0ef689830 Fix MSVC build by correcting placement of declspec after r345056
Going by the MSVC toolchains at godbolt.org, declspec comes after the template<...>.

llvm-svn: 345059
2018-10-23 17:41:39 +00:00
Daniel Sanders d300ba1ed7 [tblgen] Allow FixedLenDecoderEmitter to use APInt-like objects as InsnType
Summary:
Some targets have very long encodings and uint64_t isn't sufficient. uint128_t
isn't portable so such targets need to use an object instead.

There is one catch with this at the moment, no string of bits extracted
from the encoding may exceeed 64-bits. Fields are still permitted to
exceed 64-bits so long as they aren't one contiguous string of bits. If
this proves to be a problem then we can modify the generation of
fieldFromInstruction() calls to account for it but for now I've added an
assertion for this.

InsnType must either be integral or an APInt-like object that must:
* Have a static const max_size_in_bits equal to the number of bits in the encoding.
* be default-constructible and copy-constructible
* be constructible from a uint64_t (this is the key area the interface deviates
  from APInt since this constructor does not take the bit width)
* be constructible from an APInt (this can be private)
* be convertible to uint64_t
* Support the ~, &,, ==, !=, and |= operators with other objects of the same type
* Support shift (<<, >>) with signed and unsigned integers on the RHS
* Support put (<<) to raw_ostream&

Reviewers: bogner, charukcs

Subscribers: nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D52100

llvm-svn: 345056
2018-10-23 17:23:31 +00:00
Thomas Lively c63b5fcb2a [WebAssembly][NFC] Remove WebAssemblyStackifier TableGen backend
Summary:
Replace its functionality with a TableGen InstrInfo relational
instruction mapping. Although arguably more complex than the TableGen
backend, the relational mapping is a smaller maintenance burden than a
TableGen backend.

Reviewers: aardappel, aheejin, dschuff

Subscribers: mgorny, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53307

llvm-svn: 344962
2018-10-22 21:55:26 +00:00
Fangrui Song 2e83b2e9ee Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC
llvm-svn: 344774
2018-10-19 06:12:02 +00:00
Andrea Di Biagio 6eebbe0a97 [tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen.
This patch adds the ability to identify instructions that are "move elimination
candidates". It also allows scheduling models to describe processor register
files that allow move elimination.

A move elimination candidate is an instruction that can be eliminated at
register renaming stage.
Each subtarget can specify which instructions are move elimination candidates
with the help of tablegen class "IsOptimizableRegisterMove" (see
llvm/Target/TargetInstrPredicate.td).

For example, on X86, BtVer2 allows both GPR and MMX/SSE moves to be eliminated.
The definition of 'IsOptimizableRegisterMove' for BtVer2 looks like this:

```
def : IsOptimizableRegisterMove<[
  InstructionEquivalenceClass<[
    // GPR variants.
    MOV32rr, MOV64rr,

    // MMX variants.
    MMX_MOVQ64rr,

    // SSE variants.
    MOVAPSrr, MOVUPSrr,
    MOVAPDrr, MOVUPDrr,
    MOVDQArr, MOVDQUrr,

    // AVX variants.
    VMOVAPSrr, VMOVUPSrr,
    VMOVAPDrr, VMOVUPDrr,
    VMOVDQArr, VMOVDQUrr
  ], CheckNot<CheckSameRegOperand<0, 1>> >
]>;
```

Definitions of IsOptimizableRegisterMove from processor models of a same
Target are processed by the SubtargetEmitter to auto-generate a target-specific
override for each of the following predicate methods:

```
bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI)
const;
bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned
CPUID) const;
```

By default, those methods return false (i.e. conservatively assume that there
are no move elimination candidates).

Tablegen class RegisterFile has been extended with the following information:
 - The set of register classes that allow move elimination.
 - Maxium number of moves that can be eliminated every cycle.
 - Whether move elimination is restricted to moves from registers that are
   known to be zero.

This patch is structured in three part:

A first part (which is mostly boilerplate) adds the new
'isOptimizableRegisterMove' target hooks, and extends existing register file
descriptors in MC by introducing new fields to describe properties related to
move elimination.

A second part, uses the new tablegen constructs to describe move elimination in
the BtVer2 scheduling model.

A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove'
hook to mark instructions that are candidates for move elimination. It also
teaches class RegisterFile how to describe constraints on move elimination at
PRF granularity.

llvm-mca tests for btver2 show differences before/after this patch.

Differential Revision: https://reviews.llvm.org/D53134

llvm-svn: 344334
2018-10-12 11:23:04 +00:00
Andrea Di Biagio f455e3569f [tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero physical registers.
llvm-svn: 344235
2018-10-11 10:39:03 +00:00
Nicolai Haehnle 46c91fd233 TableGen/CodeGenDAGPatterns: addPredicateFn only once
Summary:
The predicate function is added in InlinePatternFragments, no need to
do it here. As a result, all uses of addPredicateFn are located in
InlinePatternFragments.

Test confirmed that there are no changes to generated files when
building all (non-experimental) targets.

Change-Id: I720e42e045ca596eb0aa339fb61adf6fe71034d5

Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D51993

llvm-svn: 343977
2018-10-08 16:53:31 +00:00
Fangrui Song 3507c6e884 Use the container form llvm::sort(C, ...)
There are a few leftovers in rL343163 which span two lines. This commit
changes these llvm::sort(C.begin(), C.end, ...) to llvm::sort(C, ...)

llvm-svn: 343426
2018-09-30 22:31:29 +00:00
Fangrui Song 0cac726a00 llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
Summary: The convenience wrapper in STLExtras is available since rL342102.

Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb

Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D52573

llvm-svn: 343163
2018-09-27 02:13:45 +00:00
Clement Courbet 596c56ff9c [llvm-exegesis] Add support for measuring NumMicroOps.
Summary:
Example output for vzeroall:

---
mode:            uops
key:
  instructions:
    - 'VZEROALL'
  config:          ''
  register_initial_values:
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:
  - { debug_string: HWPort0, value: 0.0006, per_snippet_value: 0.0006,
      key: '3' }
  - { debug_string: HWPort1, value: 0.0011, per_snippet_value: 0.0011,
      key: '4' }
  - { debug_string: HWPort2, value: 0.0004, per_snippet_value: 0.0004,
      key: '5' }
  - { debug_string: HWPort3, value: 0.0018, per_snippet_value: 0.0018,
      key: '6' }
  - { debug_string: HWPort4, value: 0.0002, per_snippet_value: 0.0002,
      key: '7' }
  - { debug_string: HWPort5, value: 1.0019, per_snippet_value: 1.0019,
      key: '8' }
  - { debug_string: HWPort6, value: 1.0033, per_snippet_value: 1.0033,
      key: '9' }
  - { debug_string: HWPort7, value: 0.0001, per_snippet_value: 0.0001,
      key: '10' }
  - { debug_string: NumMicroOps, value: 20.0069, per_snippet_value: 20.0069,
      key: NumMicroOps }
error:           ''
info:            ''
assembled_snippet: C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C5FC77C3
...

Reviewers: gchatelet

Subscribers: tschuett, RKSimon, andreadb, llvm-commits

Differential Revision: https://reviews.llvm.org/D52539

llvm-svn: 343094
2018-09-26 11:22:56 +00:00
Daniel Sanders 06f4ff1952 [globalisel][tblgen] Table optimization should consider the C++ code in C++ predicates
This fixes PR39045

llvm-svn: 342997
2018-09-25 17:59:02 +00:00
Wouter van Oortmerssen e0403f13c4 [WebAssembly] Simplified selecting asmmatcher stack instructions.
Summary:
By using the existing isCodeGenOnly bit in the tablegen defs, as
suggested by tlively in https://reviews.llvm.org/D51662

Tested: llvm-lit -v `find test -name WebAssembly`

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52373

llvm-svn: 342772
2018-09-21 20:53:55 +00:00
Wouter van Oortmerssen 7beaa30e4e [WebAssembly] Made assembler only use stack instruction tablegen defs
Summary:
This ensures we have the non-register version of the instruction.

The stack version of call_indirect now wants a type index argument,
so that has been added in the existing tests.

Tested:
llvm-lit -v `find test -name WebAssembly`

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51662

llvm-svn: 342753
2018-09-21 17:47:58 +00:00
Andrea Di Biagio c33b2e6d0f Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555.
The reason why build #25777 might have failed is because the SmallVector move
constructor is _not_ noexcept, and the stl implementation used by that buildbot
calls _VSTD::move_if_noexcept() (according to the backtrace).

OpcodeInfo has a default move constructor, and the copy constructor is deleted.
However, as far as I can see, SmallVector doesn't declare a noexcept move
constructor. So, what I believe it is happening here is that,
_VSTD::move_if_noexcept() returns an lvalue reference and not an rvalue
reference.
This eventually triggers a copy that fails to compile.

Hopefully, using a std::vector instead of SmallVector (as it was originally
suggested by Simon in the code review) should be enough to unbreak the buildbot.

llvm-svn: 342561
2018-09-19 17:54:01 +00:00
Andrea Di Biagio 8b6c314be1 [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
This patch adds the ability for processor models to describe dependency breaking
instructions.

Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.

The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).

```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
  return false;
}

virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
  return isZeroIdiom(MI);
}
```

An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.

A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.

STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.

This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.

This patch supersedes the one committed at r338372 (phabricator review: D49310).

The main advantages are:
 - We can describe subtarget predicates via tablegen using STIPredicates.
 - We can describe zero-idioms / dep-breaking instructions directly via
   tablegen in the scheduling models.

In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
 - Teach how to identify optimizable register-register moves
 - Teach how to identify slow LEA instructions (each subtarget defining its own
   concept of "slow" LEA).
 - Teach how to identify instructions that have undocumented false dependencies
   on the output registers on some processors only.

It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.

This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.

Differential Revision: https://reviews.llvm.org/D52174

llvm-svn: 342555
2018-09-19 15:57:45 +00:00
Simon Pilgrim 6d70677937 [TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::set() where possible. NFCI.
In these cases we are always setting to true.

llvm-svn: 342543
2018-09-19 12:23:50 +00:00
Simon Pilgrim 429df29eea [TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVector::push_back()
As mentioned on D52236, this saves 10secs in debug builds of x86 -gen-dag-isel

llvm-svn: 342536
2018-09-19 11:18:49 +00:00
Jinsong Ji 0594162f32 [NFC] Update comments regarding BufferSize for ProcResources
llvm-svn: 342491
2018-09-18 15:38:56 +00:00
Simon Pilgrim b244435dc2 Use pass-by-reference for-range loop. NFCI.
llvm-svn: 342481
2018-09-18 14:05:07 +00:00
Simon Pilgrim e3c6f8ddcf Fix signed/unsigned comparison warning. NFCI.
llvm-svn: 342469
2018-09-18 12:01:25 +00:00
Simon Pilgrim 0621f56c84 [TableGen] CodeGenDAGPatterns::GenerateVariants - full caching of matching predicates
Further extension to D51035, this patch avoids all repeated predicates[] matching by caching as it collects the patterns that have multiple variants.

Saves around 25secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D51839

llvm-svn: 342467
2018-09-18 11:30:30 +00:00
Josh Stone aca532f14d Test commit: remove trailing whitespace
llvm-svn: 341966
2018-09-11 17:28:43 +00:00
Wouter van Oortmerssen a733d08db2 [WebAssembly] Made disassembler only use stack instructions.
Summary:
Now uses the StackBased bit from the tablegen defs to identify
stack instructions (and ignore register based or non-wasm instructions).

Also changed how we store operands, since we now have up to 16 of them
per instruction. To not cause static data bloat, these are compressed
into a tiny table.

+ a few other cleanups.

Tested:
- MCTest
- llvm-lit -v `find test -name WebAssembly`

Reviewers: dschuff, jgravelle-google, sunfish, tlively

Subscribers: sbc100, aheejin, llvm-commits

Differential Revision: https://reviews.llvm.org/D51320

llvm-svn: 341081
2018-08-30 15:40:53 +00:00
Simon Pilgrim 39715e3a66 Remove debug code accidently committed in rL340837. NFCI.
llvm-svn: 340908
2018-08-29 10:10:58 +00:00
Thomas Lively adb6da10b8 [WebAssembly][NFC] Document stackifier tablegen backend
Summary:
Add comments to help readers avoid having to read tablegen backends to
understand the code. Also remove unecessary breaks from the output.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51371

llvm-svn: 340864
2018-08-28 18:49:47 +00:00
Thomas Lively 94a91dbac5 [WebAssembly][NFC] Fix formatting from rL340781
Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51367

llvm-svn: 340861
2018-08-28 18:34:33 +00:00
Simon Pilgrim 6a92b5e1e2 [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching predicates
CodeGenDAGPatterns::GenerateVariants is a costly function in many tblgen commands (33.87% of the total runtime of x86 -gen-dag-isel), and due to the O(N^2) nature of the function, there are a high number of repeated comparisons of the pattern's vector<Predicate>.

This initial patch at least avoids repeating these comparisons for every Variant in a pattern. I began investigating caching all the matches before entering the loop but hit issues with how best to store the data and how to update the cache as patterns were added.

Saves around 15secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D51035

llvm-svn: 340837
2018-08-28 15:42:08 +00:00
Simon Pilgrim b7e10182ce [TableGen] Use std::move where possible in InstructionMemo constructor. NFCI.
Requested in post-commit review for rL339670

llvm-svn: 340819
2018-08-28 11:10:27 +00:00
Thomas Lively 211874d2f3 [WebAssembly] TableGen backend for stackifying instructions
Summary:
The new stackification backend generates the giant switch statement
used to translate instructions to their stackified forms. I did this
because it was more interesting than adding all the different vector
versions of the various SIMD instructions to the switch statment
manually.

Reviewers: aardappel, aheejin, dschuff

Subscribers: mgorny, sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D51318

llvm-svn: 340781
2018-08-27 22:02:09 +00:00
Nicolai Haehnle ba9eee5fad TableGen/SearchableTables: Cast enums to unsigned in generated code
Summary:
This should fix signedness warnings when compiling with MSVC.

Change-Id: I4664cce0ba91e9b42d21a86fd4a7e82f2320c451

Reviewers: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51097

llvm-svn: 340518
2018-08-23 08:02:02 +00:00
Heejin Ahn ed5e06b0a7 [WebAssembly] Add isEHScopeReturn instruction property
Summary:
So far, `isReturn` property is used to mean both a return instruction
from a functon and the end of an EH scope, a scope that starts with a EH
scope entry BB and ends with a catchret or a cleanupret instruction.
Because WinEH uses funclets, all EH-scope-ending instructions are also
real return instruction from a function. But for wasm, they only serve
as the end marker of an EH scope but not a return instruction that
exits a function. This mismatch caused incorrect prolog and epilog
generation in wasm EH scopes. This patch fixes this.

This patch is in the same vein with rL333045, which splits
`MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and
`isEHScopeEntry`.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50653

llvm-svn: 340325
2018-08-21 19:44:11 +00:00
Simon Pilgrim 2784a339ab [TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI.
llvm-svn: 340055
2018-08-17 17:45:15 +00:00
Simon Pilgrim 45e61c5f99 [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode
We were just caching the MVT set of legal types, then every call creating a new TypeSetByHwMode with it and passing it back on the stack. There's no need to do this - we can create and cache the whole TypeSetByHwMode once and return a const reference to it each time.

Additionally, TypeInfer::expandOverloads wasn't making use of the fact that the cache just contains a default mode containing all the types.

Saves up to 30secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50903

llvm-svn: 340042
2018-08-17 15:54:07 +00:00
Simon Pilgrim 16a2f54eee [TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI.
Avoids repeated count()/find() calls that we've already have the default values for.

llvm-svn: 340020
2018-08-17 13:03:17 +00:00
Simon Pilgrim 0e18133905 [TableGen] TypeSetByHwMode::operator== optimization
This operator is called a great deal, by checking for the cheap isSimple equality cases first (a common occurrence) we can improve performance as we avoid a lot of std::map find/iteration in hasDefault.

isSimple also means that a default value is present, so we can avoid some hasDefault calls.

This also avoids a rather dodgy piece of logic that was checking for isSimple() && !VTS.isSimple() but not the inverse - it now uses the general hasDefault mode comparison test instead.

Saves around 15secs in debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50841

llvm-svn: 339890
2018-08-16 16:16:28 +00:00
Simon Pilgrim f19cdc6127 [TableGen] Avoid self getPredicates() != comparison. NFCI.
We were performing a completely unnecessary full comparison of the same std::vector<Predicate>.

llvm-svn: 339888
2018-08-16 16:04:05 +00:00
Simon Pilgrim a9d64122c5 [TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum
Avoids costly std::map copies inside ValueTypeByHwMode constructor

llvm-svn: 339884
2018-08-16 15:29:24 +00:00
Simon Pilgrim c3c1441bda [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize
I noticed this during profiling of tablegen (PR28222) that we were calling Child->getType(0) which creates a ValueTypeByHwMode on the fly from the requested internal TypeSetByHwMode type and returns it by value, we then treat it as a TypeSetByHwMode reference which involves constructing a new TypeSetByHwMode on the stack with a large amount of std::map iterating/copying all along the way.

I am not an expert on tablegen, but AFAICT this is all unnecessary and we should be calling Child->getExtType(0) which returns the original TypeSetByHwMode by reference.

This gives me a 90sec reduction in msvc debug builds of x86 -gen-dag-isel.

Differential Revision: https://reviews.llvm.org/D50789

llvm-svn: 339812
2018-08-15 20:41:19 +00:00
Andrea Di Biagio 9eaf5aa006 [Tablegen][MCInstPredicate] Removed redundant template argument from class TIIPredicate, and implemented verification rules for TIIPredicates.
This patch removes redundant template argument `TargetName` from TIIPredicate.
Tablegen can always infer the target name from the context. So we don't need to
force users of TIIPredicate to always specify it.

This allows us to better modularize the tablegen class hierarchy for the
so-called "function predicates". class FunctionPredicateBase has been added; it
is currently used as a building block for TIIPredicates. However, I plan to
reuse that class to model other function predicate classes too (i.e. not just
TIIPredicates). For example, this can be a first step towards implementing
proper support for dependency breaking instructions in tablegen.

This patch also adds a verification step on TIIPredicates in tablegen.
We cannot have multiple TIIPredicates with the same name. Otherwise, this will
cause build errors later on, when tablegen'd .inc files are included by cpp
files and then compiled.

Differential Revision: https://reviews.llvm.org/D50708

llvm-svn: 339706
2018-08-14 18:36:54 +00:00
Simon Pilgrim 77af5fdb18 [TableGen] Pass string/vector types by const reference (PR37666). NFCI
llvm-svn: 339670
2018-08-14 11:17:38 +00:00
Craig Topper cade635c77 [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions.
The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same.

While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day.

The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with.

While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them.

Fixes PR38537.

llvm-svn: 339622
2018-08-13 22:06:28 +00:00
Andrea Di Biagio 2c6cbc8bb2 [Tablegen] Replace uses of formatted_raw_ostream with raw_ostream in the predicate expander. NFCI
This is a follow-up of r339552.

As pointed out by Craig in D50566, we don't need a formatted_raw_ostream to
indent strings. We can use instead raw_ostream::indent().

Internally, class PredicateExpander already keeps track of the current
indentation level. Also, the grammar for predicates is well parenthesized, and
therefore we don't need to use a formatted_raw_ostream to continuously track the
column number. Instead we can safely replace all the uses of
formatted_raw_ostream::PadToColumn() with uses of raw_ostream::indent().

By replacing formatted_raw_ostream with a simpler raw_ostream, we also avoid the
implicit check on the newline character on every print to stream.

No functional change intended.

llvm-svn: 339577
2018-08-13 15:13:35 +00:00
Andrea Di Biagio 24d86d8513 [Tablegen][SubtargetEmitter] Improve expansion of predicates of a variant scheduling class.
This patch refactors the logic that expands predicates of a variant scheduling
class.

The idea is to improve the readability of the auto-generated code by removing
redundant parentheses around predicate expressions, and by removing redundant
if(true) statements.

This patch replaces the definition of NoSchedPred in TargetSchedule.td with an
instance of MCSchedPredicate. The new definition is sematically equivalent to
the previous one. The main difference is that now SubtargetEmitter knows that it
represents predicate "true".

Before this patch, we always generated an if (true) for the default transition
of a variant scheduling class.

Example (taken from AArch64GenSubtargetInfo.inc) :

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if ((TII->isScaledAddr(*MI)))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  if ((true))
    return 928; // WriteLD_ReadDefault
}
```

Extra parentheses were also generated around the predicate expressions.

With this patch, we get the following auto-generated checks:

```
if (SchedModel->getProcessorID() == 3) { // CycloneModel
  if (TII->isScaledAddr(*MI))
    return 927; // (WriteIS_WriteLD)_ReadBaseRS
  return 928; // WriteLD_ReadDefault
}
```

The new auto-generated code behaves exactly the same as before. So, technically
this is a non functional change.

Differential revision: https://reviews.llvm.org/D50566

llvm-svn: 339552
2018-08-13 11:09:04 +00:00
Daniel Sanders f1e8e3b316 [globalisel] Remove dead code from GlobalISelEmitter
Summary: Found by GCC's -Wunused-function.

Patch by Kim Gräsman

Reviewers: ab, dsanders, llvm-commits

Reviewed By: dsanders

Subscribers: rovka, kristof.beyls

Differential Revision: https://reviews.llvm.org/D50611

llvm-svn: 339528
2018-08-12 21:49:42 +00:00
Andrea Di Biagio 8bdfd52ba7 [Tablegen][SubtargetEmitter] refactor method `emitSchedModelHelpersImpl()`. NFCI
Part of the logic has been moved to helper functions to (hopefully) improve
readability.
Added a few code comments to better describe how the algorithm works.

No functional change intended.

llvm-svn: 339421
2018-08-10 10:43:43 +00:00
Andrea Di Biagio f3bde0485c [MC][PredicateExpander] Extend the grammar to support simple switch and return statements.
This patch introduces tablegen class MCStatement.

Currently, an MCStatement can be either a return statement, or a switch
statement.

```
MCStatement:
   MCReturnStatement
   MCOpcodeSwitchStatement
```

A MCReturnStatement expands to a return statement, and the boolean expression
associated with the return statement is described by a MCInstPredicate.

An MCOpcodeSwitchStatement is a switch statement where the condition is a check
on the machine opcode. It allows the definition of multiple checks, as well as a
default case. More details on the grammar implemented by these two new
constructs can be found in the diff for TargetInstrPredicates.td.

This patch makes it easier to read the body of auto-generated TargetInstrInfo
predicates.

In future, I plan to reuse/extend the MCStatement grammar to describe more
complex target hooks. For now, this is just a first step (mostly a minor
cosmetic change to polish the new predicates framework).

Differential Revision: https://reviews.llvm.org/D50457

llvm-svn: 339352
2018-08-09 15:32:48 +00:00
Bjorn Pettersson c8b782cec2 [MC] Remove PhysRegSize from MCRegisterClass
Summary:
The interface to get size and spill size of a register
was moved from MCRegisterInfo to TargetRegisterInfo over
a year ago. Afaik the old interface has bee around
to give out-of-tree targets a chance to adapt to the
new interface.

One problem with the old MCRegisterClass::PhysRegSize was that
it represented the size of a register as "size in bits" / 8.
So a register had to be a multiple of eight bits wide for the
size to be correct (and the byte size for the target needed to
be eight bits).

Reviewers: kparzysz, qcolombet

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47199

llvm-svn: 339350
2018-08-09 15:19:07 +00:00
Daniel Sanders 944fbb1475 [tablegen] Improve performance of -gen-register-info by replacing barely-necessary std::map with a sorted vector
Summary:
This particular map is hardly ever queried and has a phased usage pattern (insert,
iterate, query, insert, iterate) so it's a good candidate for a sorted vector and
std::lower_bound.

This significantly reduces the run time of runTargetDesc() in some circumstances.
One llvm-tblgen invocation in my build improves the time spent in runTargetDesc()
from 9.86s down to 0.80s (~92%) without changing the output. The same invocation
also has 2GB less allocation churn.

Reviewers: bogner, rtereshin, aditya_nandakumar, volkan

Reviewed By: rtereshin

Subscribers: mgrang, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D50272

llvm-svn: 339208
2018-08-08 00:19:59 +00:00
Ulrich Weigand f989cd78e4 Fix build bot after r338521
llvm-svn: 338522
2018-08-01 12:07:32 +00:00