38b7eee164
More DCE.
...
llvm-svn: 77231
2009-07-27 18:48:45 +00:00
0e075e2429
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
...
llvm-svn: 77230
2009-07-27 18:44:00 +00:00
18688f431d
Get rid of more dead code.
...
llvm-svn: 77227
2009-07-27 18:38:54 +00:00
239ed4b343
Cosmetic change.
...
llvm-svn: 77222
2009-07-27 18:31:40 +00:00
8f2ed1bc5a
Clean up.
...
llvm-svn: 77221
2009-07-27 18:25:24 +00:00
056c669e93
Get rid of some more getOpcode calls.
...
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
007031d1b4
Thumb-2 does not have RSC.
...
llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
...
llvm-svn: 77199
2009-07-27 16:31:55 +00:00
86b7255776
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
...
instead.
llvm-svn: 77186
2009-07-27 06:17:14 +00:00
149465ea06
Eliminate SectionFlags, just embed a SectionKind into Section
...
instead and drive things based off of that.
llvm-svn: 77184
2009-07-27 05:32:16 +00:00
371ec9e810
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
...
llvm-svn: 77182
2009-07-27 04:18:04 +00:00
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
...
llvm-svn: 77181
2009-07-27 03:14:20 +00:00
186332f898
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
...
llvm-svn: 77175
2009-07-27 00:33:08 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
...
llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
...
llvm-svn: 77173
2009-07-27 00:05:15 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
...
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
602d44fa70
untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a
...
'unnamed' bss section, but some impls would want a named one. Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.
llvm-svn: 77165
2009-07-26 19:23:28 +00:00
8953720f23
Refactor. Get rid of a few more getOpcode() calls.
...
llvm-svn: 77164
2009-07-26 18:55:14 +00:00
9813b0b025
Eliminate some uses of DOUT, cerr, and getNameStart().
...
llvm-svn: 77145
2009-07-26 07:49:05 +00:00
ee01b242e8
Factor commonality in triple match routines into helper template for registering
...
classes, and migrate existing targets over.
llvm-svn: 77126
2009-07-26 05:03:33 +00:00
bc981d8efa
Kill Target specific ModuleMatchQuality stuff.
...
- This was overkill and inconsistently implemented.
llvm-svn: 77114
2009-07-26 02:22:58 +00:00
8a37bbebfd
Add support for ARM Neon VREV instructions.
...
Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
e03eecb75f
Remove Value::{isName, getNameRef}.
...
Also, change MDString to use a StringRef.
llvm-svn: 77098
2009-07-25 23:55:21 +00:00
691a4784db
Simplify JIT target selection.
...
- Instead of requiring targets to define a JIT quality match function, we just
have them specify if they support a JIT.
- Target selection for the JIT just gets the host triple and looks for the best
target which matches the triple and has a JIT.
llvm-svn: 77060
2009-07-25 10:09:50 +00:00
5680b4f285
Add new helpers for registering targets.
...
- Less boilerplate == good.
llvm-svn: 77052
2009-07-25 06:49:55 +00:00
ea23c3ba46
80 col violation.
...
llvm-svn: 77041
2009-07-25 01:55:25 +00:00
c1a5cfa9a0
Get rid of a couple of unnecessary getOpcode calls.
...
llvm-svn: 77035
2009-07-25 01:25:08 +00:00
b2c22f00de
Another TODO.
...
llvm-svn: 77026
2009-07-25 00:39:37 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
...
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
0dd5e1ed39
More migration to raw_ostream, the water has dried up around the iostream hole.
...
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
llvm-svn: 77019
2009-07-25 00:23:56 +00:00
f297256136
ARM code emitter can't handle Thumb2 instructions yet. So don't even try.
...
llvm-svn: 77018
2009-07-25 00:13:11 +00:00
edb4a70325
Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.
...
llvm-svn: 77011
2009-07-24 23:12:02 +00:00
c64ce30c67
Uh. It would be useful to actually print the operand.
...
llvm-svn: 77004
2009-07-24 20:47:38 +00:00
c26c76ec1d
Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
...
llvm-svn: 76995
2009-07-24 19:31:03 +00:00
5a49c54061
Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden.
...
llvm-svn: 76991
2009-07-24 18:54:23 +00:00
666c912ce3
Make sure thumb2 jumptable entries are aligned.
...
llvm-svn: 76986
2009-07-24 18:20:44 +00:00
886f303480
Clean up.
...
llvm-svn: 76984
2009-07-24 18:20:16 +00:00
986fc8e74b
Replace use of std::set with SmallPtrSet.
...
llvm-svn: 76983
2009-07-24 18:19:46 +00:00
95fc6ee51a
Remove unused member functions.
...
llvm-svn: 76960
2009-07-24 07:43:59 +00:00
1553fdee55
use section flags more correctly.
...
llvm-svn: 76944
2009-07-24 04:08:17 +00:00
07bd1cd8c5
reduce api exposure: clients shouldn't call SectionKindForGlobal directly.
...
llvm-svn: 76941
2009-07-24 03:49:17 +00:00
c3259f3ffb
Thumb2 should use the register scavenger.
...
llvm-svn: 76930
2009-07-24 01:05:51 +00:00
6cfbe61361
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
...
llvm-svn: 76925
2009-07-24 00:53:56 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
...
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
...
llvm-svn: 76909
2009-07-23 23:09:51 +00:00
d2919a1773
Fix up ARM constant island pass for Thumb2.
...
Also fixed up code to fully use the SoImm field for ADR on ARM mode.
llvm-svn: 76890
2009-07-23 18:27:47 +00:00
95a73e2eab
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
...
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
...
llvm-svn: 76883
2009-07-23 17:06:46 +00:00
edda8cbfad
80 col violation.
...
llvm-svn: 76872
2009-07-23 07:58:08 +00:00
a0b2dc93b5
Fix typo in addrmode definition.
...
llvm-svn: 76806
2009-07-22 22:24:31 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
1ec4396ee3
Eliminate a redudant check Eli pointed out.
...
llvm-svn: 76762
2009-07-22 18:08:05 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
...
llvm-svn: 76729
2009-07-22 06:46:53 +00:00
6253a19651
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
...
llvm-svn: 76728
2009-07-22 06:37:28 +00:00
eadb6681cf
Fix a obvious copy-n-paste bug.
...
llvm-svn: 76727
2009-07-22 06:12:40 +00:00
2e1d66847c
Get rid one of the getRegisterNumbering. Also add D16 - D31.
...
llvm-svn: 76725
2009-07-22 05:55:18 +00:00
c7a243dfdd
Add an entry.
...
llvm-svn: 76711
2009-07-22 00:58:27 +00:00
47db941fd3
Get rid of the Pass+Context magic.
...
llvm-svn: 76702
2009-07-22 00:24:57 +00:00
87aaa194f9
Fixing cp island pass. Step 1: Determine whether the constant pool offset can be
...
negative on an individual bases rather than basing on whether it's in thumb
mode.
llvm-svn: 76698
2009-07-21 23:56:01 +00:00
f206d925a5
Fix comment.
...
llvm-svn: 76693
2009-07-21 23:54:22 +00:00
9bd736e2f7
no really, I can spell!
...
llvm-svn: 76679
2009-07-21 23:36:01 +00:00
cfb01e26bc
add an API so target-independent codegen can determine if a constant
...
pool entry will require relocations against it. I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.
llvm-svn: 76678
2009-07-21 23:34:23 +00:00
18e32946f8
Add fake v7 itineraries for now.
...
llvm-svn: 76612
2009-07-21 18:54:14 +00:00
100865e59d
make AsmPrinter::doFinalization iterate over the global variables
...
and call PrintGlobalVariable, allowing elimination and simplification
of various targets.
llvm-svn: 76604
2009-07-21 18:38:57 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
...
llvm-svn: 76600
2009-07-21 18:15:26 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
...
llvm-svn: 76520
2009-07-21 00:31:12 +00:00
711b9e809c
CMP and TST define CPSR, not use it.
...
llvm-svn: 76489
2009-07-20 22:13:31 +00:00
1bcfbff7af
Rename Mangler linkage enums to something less gross.
...
llvm-svn: 76456
2009-07-20 19:41:27 +00:00
802a0b576f
Use t2LDRri12 for frame index loads.
...
llvm-svn: 76424
2009-07-20 15:55:39 +00:00
fa60698c29
Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.
...
llvm-svn: 76401
2009-07-20 06:59:32 +00:00
d214b72962
Model fpscr to prevent fcmped / fcmpezs etc from being deleted.
...
llvm-svn: 76390
2009-07-20 02:12:31 +00:00
a3c6f6bffa
Add plumbing for the `linker_private' linkage type. This type is meant for
...
"private" symbols which the assember shouldn't strip, but which the linker may
remove after evaluation. This is mostly useful for Objective-C metadata.
This is plumbing, so we don't have a use of it yet. More to come, etc.
llvm-svn: 76385
2009-07-20 01:03:30 +00:00
151b23d043
Fix a regression from 76124. Thumb1 instructions default to S bit being true.
...
llvm-svn: 76374
2009-07-19 19:16:46 +00:00
83779208cc
Add dependencies from TargetInfo onto .td generation.
...
- Shouldn't really be necessary, but currently .inc files get included into
some main target headers.
llvm-svn: 76349
2009-07-19 00:21:12 +00:00
67038c1333
Put Target definitions inside Target specific header, and llvm namespace.
...
llvm-svn: 76344
2009-07-18 23:03:22 +00:00
15d54b9504
r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
...
the X86 Emitter. This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.
llvm-svn: 76211
2009-07-17 18:49:39 +00:00
aaf48343fb
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
...
llvm-svn: 76155
2009-07-17 05:43:12 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
...
Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
...
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
c151c51ea0
Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLink
...
variables.
- Module initialization functions supplanted the need for these.
llvm-svn: 75886
2009-07-16 01:55:13 +00:00
d97db682a3
Lift addAssemblyEmitter into LLVMTargetMachine.
...
- No functionality change.
llvm-svn: 75859
2009-07-15 23:34:19 +00:00
c901392ba4
Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.
...
- No intended functionality change.
llvm-svn: 75848
2009-07-15 22:33:19 +00:00
5302288c90
Remove old style hacks to register AsmPrinter into TargetMachine.
...
- No intended functionality change.
llvm-svn: 75843
2009-07-15 22:01:32 +00:00
e833810a5e
Reapply TargetRegistry refactoring commits.
...
--- Reverse-merging r75799 into '.':
U test/Analysis/PointerTracking
U include/llvm/Target/TargetMachineRegistry.h
U include/llvm/Target/TargetMachine.h
U include/llvm/Target/TargetRegistry.h
U include/llvm/Target/TargetSelect.h
U tools/lto/LTOCodeGenerator.cpp
U tools/lto/LTOModule.cpp
U tools/llc/llc.cpp
U lib/Target/PowerPC/PPCTargetMachine.h
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCTargetMachine.cpp
U lib/Target/PowerPC/PPC.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/ARMTargetMachine.h
U lib/Target/ARM/ARM.h
U lib/Target/XCore/XCoreTargetMachine.cpp
U lib/Target/XCore/XCoreTargetMachine.h
U lib/Target/PIC16/PIC16TargetMachine.cpp
U lib/Target/PIC16/PIC16TargetMachine.h
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/Alpha/AlphaTargetMachine.cpp
U lib/Target/Alpha/AlphaTargetMachine.h
U lib/Target/X86/X86TargetMachine.h
U lib/Target/X86/X86.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.cpp
U lib/Target/MSP430/MSP430TargetMachine.h
U lib/Target/CppBackend/CPPTargetMachine.h
U lib/Target/CppBackend/CPPBackend.cpp
U lib/Target/CBackend/CTargetMachine.h
U lib/Target/CBackend/CBackend.cpp
U lib/Target/TargetMachine.cpp
U lib/Target/IA64/IA64TargetMachine.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/IA64/IA64TargetMachine.h
U lib/Target/IA64/IA64.h
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/CellSPU/SPUTargetMachine.h
U lib/Target/CellSPU/SPU.h
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/CellSPU/SPUTargetMachine.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
U lib/Target/Mips/MipsTargetMachine.cpp
U lib/Target/Mips/MipsTargetMachine.h
U lib/Target/Mips/Mips.h
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Sparc/SparcTargetMachine.cpp
U lib/Target/Sparc/SparcTargetMachine.h
U lib/ExecutionEngine/JIT/TargetSelect.cpp
U lib/Support/TargetRegistry.cpp
llvm-svn: 75820
2009-07-15 20:24:03 +00:00
338191cd67
Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to repair broken LLVM-GCC build.
...
Will revert 75770 in the llvm-gcc trunk.
llvm-svn: 75799
2009-07-15 17:27:11 +00:00
f39120571b
Thumb-2 only support [base_reg + offset_reg] addressing, not [base_reg - offset_reg].
...
llvm-svn: 75789
2009-07-15 15:50:19 +00:00
eb8c83b4c3
Replace large swaths of copy-n-paste code with obvious helper function...
...
- Which was already present in the module!
- I skipped this xform for Alpha, since it runs an extra pass during assembly
emission, but not when emitting assembly via the DumpAsm flag.
- No functionality change.
--
ddunbar@giles:llvm$ svn diff | grep '^- ' | sort | uniq -c
18 - PM.add(AsmPrinterCtor(ferrs(), *this, true));
18 - assert(AsmPrinterCtor && "AsmPrinter was not linked in");
18 - if (AsmPrinterCtor)
18 - if (DumpAsm) {
18 - }
ddunbar@giles:llvm$ svn diff | grep '^+ ' | sort | uniq -c
18 + addAssemblyEmitter(PM, OptLevel, true, ferrs());
18 + if (DumpAsm)
--
llvm-svn: 75782
2009-07-15 12:49:15 +00:00
863e587d27
Kill off old (TargetMachine level, not Target level) match quality functions.
...
llvm-svn: 75780
2009-07-15 12:26:05 +00:00
6db8134e80
Provide TargetMachine implementations with reference to Target they were created
...
from.
- This commit is almost entirely propogating the reference through the
TargetMachine subclasses' constructor calls.
llvm-svn: 75778
2009-07-15 12:11:05 +00:00
b22f50e4c4
Register Target's TargetMachine and AsmPrinter in the new registry.
...
- This abuses TargetMachineRegistry's constructor for now, this will get
cleaned up in time.
llvm-svn: 75762
2009-07-15 09:22:31 +00:00
56e2947a33
Add TargetInfo libraries for all targets.
...
- Intended to match current TargetMachine implementations.
- No facilities for linking these in yet.
llvm-svn: 75751
2009-07-15 06:35:19 +00:00
a2268c0b19
convert arm/darwin stubs to use the mangler to synthesize all the names instead of
...
doing it with printSuffixedName.
llvm-svn: 75741
2009-07-15 04:41:01 +00:00
55452c2bea
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
...
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
llvm-svn: 75737
2009-07-15 04:12:33 +00:00
53fe736214
convert [Hidden]GVNonLazyPtrs to compute the global and stub names
...
with the mangler (like x86 and ppc), instead of going through
printSuffixedName.
llvm-svn: 75736
2009-07-15 03:12:43 +00:00
b6b2530000
Move EVER MORE stuff over to LLVMContext.
...
llvm-svn: 75703
2009-07-14 23:09:55 +00:00
a9111b9f97
Fix bad indentation and 80-col violation.
...
llvm-svn: 75686
2009-07-14 21:45:58 +00:00
95bad85498
Check for PRE_INC and POST_INC.
...
llvm-svn: 75683
2009-07-14 21:29:29 +00:00
a31f96cf2b
Have asm printers use formatted_raw_ostream directly to avoid a
...
dynamic_cast<>.
llvm-svn: 75670
2009-07-14 20:18:05 +00:00
4ad7797e1c
hasThumb2() does not mean we are compiling for thumb, must also check isThumb().
...
llvm-svn: 75660
2009-07-14 18:48:51 +00:00
3f17aee94b
Remove an extra space.
...
llvm-svn: 75658
2009-07-14 18:44:34 +00:00
8c9a96b966
Reapply my previous asmprinter changes now with more testing and two
...
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
llvm-svn: 75646
2009-07-14 18:17:16 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
...
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
6c5282e3db
Revert r75615, which depended on 75610.
...
--- Reverse-merging r75615 into '.':
U lib/Target/XCore/XCoreAsmPrinter.cpp
U lib/Target/PIC16/PIC16AsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/MSP430/MSP430AsmPrinter.cpp
U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp
U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
U lib/Target/MSIL/MSILWriter.cpp
U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp
U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
llvm-svn: 75637
2009-07-14 16:12:13 +00:00
027c84d2c8
Rename getValueName -> getMangledName.
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llvm-svn: 75615
2009-07-14 06:18:50 +00:00
bd9ba429ca
1. In Thumb mode, select tBx instead of ARM variants.
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2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
72b80ac9b1
Fix detection of valid BFC immediates.
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llvm-svn: 75576
2009-07-14 00:57:56 +00:00
7bbb9a91ab
Fix an obvious copy-and-paste error.
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llvm-svn: 75566
2009-07-14 00:23:44 +00:00
acb9927fd8
Revert 75309.
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llvm-svn: 75562
2009-07-14 00:01:42 +00:00
160521095b
Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).
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llvm-svn: 75513
2009-07-13 21:43:08 +00:00
844d6c82a7
Fix comment typos.
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llvm-svn: 75479
2009-07-13 18:11:36 +00:00
69208f0f9e
Remove extra \n from LLVM_UNREACHABLE calls.
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llvm-svn: 75416
2009-07-12 07:15:17 +00:00
56d0659726
assert(0) -> LLVM_UNREACHABLE.
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Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
llvm-svn: 75379
2009-07-11 20:10:48 +00:00
017288a4fc
Don't put IT instruction before conditional branches.
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llvm-svn: 75361
2009-07-11 07:26:20 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
bf041366c4
80 col violation.
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llvm-svn: 75358
2009-07-11 06:37:27 +00:00
a51f8ebf1a
Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of
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quad registers and the Q4PR class holds sets of 4 quad registers.
llvm-svn: 75309
2009-07-10 23:09:06 +00:00
81cdd21dcb
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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llvm-svn: 75254
2009-07-10 17:03:29 +00:00
c9b1efd515
t2LDM_RET does not fall-through.
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llvm-svn: 75250
2009-07-10 15:33:46 +00:00
0006349f4d
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing
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the cmake build.
llvm-svn: 75246
2009-07-10 08:31:50 +00:00
01b8630879
More info about Thumb1 predication support.
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llvm-svn: 75220
2009-07-10 02:10:17 +00:00
61671c87a7
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
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llvm-svn: 75219
2009-07-10 02:09:04 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
3b88dd6900
Move isPredicated from .cpp to .h
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llvm-svn: 75217
2009-07-10 01:38:27 +00:00
5d8a1b2c18
80 col violation.
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llvm-svn: 75212
2009-07-10 00:45:16 +00:00
223ac25930
Remove a bogus assertion.
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llvm-svn: 75206
2009-07-10 00:23:48 +00:00
75aa75cabc
Replace TM.getRegisterInfo() calls by TRI instance variable.
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Use getAsmName() method instead of accessing AsmName field directly.
llvm-svn: 75205
2009-07-10 00:14:05 +00:00
9ce44e2521
Handle 'a' modifier on inline assembly operands.
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This is part of the fix for pr4521.
llvm-svn: 75201
2009-07-09 23:54:51 +00:00
26b2ba4285
Added Thumb IT instruction.
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llvm-svn: 75198
2009-07-09 23:43:36 +00:00
ae4f2e142a
Another todo entry.
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llvm-svn: 75192
2009-07-09 23:17:28 +00:00
4605e8aac4
Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.
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llvm-svn: 75190
2009-07-09 23:11:34 +00:00
1622d7b429
Fix ldm / stm unified syntax; add t2LDM_RET.
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llvm-svn: 75188
2009-07-09 22:58:39 +00:00
a02fc2d327
LDM_RET should be marked mayLoad.
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llvm-svn: 75187
2009-07-09 22:57:41 +00:00
7591d02c84
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
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Note, we are not yet generating these instructions.
llvm-svn: 75181
2009-07-09 22:21:59 +00:00
f9870125fc
Add a Thumb readme entry.
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llvm-svn: 75173
2009-07-09 20:50:52 +00:00
ad93707e16
Correct comment.
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llvm-svn: 75172
2009-07-09 20:40:44 +00:00
7bf08beb2e
Handle Thumb-2 addressing modes during FP elimination.
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llvm-svn: 75158
2009-07-09 18:35:52 +00:00
0504e0a222
Thread LLVMContext through MVT and related parts of SDISel.
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llvm-svn: 75153
2009-07-09 17:57:24 +00:00
27e32c092e
Reorg includes.
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llvm-svn: 75115
2009-07-09 06:49:09 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
5edd90cbbc
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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llvm-svn: 75048
2009-07-08 21:03:57 +00:00
f8d479c1ce
Missed an exit during the conversion.
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Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.
llvm-svn: 75045
2009-07-08 20:55:50 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
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Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
1d298fd75b
Implement NEON vst1 instruction.
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llvm-svn: 75037
2009-07-08 20:32:02 +00:00
03ab0bbb24
Generalize opcode selection in ARMBaseRegisterInfo.
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llvm-svn: 75036
2009-07-08 20:28:28 +00:00
b009980f0b
Fix cmake build.
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Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt
llvm-svn: 75035
2009-07-08 20:13:41 +00:00
9ca33e8a9f
Push methods into base class in preparation for sharing.
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llvm-svn: 75020
2009-07-08 18:31:39 +00:00
f731a2df6b
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
6dd2730024
Start converting to new error handling API.
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cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
eebf58805c
Start breaking out common base functionality for register info.
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llvm-svn: 75016
2009-07-08 17:28:55 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
a21d3daadc
Remove the vicmp and vfcmp instructions. Because we never had a release with
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these instructions, no autoupgrade or backwards compatibility support is
provided.
llvm-svn: 74991
2009-07-08 03:04:38 +00:00
14965760a7
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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llvm-svn: 74988
2009-07-08 01:46:35 +00:00
b61e3a83ee
Add a todo.
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llvm-svn: 74976
2009-07-08 00:05:05 +00:00
f0080b734a
Also statically set bit 25 for BR_JT instructions.
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llvm-svn: 74974
2009-07-07 23:45:10 +00:00
2cff076cfe
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
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llvm-svn: 74972
2009-07-07 23:40:25 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
02a44edf12
Add BX and BXr9 encodings. Patch by Sean Callanan.
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llvm-svn: 74938
2009-07-07 19:16:24 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
7c9434399d
80 col violation.
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llvm-svn: 74888
2009-07-07 01:16:41 +00:00
3d8ccdb4be
isThumb2 really should mean thumb2 only, not thumb2+.
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llvm-svn: 74871
2009-07-06 22:29:14 +00:00
40398233b7
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
e63b0e6f79
Added ARM::mls for armv6t2.
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llvm-svn: 74866
2009-07-06 22:05:45 +00:00
5661ea68e7
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
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cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
2009-07-06 05:09:34 +00:00
aea6059ed4
Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.
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With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
llvm-svn: 74764
2009-07-03 06:44:53 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
6d9041100b
Add Thumb2 load / store multiple instructions. Not used yet.
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llvm-svn: 74749
2009-07-03 00:18:36 +00:00
f30ee8820a
t2LDR_PRE etc are loads.
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llvm-svn: 74741
2009-07-03 00:08:19 +00:00
53cdf022b6
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
ade05a37f1
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
6141511621
CMake build fixes, from Xerxes Ranby
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llvm-svn: 74720
2009-07-02 18:53:52 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
844f0b4562
80 col violation.
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llvm-svn: 74693
2009-07-02 06:44:30 +00:00
2c450d35ae
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
979da0e590
80 col violation.
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llvm-svn: 74683
2009-07-02 01:30:04 +00:00
d9c55368e7
Factor out ARM indexed load matching code.
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llvm-svn: 74681
2009-07-02 01:23:32 +00:00
deb35afd23
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
affb68bd08
Fix a comment typo.
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llvm-svn: 74650
2009-07-01 21:59:43 +00:00
bbbf805049
Fix up a comment: besides the >80col lines, the operation for this
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addressing mode is encoded in the second operand, not the third.
llvm-svn: 74641
2009-07-01 21:22:45 +00:00
512ff7353e
Update comments to make it clear that the function alignment is the Log2 of the
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bytes and not bytes.
llvm-svn: 74624
2009-07-01 18:50:55 +00:00
d379e896ff
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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llvm-svn: 74580
2009-07-01 01:59:31 +00:00
75c12e1569
Remove unused AsmPrinter OptLevel argument, and propogate.
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- This more or less amounts to a revert of r65379. I'm curious to know what
happened that caused this variable to become unused.
llvm-svn: 74579
2009-07-01 01:48:54 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
a83100f687
Thumb-2 load and store double description. But nothing yet creates them.
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llvm-svn: 74566
2009-06-30 22:50:01 +00:00
31ceb1bcba
Add an "alignment" field to the MachineFunction object. It makes more sense to
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have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
llvm-svn: 74564
2009-06-30 22:38:32 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
24a3724b04
Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt
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to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.
llvm-svn: 74421
2009-06-29 13:11:32 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
0f2158b35f
Simplify a bit
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llvm-svn: 74385
2009-06-27 12:59:03 +00:00
a1b5b18bd0
ARM refactoring. Step 2: split RegisterInfo
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llvm-svn: 74384
2009-06-27 12:16:40 +00:00
33400e3670
Add ThumbInstrInfo.cpp to the CMake makefiles
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llvm-svn: 74382
2009-06-27 07:44:59 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Evan Cheng