Commit Graph

377441 Commits

Author SHA1 Message Date
Siva Chandra 7bd3702b64 [libc] Extend the current fenv functions to aarch64.
This change does not try to move the common parts of x86 and aarch64 and
build few abstractions over them. While this is possible, x86 story
needs a bit of cleanup, especially around manipulation of the mxcsr
register. Moreover, on x86 one can raise exceptions without performing
exception raising operations. So, all of this can be done in follow up
patches.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D94947
2021-01-19 12:47:54 -08:00
Alexey Bataev b272698de7 [OPENMP]Do not use OMP_MAP_TARGET_PARAM for data movement directives.
OMP_MAP_TARGET_PARAM flag is used to mark the data that shoud be passed
as arguments to the target kernels, nothing else. But the compiler still
marks the data with OMP_MAP_TARGET_PARAM flags even if the data is
passed to the data movement directives, like target data, target update
etc. This flag is just ignored for this directives and the compiler does
not need to emit it.

Reviewed By: cchen

Differential Revision: https://reviews.llvm.org/D91261
2021-01-19 12:41:15 -08:00
Arthur Eubanks cabe1b1124 [polly][NewPM][test] Fix polly tests under -enable-new-pm
In preparation for turning on opt's -enable-new-pm by default, this pins
uses of passes via the legacy "opt -passname" with pass names beginning
with "polly-" and "polyhedral-info" to the legacy PM. Many of these
tests use -analyze, which isn't supported in the new PM.

(This doesn't affect uses of "opt -passes=passname").

rL240766 accidentally removed `-polly-prepare` in
phi_not_grouped_at_top.ll, and it also doesn't use the output of
-analyze.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D94266
2021-01-19 12:38:58 -08:00
Mircea Trofin 27afc091e2 [NFC] Disallow unused prefixes under Other
Differential Revision: https://reviews.llvm.org/D94853
2021-01-19 12:22:29 -08:00
Alexey Bataev e463bd53c0 Revert "[SLP]Merge reorder and reuse shuffles."
This reverts commit 438682de6a to fix the
bug with the reducing size of the resulting vector for the entry node
with multiple users.
2021-01-19 11:48:04 -08:00
Jeroen Dobbelaere d8ffaa9f72 [NFC] cleanup noalias2.ll test
D75825 and D75828 modified llvm/test/Transforms/Inline/noalias2.ll to handle llvm.assume. The checking though was broken.
The NO_ASSUME has been replaced by a normal CHECK; the ASSUME rules were never triggered and have been removed.
The test checks have been regenerated.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94978
2021-01-19 20:47:02 +01:00
Mitch Phillips 5b7aef6eb4 Revert "[PDB] Defer relocating .debug$S until commit time and parallelize it"
This reverts commit 6529d7c5a4.

Reason: Broke the ASan buildbots.
http://lab.llvm.org:8011/#/builders/99/builds/1567
2021-01-19 11:45:48 -08:00
peter klausler 24e8e21f19 [flang] Refine WhyNotModifiable()
The utility routine WhyNotModifiable() needed to become more
aware of the use of pointers in data-refs; the targets of
pointer components are sometimes modifiable even when the
leftmost ("base") symbol of a data-ref is not.

Added a new unit test for WhyNotModifiable() that uses internal
READ statements (mostly), since I/O semantic checking uses
WhyNotModifiable() for all its definability checking.

Differential Revision: https://reviews.llvm.org/D94849
2021-01-19 11:44:51 -08:00
Fangrui Song 5fcb412ed0 [ELF] Support R_PPC64_ADDR16_HIGH
R_PPC64_ADDR16_HI represents bits 16-31 of a 32-bit value
R_PPC64_ADDR16_HIGH represents bits 16-31 of a 64-bit value.

In the Linux kernel, `LOAD_REG_IMMEDIATE_SYM` defined in `arch/powerpc/include/asm/ppc_asm.h`
uses @l, @high, @higher, @highest to load the 64-bit value of a symbol.

Fixes https://github.com/ClangBuiltLinux/linux/issues/1260
2021-01-19 11:42:53 -08:00
Fangrui Song e12e0d66c0 [ELF] Error for out-of-range R_PPC64_ADDR16_HA, R_PPC64_ADDR16_HI and their friends
There are no tests for REL16_* and TPREL16_*.
2021-01-19 11:42:52 -08:00
Fangrui Song d39adeaf44 [ELF] Improve R_PPC64_ADDR* relocation tests 2021-01-19 11:42:51 -08:00
Jonas Devlieghere a4b42c621b [llvm] Protect signpost map with a mutex
Use a mutex to protect concurrent access to the signpost map. This fixes
nondeterministic crashes in LLDB that appeared after using signposts in
the timer implementation.

Differential revision: https://reviews.llvm.org/D94285
2021-01-19 11:41:54 -08:00
Wim Leflere 6ac9cb2a7c [libc++][P1679] add string contains
C++23 string contains implementation and tests

Paper: https://wg21.link/P1679R3
Standard (string): https://eel.is/c++draft/string.contains
Standard (string_view): https://eel.is/c++draft/string.view.ops#lib:contains,basic_string_view

Differential Revision: https://reviews.llvm.org/D93912
2021-01-19 14:35:07 -05:00
Mariya Podchishchaeva 7113de301a [ScalarizeMaskedMemIntrin] Add missing dependency
The pass has dependency on 'TargetTransformInfoWrapperPass', but the
corresponding call to INITIALIZE_PASS_DEPENDENCY was missing.

Differential Revision: https://reviews.llvm.org/D94916
2021-01-19 22:33:47 +03:00
Nikita Popov 21443381c0 Reapply [InstCombine] Replace one-use select operand based on condition
Relative to the original change, this adds a check that the
instruction on which we're replacing operands is safe to speculatively
execute, because that's what we're effectively doing. We're executing
the instruction with the replaced operand, which is fine if it's pure,
but not fine if can cause side-effects or UB (aka is not speculatable).

Additionally, we cannot (generally) replace operands in phi nodes,
as these may refer to a different loop iteration. This is also covered
by the speculation check.

-----

InstCombine already performs a fold where X == Y ? f(X) : Z is
transformed to X == Y ? f(Y) : Z if f(Y) simplifies. However,
if f(X) only has one use, then we can always directly replace the
use inside the instruction. To actually be profitable, limit it to
the case where Y is a non-expr constant.

This could be further extended to replace uses further up a one-use
instruction chain, but for now this only looks one level up.

Among other things, this also subsumes D94860.

Differential Revision: https://reviews.llvm.org/D94862
2021-01-19 20:26:38 +01:00
Nikita Popov bedbb58203 [InstCombine] Add additional tests for select operand replacement (NFC)
In particular, add tests for speculatable and non-speculatable
instructions.
2021-01-19 20:26:38 +01:00
Arthur Eubanks a231786909 [wasm][LLD] Rename --lto-new-pass-manager to --no-lto-legacy-pass-manager
This follows a similar ELF change.

Reviewed By: MaskRay, sbc100

Differential Revision: https://reviews.llvm.org/D93253
2021-01-19 11:22:40 -08:00
Craig Topper ce8b3937dd [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
If we are able to compare with 0 instead of 1, we might be able
to fold the setcc into a beqz/bnez.

Often these setccs start life as an xor that gets converted to
a setcc by DAG combiner's rebuildSetcc. I looked into a detecting
(xor X, 1) and converting to (seteq X, 0) based on boolean contents
being 0/1 in rebuildSetcc instead of using computeKnownBits. It was
very perturbing to AMDGPU tests which I didn't look closely at.
It had a few changes on a couple other targets, but didn't seem
to be much if any improvement.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94730
2021-01-19 11:21:48 -08:00
Shilei Tian 82e537a9d2 [Clang][OpenMP] Fixed an issue that clang crashed when compiling OpenMP program in device only mode without host IR
D94745 rewrites the `deviceRTLs` using OpenMP and compiles it by directly
calling the device compilation. `clang` crashes because entry in
`OffloadEntriesDeviceGlobalVar` is unintialized. Current design supposes the
device compilation can only be invoked after host compilation with the host IR
such that `clang` can initialize `OffloadEntriesDeviceGlobalVar` from host IR.
This avoids us using device compilation directly, especially when we only have
code wrapped into `declare target` which are all device code. The same issue
also exists for `OffloadEntriesInfoManager`.

In this patch, we simply initialized an entry if it is not in the maps. Not sure
we need an option to tell the device compiler that it is invoked standalone.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D94871
2021-01-19 14:18:42 -05:00
Louis Dionne 933518fff8 [libc++] Make LIBCXX_ENABLE_FILESYSTEM fully consistent
Previously, LIBCXX_ENABLE_FILESYSTEM controlled only whether the filesystem
support was compiled into libc++'s library. This commit promotes the
setting to a first-class option like LIBCXX_ENABLE_LOCALIZATION, where
the whole library is aware of the setting and features that depend on
<filesystem> won't be provided at all. The test suite is also properly
annotated such that tests that depend on <filesystem> are disabled when
the library doesn't support it.

This is an alternative to https://llvm.org/D94824, but also an improvement
along the lines of LIBCXX_ENABLE_LOCALIZATION that I had been wanting to
make for a while.

Differential Revision: https://reviews.llvm.org/D94921
2021-01-19 14:15:48 -05:00
Louis Dionne 68dba7eae1 [libc++] Unbreak the debug mode
When the Debug mode is enabled, we disable extern declarations because we
don't want to use the functions compiled in the library, which might not
have had the debug mode enabled when built. However, some extern declarations
need to be kept, because code correctness depends on it.

31e820378b removed those declarations, which had the unintended
consequence of breaking the debug build. This commit fixes that by
re-introducing a separate macro for the required extern declarations,
and adds a comment so that we don't fall into that trap in the future.

Differential Revision: https://reviews.llvm.org/D94718
2021-01-19 14:15:31 -05:00
Reid Kleckner e678656625 Add bounds checking assertions to APValue, NFC
These checks help find llvm.org/pr48582 without ASan
2021-01-19 11:15:02 -08:00
Reid Kleckner 6f69f2ed61 Consider ASan messages interesting for creduce
Helped me reduce llvm.org/pr48582
2021-01-19 11:15:02 -08:00
Jeroen Dobbelaere 121cac01e8 [noalias.decl] Look through llvm.experimental.noalias.scope.decl
Just like llvm.assume, there are a lot of cases where we can just ignore llvm.experimental.noalias.scope.decl.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93042
2021-01-19 20:09:42 +01:00
Richard Smith 987760b463 [www] Fix background color in table cell. 2021-01-19 11:04:31 -08:00
Brendon Cahoon 57443bfb4a [Hexagon] Fix segment start to adjust for gaps between segments
The Hexagon Vector Combine pass genertes stores for a complete
aligned vector. The start of each section is a multiple of the
vector size, so that value is passed to normalize to compute
the offset of the stores in the section.  The first store may
not occur at offset 0 when there is a gap between sections.
2021-01-19 12:49:39 -06:00
Utkarsh Saxena 17846ed5af [clangd] Use ASTSignals in Heuristics CC Ranking.
Differential Revision: https://reviews.llvm.org/D94927
2021-01-19 19:48:42 +01:00
Jay Foad 18cb7441b6 [AMDGPU] Simpler names for arch-specific ttmp registers. NFC.
Rename the *_gfx9_gfx10 ttmp registers to *_gfx9plus for simplicity,
and use the corresponding isGFX9Plus predicate to decide when to use
them instead of the old *_vi versions.

Differential Revision: https://reviews.llvm.org/D94975
2021-01-19 18:47:14 +00:00
Jessica Paquette cbf5246359 Fix buildbot after cfc6073017
Windows buildbots were not happy with using find_if + instructionsWithoutDebug.

In cfc6073017, instructionsWithoutDebug is not technically necessary. So,
just iterate over the block directly.

http://lab.llvm.org:8011/#/builders/127/builds/4732/steps/7/logs/stdio
2021-01-19 10:38:04 -08:00
Jessica Paquette cfc6073017 [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load
This is a restricted version of the combine in `DAGCombiner::MatchLoadCombine`.
(See D27861)

This tries to recognize patterns like below (assuming a little-endian target):

```
s8* x = ...
s32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24)
->
s32 val = *((i32)a)

s8* x = ...
s32 val = a[3] | (a[2] << 8) | (a[1] << 16) | (a[0] << 24)
->
s32 val = BSWAP(*((s32)a))
```

(This patch also handles the big-endian target case as well, in which the first
example above has a BSWAP, and the second example above does not.)

To recognize the pattern, this searches from the last G_OR in the expression
tree.

E.g.

```
    Reg   Reg
     \    /
      OR_1   Reg
       \    /
        OR_2
          \     Reg
           .. /
          Root
```

Each non-OR register in the tree is put in a list. Each register in the list is
then checked to see if it's an appropriate load + shift logic.

If every register is a load + potentially a shift, the combine checks if those
loads + shifts, when OR'd together, are equivalent to a wide load (possibly with
a BSWAP.)

To simplify things, this patch

(1) Only handles G_ZEXTLOADs (which appear to be the common case)
(2) Only works in a single MachineBasicBlock
(3) Only handles G_SHL as the bit twiddling to stick the small load into a
    specific location

An IR example of this is here: https://godbolt.org/z/4sP9Pj (lifted from
test/CodeGen/AArch64/load-combine.ll)

At -Os on AArch64, this is a 0.5% code size improvement for CTMark/sqlite3,
and a 0.4% improvement for CTMark/7zip-benchmark.

Also fix a bug in `isPredecessor` which caused it to fail whenever `DefMI` was
the first instruction in the block.

Differential Revision: https://reviews.llvm.org/D94350
2021-01-19 10:24:27 -08:00
Fraser Cormack 9c6a00fe99 [RISCV] Add ISel patterns for scalable mask exts & truncs
Original patch by @rogfer01.

This patch adds support for sign-, zero-, and any-extension from
scalable mask vector types to integer vector types, as well as
truncation in the opposite direction.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94590
2021-01-19 18:13:15 +00:00
Abhina Sreeskantharajan 88e7c3498c [SystemZ][z/OS] Fix Permission denied pattern matching
On z/OS, the error message "EDC5111I Permission denied." is not matched correctly in lit tests. This patch updates the check expression to match successfully.

Differential Revision: https://reviews.llvm.org/D94432
2021-01-19 13:05:52 -05:00
Michael Kruse 842314b5f0 [Polly] Update isl to isl-0.23-61-g24e8cd12.
This fixes llvm.org/PR48554

Some test cases had to be updated because the hash function for
union_maps have been changed which affects the output order.
2021-01-19 12:01:31 -06:00
Raphael Isemann 2f80995090 [lldb][docs] Update .htaccess to redirect from old SB API documentation to new one
This is mostly SEO so that the new API can take over the old API when people
search for the different SB* classes. Sadly epydoc decided to throw in a -class
prefix behind all the class file names, so we can't just overwrite the old files
with the newly generated ones.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D94900
2021-01-19 18:58:43 +01:00
David Green 6a563eef13 [ARM] Expand vXi1 VSELECT's
We have no lowering for VSELECT vXi1, vXi1, vXi1, so mark them as
expanded to turn them into a series of logical operations.

Differential Revision: https://reviews.llvm.org/D94946
2021-01-19 17:56:50 +00:00
Raphael Isemann 3cae8b3329 [lldb][docs] Add a doc page for enums and constants
Enums and constants are currently missing in the new LLDB Python API docs.

In theory we could just let them be autogenerated like the SB API classes, but sadly the generated documentation
suffers from a bunch of problems. Most of these problems come from the way SWIG is representing enums, which is
done by translating every single enum case into its own constant. This has a bunch of nasty effects:

* Because SWIG throws away the enum types, we can't actually reference the enum type itself in the API. Also because automodapi is impossible to script, this can't be fixed in post (at least without running like sed over the output files).
* The lack of enum types also causes that every enum *case* has its own full doc page. Having a full doc page that just shows a single enum case is pointless and it really slows down sphinx.
* There is no SWIG code for the enums, so there is also no place to write documentation strings for them. Also there is no support for copying the doxygen strings (which would be in the wrong format, but better than nothing) for enums (let alone our defines), so we can't really document all this code.
* Because the enum cases are just forwards to the native lldb module (which we mock), automodapi actually takes the `Mock` docstrings and adds it to every single enum case.

I don't see any way to solve this via automodapi or SWIG. The most reasonable way to solve this is IMHO to write a simple Clang tool
that just parses our enum/constant headers and emits an *.rst file that we check in. This way we can do all the LLDB-specific enum case and constant
grouping that we need to make a readable documentation page.

As we're without any real documentation until I get around to write that tool, I wrote a doc page for the enums/constants as a stop gap measure.
Most of this is done by just grepping our enum header and then manually cleaning up all the artifacts and copying the few doc strings we have.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D94959
2021-01-19 18:54:05 +01:00
Andrzej Warzynski cea3abc26f [flang][driver] Move isFixedFormSuffix and isFreeFormSuffix to flangFrontend
isFixedFormSuffix and isFreeFormSuffix should be defined in
flangFrontend rather than flangFrontendTool library. That's for 2
reasons:
  * these methods are used in flangFrontend rather than flangFrontendTool
  * flangFrontendTool depends on flangFrontend

As mentioned in the post-commit review for D94228, without this change
shared library builds fail.

Differential Revision: https://reviews.llvm.org/D94968
2021-01-19 17:47:40 +00:00
Stella Laurenzo 71b6b010e6 [mlir][python] Factor out standalone OpView._ods_build_default class method.
* This allows us to hoist trait level information for regions and sized-variadic to class level attributes (_ODS_REGIONS, _ODS_OPERAND_SEGMENTS, _ODS_RESULT_SEGMENTS).
* Eliminates some splicey python generated code in favor of a native helper for it.
* Makes it possible to implement custom, variadic and region based builders with one line of python, without needing to manually code access to the segment attributes.
* Needs follow-on work for region based callbacks and support for SingleBlockImplicitTerminator.
* A follow-up will actually add ODS support for generating custom Python builders that delegate to this new method.
* Also includes the start of an e2e sample for constructing linalg ops where this limitation was discovered (working progressively through this example and cleaning up as I go).

Differential Revision: https://reviews.llvm.org/D94738
2021-01-19 09:29:57 -08:00
Björn Schäpers cbdde495ba [clang-format] Apply Allman style to lambdas
Differential Revision: https://reviews.llvm.org/D94906
2021-01-19 18:17:01 +01:00
Nikita Popov 051ec9f5f4 [ValueTracking] Strengthen impliesPoison reasoning
Split impliesPoison into two recursive walks, one over V, the
other over ValAssumedPoison. This allows us to reason about poison
implications in a number of additional cases that are important
in practice. This is a generalized form of D94859, which handles
the cmp to cmp implication in particular.

Differential Revision: https://reviews.llvm.org/D94866
2021-01-19 18:04:23 +01:00
Jay Foad 0808c7009a [AMDGPU] Fix test case for D94010 2021-01-19 16:46:47 +00:00
KareemErgawy-TomTom 27820496a7 [MLIR][SPIRV] Add `SignedOp` trait.
This commit adds a new trait that can be attached to ops that have
signed semantics.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D94896
2021-01-19 17:40:40 +01:00
Jay Foad de2f942399 [AMDGPU] Simplify test case for D94010 2021-01-19 16:36:43 +00:00
Hansang Bae 2d911f7c72 [OpenMP] Fix atomic entries for captured logical operation
Added missing code for the captured atomic operation.

Differential Revision: https://reviews.llvm.org/D94848
2021-01-19 09:59:28 -06:00
Fraser Cormack 15fd6bae0e [RISCV] Extend RVV VType info with the type's AVL (NFC)
This patch factors out the "VLMax" operand passed to most
scalable-vector ISel patterns into a property of each VType.

This is seen as a preparatory change to allow RVV in the future to
more easily support fixed-length vector types with constrained vector
lengths, with the AVL operand set to the length of the fixed-length
vector. It has no effect on the scalable code generation path.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D94594
2021-01-19 15:46:56 +00:00
David Green f373b30923 [ARM] Add MVE add.sat costs
This adds some basic MVE sadd_sat/ssub_sat/uadd_sat/usub_sat costs,
based on when the instruction is legal. With smaller than legal types
that are promoted we generate shr(qadd(shl, shl)), so the cost is 4
appropriately.

Differential Revision: https://reviews.llvm.org/D94958
2021-01-19 15:38:46 +00:00
Valentin Clement 6bd0a4451c [flang][directive] Get rid of flangClassValue in TableGen
The TableGen emitter for directives has two slots for flangClass information and this was mainly
to be able to keep up with the legacy openmp parser at the time. Now that all clauses are encapsulated in
AccClause or OmpClause, these two strings are not necessary anymore and were the the source of couple
of problem while working with the generic structure checker for OpenMP.
This patch remove the flangClassValue string from DirectiveBase.td and use the string flangClass as the
placeholder for the encapsulated class.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D94821
2021-01-19 10:28:46 -05:00
Victor Huang 909d6c86ea [PowerPC] Fix the check for the instruction using FRSP/XSRSP output register
When performing peephole optimization to simplify the code, after removing
passed FPSP/XSRSP instruction we will set any uses of that FRSP/XSRSP to the
source of the FRSP/XSRSP.

We are finding the machine instruction using virtual register holding FRSP/XSRSP
results by searching all following instructions and encountering an issue
that the first use of the virtual register is a debug MI causing:
1. virtual register in the debug MI removed unexpectedly.
2. virtual register used in non-debug MI not replaced with the source of
  FRSP/XSRSP. which stays in a undef status.

This patch fix the issue by only searching non-debug machine instruction using
virtual register holding FRSP/XSRSP results when the vr only has one non debug
usage.

Differential Revisien: https://reviews.llvm.org/D94711
Reviewed by: nemanjai
2021-01-19 09:20:03 -06:00
Raul Tambre 480643a95c [CMake] Remove dead code setting policies to NEW
cmake_minimum_required(VERSION) calls cmake_policy(VERSION),
which sets all policies up to VERSION to NEW.
LLVM started requiring CMake 3.13 last year, so we can remove
a bunch of code setting policies prior to 3.13 to NEW as it
no longer has any effect.

Reviewed By: phosek, #libunwind, #libc, #libc_abi, ldionne

Differential Revision: https://reviews.llvm.org/D94374
2021-01-19 17:19:36 +02:00
Utkarsh Saxena 8bf7116d50 [clangd] Index local classes, virtual and overriding methods.
Previously we did not record local class declarations. Now with features like
findImplementation and typeHierarchy, we have a need to index such local
classes to accurately report subclasses and implementations of methods.

Performance testing results:
- No changes in indexing timing.
- No significant change in memory usage.
- **1%** increase in #relations.
- **0.17%** increase in #refs.
- **0.22%** increase #symbols.

**New index stats**
Time to index: **4:13 min**
memory usage **543MB**
number of symbols: **521.5K**
number of refs: **8679K**
number of relations: **49K**

**Base Index stats**
Time to index: **4:15 min**
memory usage **542MB**
number of symbols: **520K**
number of refs: **8664K**
number of relations: **48.5K**

Fixes: https://github.com/clangd/clangd/issues/644

Differential Revision: https://reviews.llvm.org/D94785
2021-01-19 16:18:48 +01:00