Commit Graph

24286 Commits

Author SHA1 Message Date
Adam Nemet 571eb5fc91 [PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate
The SplitIndexingFromLoad changes exposed a latent isel bug in the PowerPC64
backend.  We matched an immediate offset with STWX8 even though it only
supports register offset.

The culprit is the complex-pattern predicate, SelectAddrIdx, which decides
that if the offset is not ISD::Constant it must be a register.

Many thanks to Bill Schmidt for testing this.

llvm-svn: 209219
2014-05-20 17:20:34 +00:00
Daniel Sanders a714fcb02a Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests
After discussion with Zoran, we have decided to temporarily revert this commit.
It's causing some difficult to resolve conflicts and we are under time pressure
to deliver an initial MIPS64r6 compiler.

We will re-apply an equivalent patch once the time pressure has passed.

llvm-svn: 209211
2014-05-20 14:46:24 +00:00
Bradley Smith cf5b09b5dc [ARM64] Port basic-a64-diagnostics.s over to ARM64
llvm-svn: 209207
2014-05-20 13:33:41 +00:00
Benjamin Kramer 7bd6bee385 Legalizer: Make bswap promotion safe for vectors.
llvm-svn: 209202
2014-05-20 09:42:31 +00:00
Christian Pirker 875629f713 ARMEB: Additional test files for ARM fixups
llvm-svn: 209200
2014-05-20 09:24:37 +00:00
Tim Northover 9a24f88a37 TableGen: convert InstAlias's Emit bit to an int.
When multiple aliases overlap, the correct string to print can often be
determined purely by considering the InstAlias declarations in some particular
order. This allows the user to specify that order manually when desired,
without resorting to hacking around with the default lexicographical order on
Record instantiation, which is error-prone and ugly.

I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4,
uxtw". That's only true if Rn is the stack pointer.

llvm-svn: 209199
2014-05-20 09:17:16 +00:00
Nick Lewycky ec373545b8 Teach isKnownNonNull that a nonnull return is not null. Add a test for this case as well as the case of a nonnull attribute (already handled but not tested).
llvm-svn: 209193
2014-05-20 05:13:21 +00:00
David Blaikie 8e1d489351 DebugInfo: Emit function definitions within their namespace scope.
This workaround (presumably for ancient GDB) doesn't appear to be
required (GDB 7.5 seems to tolerate function definition DIEs in
namespace scope just fine).

llvm-svn: 209189
2014-05-20 03:23:24 +00:00
David Blaikie e837e96a82 Follow up to 209187, updating a test to use FileCheck. Needed to ignore an extra DW_TAG_class_type
llvm-svn: 209188
2014-05-20 02:40:34 +00:00
David Blaikie 0a8cabb431 Update test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll to use FileCheck.
llvm-svn: 209187
2014-05-20 02:19:15 +00:00
Nick Lewycky d52b1528c0 Add 'nonnull', a new parameter and return attribute which indicates that the pointer is not null. Instcombine will elide comparisons between these and null. Patch by Luqman Aden!
llvm-svn: 209185
2014-05-20 01:23:40 +00:00
Adrian Prantl eb1ddfc8f4 LTO: Add a testcase for linking modules with incompatible Debug Info
Versions.
rdar://problem/16926122

llvm-svn: 209183
2014-05-19 23:41:25 +00:00
Kevin Enderby 1fc760add4 OK, NAKAMURA Takumi beat me to this change. So backing out my addition of
llvm-size to the list so it only has one.  Sorry for the noise.

llvm-svn: 209181
2014-05-19 23:26:51 +00:00
Kevin Enderby 5f4aebc204 David Blaikie pointed out that the test added in r209158 fails in the
check-llvm target under CMake.  And the test/CMakeFiles.txt needs to
have llvm-size added to the list.

llvm-svn: 209179
2014-05-19 23:22:58 +00:00
David Blaikie 424b59b1ce DebugInfo: Assume all subprogram DIEs have been created before any abstract subprograms are constructed.
Since we visit the whole list of subprograms for each CU at module
start, this is clearly true - don't test for the case, just assert it.

A few old test cases seemed to have incomplete subprogram lists, but any
attempt to reproduce them shows full subprogram lists that even include
entities that have been completely inlined and the out of line
definition removed.

llvm-svn: 209178
2014-05-19 23:16:19 +00:00
NAKAMURA Takumi bdc1d45f57 [CMake] Add llvm-size to check-llvm, to fix build since r209158.
llvm-svn: 209177
2014-05-19 23:12:43 +00:00
Chad Rosier b06ed63ebf [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.
Patch by Dave Estes<cestes@codeaurora.org>!
PR19761 http://reviews.llvm.org/D3829

llvm-svn: 209176
2014-05-19 22:59:51 +00:00
David Blaikie 973141a035 DebugInfo: Don't include DW_AT_inline on each abstract definition multiple times.
When I refactored this in r208636 I accidentally caused this to be added
multiple times to each abstract subprogram (not accounting for the
deduplicating effect of the InlinedSubprogramDIEs set).

This got better in r208798 when the abstract definitions got the
attribute added to them at construction time, but still had the
redundant copies introduced in r208636.

This commit removes those excess DW_AT_inlines and relies solely on the
insertion in r208798.

llvm-svn: 209166
2014-05-19 22:07:16 +00:00
David Blaikie 48b056bab0 DebugInfo: Fix missing inlined_subroutines caused by r208748.
The check in DwarfDebug::constructScopeDIE was meant to consider inlined
subroutines as any non-top-level scope that was a subprogram. Instead of
checking "not top level scope" it was checking if the /subprogram's/
scope was non-top-level.

Fix this and beef up a test case to demonstrate some of the missing
inlined_subroutines are no longer missing.

In the course of fixing this I also found that r208748 (with this fix)
found one /extra/ inlined_subroutine in concrete_out_of_line.ll due to
two inlined_subroutines having the same inlinedAt location. The previous
implementation was collapsing these into a single inlined subroutine.

I'm not sure what the original code was that created this .ll file so
I'm not sure if this actually happens in practice today. Since we
deliberately include column information to disambiguate two calls on the
same line, that may've addressed this bug in the frontend, but it's good
to know that workaround isn't necessary for this particular case
anymore.

llvm-svn: 209165
2014-05-19 21:54:31 +00:00
Juergen Ributzka 431761771c [ConstantHoisting][X86] Change the cost model to never hoist constants for types larger than i128.
Currently the X86 backend doesn't support types larger than i128 very well. For
example an i192 multiply will assert in codegen when the 2nd argument is a constant and the constant got hoisted.

This fix changes the cost model to never hoist constants for types larger than
i128. Once the codegen issues have been resolved, the cost model can be updated
to allow also larger types.

This is related to <rdar://problem/16954938>

llvm-svn: 209162
2014-05-19 21:00:53 +00:00
Andrea Di Biagio 7a85cadfd6 [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.
Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always
provide the operand size as output if the input operand is zero.

We can take advantage of this knowledge during instruction selection
stage in order to simplify a few corner case.

llvm-svn: 209159
2014-05-19 20:38:59 +00:00
Kevin Enderby 403258f5a3 Implement MachOObjectFile::isSectionData() and MachOObjectFile::isSectionBSS
so that llvm-size will total up all the sections in the Berkeley format.  This
allows for rough categorizations for Mach-O sections.  And allows the total of
llvm-size’s Berkeley and System V formats to be the same.

llvm-svn: 209158
2014-05-19 20:36:02 +00:00
Filipe Cabecinhas dc92102766 Added more insertps optimizations
Summary:
When inserting an element that's coming from a vector load or a broadcast
of a vector (or scalar) load, combine the load into the insertps
instruction.
Added PerformINSERTPSCombine for the case where we need to fix the load
(load of a vector + insertps with a non-zero CountS).
Added patterns for the broadcasts.

Also added tests for SSE4.1, AVX, and AVX2.

Reviewers: delena, nadav, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3581

llvm-svn: 209156
2014-05-19 19:45:57 +00:00
Lang Hames 9f7d14756d Fix testers by removing dubious testcase for r209154.
It turns out that not all the world is x86-64. Who knew?

I'll get to work on a more appropriate test case for this patch.

llvm-svn: 209155
2014-05-19 19:38:48 +00:00
Lang Hames 1fcbc08500 [RuntimeDyld] Fix x86-64 MachO GOT relocation handling.
For GOT relocations the addend should modify the offset to the
GOT entry, not the value of the entry itself. Teach RuntimeDyldMachO
to do The Right Thing here.

Fixes <rdar://problem/16961886>.
 

llvm-svn: 209154
2014-05-19 19:21:25 +00:00
Alexey Samsonov e321879709 Kill symbolization functionality in llvm-dwarfdump. We have llvm-symbolizer for that.
llvm-svn: 209152
2014-05-19 18:45:32 +00:00
Peter Collingbourne 68a889757d Check the alwaysinline attribute on the call as well as on the caller.
Differential Revision: http://reviews.llvm.org/D3815

llvm-svn: 209150
2014-05-19 18:25:54 +00:00
Jyotsna Verma 9a103563f4 reverting r209132
llvm-svn: 209139
2014-05-19 16:22:11 +00:00
Bradley Smith c3b931d005 [ARM64] Split tbz/tbnz into W/X register variant
llvm-svn: 209134
2014-05-19 15:58:15 +00:00
Jyotsna Verma daeb25d4e0 Hexagon: Add encoding bits to the mpy instructions.
llvm-svn: 209132
2014-05-19 15:32:07 +00:00
Zoran Jovanovic b2b1f98da4 [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests
Differential Revision: http://reviews.llvm.org/D3808

llvm-svn: 209129
2014-05-19 14:57:46 +00:00
Benjamin Kramer 6dd790c617 Flip on vectorization of bswap intrinsics.
The cost model conservatively assumes that it will always get scalarized and
that's about as good as we can get with the generic TTI; reasoning whether a
shuffle with an efficient lowering is available is hard. We can override that
conservative estimate for some targets in the future.

llvm-svn: 209125
2014-05-19 13:48:08 +00:00
Benjamin Kramer f3ad23551d SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not.
- On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though.
- On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal.
- On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled.

llvm-svn: 209123
2014-05-19 13:12:38 +00:00
Dinesh Dwivedi f82f16e3e6 Added inst-combine for 'MIN(MIN(A, 97), 23)' and 'MAX(MAX(A, 23), 97)'
This removes TODO added in r208849 [http://reviews.llvm.org/D3629]

MIN(MIN(A, 97), 23) -> MIN(A, 23)
MAX(MAX(A, 23), 97) -> MAX(A, 97)

Differential Revision: http://reviews.llvm.org/D3785

llvm-svn: 209110
2014-05-19 07:08:32 +00:00
Filipe Cabecinhas cc8c96c133 Change the blend tests to AVX, not AVX2.
llvm-svn: 209107
2014-05-19 04:47:12 +00:00
Saleem Abdulrasool a521845381 ARM: improve WoA ABI conformance for frame register
Windows on ARM uses R11 for the frame pointer even though the environment is a
pure Thumb-2, thumb-only environment.  Replicate this behaviour to improve
Windows ABI compatibility.  This register is used for fast stack walking, and
thus is part of the Windows ABI.

llvm-svn: 209085
2014-05-18 04:12:52 +00:00
Rafael Espindola 77bbb54fbf Handle ConstantAggregateZero when upgrading global_ctors.
llvm-svn: 209075
2014-05-17 21:00:22 +00:00
NAKAMURA Takumi 7ef81a4f98 Revert r209049 and r209065, "Add support for combining GEPs across PHI nodes"
It broke clang selfhosting even after r209065.

llvm-svn: 209067
2014-05-17 14:39:21 +00:00
Saleem Abdulrasool 2476759673 test: fix copy-paste mistake
Accidental over-quoting of the match string.

llvm-svn: 209058
2014-05-17 04:32:38 +00:00
Saleem Abdulrasool 46fed305db ARM: use the proper target object format for WoA
WoA uses COFF, not ELF.  ARMISelLowering::createTLOF would previously return ELF
for any non-MachO platform.  This was a missed site when the original change for
target format support for Windows on ARM was done.

llvm-svn: 209057
2014-05-17 04:28:08 +00:00
Chandler Carruth c85473143c [x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflw
were added in SSE2, no SSSE3. Found this while auditing all uses of
SSSE3 in the X86 target. I don't actually expect this to make
a significant difference on anything and I don't have any detailed test
cases but I updated the existing test cases that already covered some of
this code path.

llvm-svn: 209056
2014-05-17 03:29:20 +00:00
Alexey Samsonov cd01472a9b [DWARF parser] Teach DIContext to fetch short (non-linkage) function names for a given address.
Change --functions option in llvm-symbolizer tool to accept
values "none", "short" or "linkage". Update the tests and docs
accordingly.

llvm-svn: 209050
2014-05-17 00:07:48 +00:00
Louis Gerbarg 8d2a43e9be Add support for combining GEPs across PHI nodes
Currently LLVM will generally merge GEPs. This allows backends to use more
complex addressing modes. In some cases this is not happening because there
is PHI inbetween the two GEPs:

  GEP1--\
        |-->PHI1-->GEP3
  GEP2--/

This patch checks to see if GEP1 and GEP2 are similiar enough that they can be
cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123):

  GEP1--\                     --\                           --\
        |-->PHI1-->GEP3  ==>    |-->PHI2->GEP12->GEP3 == >    |-->PHI2->GEP123
  GEP2--/                     --/                           --/

This also breaks certain use chains that are preventing GEP->GEP merges that the
the existing instcombine would merge otherwise.

Tests included.

rdar://15547484

llvm-svn: 209049
2014-05-16 23:47:24 +00:00
Filipe Cabecinhas 7b12d773e3 Added tests for the cost of lowering VSELECT instructions.
llvm-svn: 209045
2014-05-16 22:47:58 +00:00
Filipe Cabecinhas 89654da069 Implemented special cases for PerformVSELECTCombine.
vselects with constant masks, after legalization, will get turned into
specialized shuffle_vectors so they can be matched to blend+imm
instructions.

Fixed some tests.

llvm-svn: 209044
2014-05-16 22:47:54 +00:00
Filipe Cabecinhas e15551832c Lower vselects into X86ISD::BLENDI when appropriate.
LowerVSELECT will, if possible, generate a X86ISD::BLENDI DAG node if the
condition is constant and we can emit that instruction, given the
subtarget.

This is not enough for all cases. An additional SELECTCombine optimization
will be committed.

Fixed tests that were expecting variable blends but where a blend+imm can
be generated.
Added test where we can't emit blend+immediate.
Added avx2 blend+imm tests.

llvm-svn: 209043
2014-05-16 22:47:49 +00:00
David Blaikie c405c9cb0b DebugInfo: Handle emitting constants of C++ unicode character type.
Patch by Stephan Tolksdorf! (with some test case stuff by me)

Differential Revision: http://reviews.llvm.org/D3810

llvm-svn: 209037
2014-05-16 21:53:09 +00:00
Tom Stellard f719ee9e76 R600/SI: Promote f32 SELECT to i32
llvm-svn: 209024
2014-05-16 20:56:41 +00:00
Reid Kleckner fceb76f5f9 Add comdat key field to llvm.global_ctors and llvm.global_dtors
This allows us to put dynamic initializers for weak data into the same
comdat group as the data being initialized.  This is necessary for MSVC
ABI compatibility.  Once we have comdats for guard variables, we can use
the combination to help GlobalOpt fire more often for weak data with
guarded initialization on other platforms.

Reviewers: nlewycky

Differential Revision: http://reviews.llvm.org/D3499

llvm-svn: 209015
2014-05-16 20:39:27 +00:00
Rafael Espindola 6b238633b7 Fix most of PR10367.
This patch changes the design of GlobalAlias so that it doesn't take a
ConstantExpr anymore. It now points directly to a GlobalObject, but its type is
independent of the aliasee type.

To avoid changing all alias related tests in this patches, I kept the common
syntax

@foo = alias i32* @bar

to mean the same as now. The cases that used to use cast now use the more
general syntax

@foo = alias i16, i32* @bar.

Note that GlobalAlias now behaves a bit more like GlobalVariable. We
know that its type is always a pointer, so we omit the '*'.

For the bitcode, a nice surprise is that we were writing both identical types
already, so the format change is minimal. Auto upgrade is handled by looking
through the casts and no new fields are needed for now. New bitcode will
simply have different types for Alias and Aliasee.

One last interesting point in the patch is that replaceAllUsesWith becomes
smart enough to avoid putting a ConstantExpr in the aliasee. This seems better
than checking and updating every caller.

A followup patch will delete getAliasedGlobal now that it is redundant. Another
patch will add support for an explicit offset.

llvm-svn: 209007
2014-05-16 19:35:39 +00:00