llvm-project

Commit Graph

Author	SHA1	Message	Date
Michael Liao	137f8aedea	Add wider vector/integer support for PR12312 - Enhance the fix to PR12312 to support wider integer, such as 256-bit integer. If more than 1 fully evaluated vectors are found, POR them first followed by the final PTEST. llvm-svn: 163832	2012-09-13 20:24:54 +00:00
NAKAMURA Takumi	cdfe1d1cdb	llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown. llvm-svn: 162736	2012-08-28 04:04:29 +00:00
Michael Liao	b7d85b6328	Fix PR12312 - Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. llvm-svn: 162735	2012-08-28 03:34:40 +00:00

Author

SHA1

Message

Date

Michael Liao

137f8aedea

Add wider vector/integer support for PR12312

- Enhance the fix to PR12312 to support wider integer, such as 256-bit
  integer. If more than 1 fully evaluated vectors are found, POR them
  first followed by the final PTEST.

llvm-svn: 163832

2012-09-13 20:24:54 +00:00

NAKAMURA Takumi

cdfe1d1cdb

llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.

llvm-svn: 162736

2012-08-28 04:04:29 +00:00

Michael Liao

b7d85b6328

Fix PR12312

- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
  Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
  X86ISD::OR node has only its flag result being used as a boolean value and
  all its leaves are extracted from the same vector, it could be folded into an
  X86ISD::PTEST node.

llvm-svn: 162735

2012-08-28 03:34:40 +00:00

3 Commits