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Author SHA1 Message Date
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Jim Grosbach fb08e55cc1 ARM: Split out cost model vcvt testcases. 
They had a separate RUN line already, so may as well be in a separate file.

llvm-svn: 179988
 2013-04-21 23:47:37 +00:00
Jakob Stoklund Olesen 84ebe25db7 Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

llvm-svn: 179987
 2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Tim Northover 4a58db65a5 ARM: fix part of test which actually needed an asserts build 
This should fix a buildbot failure that occurred after r179977.

llvm-svn: 179978
 2013-04-21 12:20:19 +00:00
Tim Northover 798697d662 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977
 2013-04-21 11:57:07 +00:00
Bill Wendling eaff0ce3a4 Remove tbaa metadata. 
llvm-svn: 179970
 2013-04-21 01:38:25 +00:00
Jakob Stoklund Olesen a41f91ea8e Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
 2013-04-20 22:49:16 +00:00
Tim Northover d9d4211fe2 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956
 2013-04-20 19:31:00 +00:00
Stephen Lin 8fccb8a772 Minor renaming of tests (for consistency with an in-development patch) 
llvm-svn: 179954
 2013-04-20 16:21:26 +00:00
Benjamin Kramer 5bd25f3786 Don't litter .s files in test directory. 
llvm-svn: 179937
 2013-04-20 10:43:40 +00:00
Stephen Lin b8bd232a3d Add CodeGen support for functions that always return arguments via a new parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). 
llvm-svn: 179925
 2013-04-20 05:14:40 +00:00
Stephen Lin ffc445492c Allow tail call opportunity detection through nested and/or multiple iterations of extractelement/insertelement indirection 
llvm-svn: 179924
 2013-04-20 04:27:51 +00:00
Akira Hatanaka 1ebb2a1c56 [mips] Instruction selection patterns for DSP-ASE vector shifts. 
llvm-svn: 179906
 2013-04-19 23:21:32 +00:00
Hal Finkel e632239d7b Fix PPC optimizeCompareInstr swapped-sub argument handling 
When matching a compare with a subtract where the arguments of the compare are
swapped w.r.t. the arguments of the subtract, we need to negate the predicates
(or CR bit indices) of the users. This, however, is not the same as inverting
the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM
backend seems to do this correctly, but when I adapted the code for the PPC
backend, I introduced an error in this logic.

Comparison optimization is now enabled again by default.

llvm-svn: 179899
 2013-04-19 22:08:38 +00:00
Anton Korobeynikov 9c0df1695d Do not mangle in MS-way the globals with magic \001 in the name. 
Based on the patch by David Nadlinger!

llvm-svn: 179889
 2013-04-19 21:20:56 +00:00
Bill Wendling b1f0f71735 Make test slightly more readable. 
llvm-svn: 179888
 2013-04-19 21:14:59 +00:00
Bill Wendling ae230c11cc Add a testcase to make sure we generate the proper compact unwind section for a function that cannot produce a compact unwind encoding. 
llvm-svn: 179887
 2013-04-19 21:07:11 +00:00
Eric Christopher 0e89ade8ff Revert "PR14606: debug info imported_module support" 
This reverts commit r179836 as it seems to have caused test failures.

llvm-svn: 179840
 2013-04-19 07:47:16 +00:00
David Blaikie 88564f3cf7 PR14606: debug info imported_module support 
Adding another CU-wide list, in this case of imported_modules (since they
should be relatively rare, it seemed better to add a list where each element
had a "context" value, rather than add a (usually empty) list to every scope).
This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll
need to expand this to cover DW_TAG_imported_declaration too.

llvm-svn: 179836
 2013-04-19 06:57:04 +00:00
Tom Stellard 9d10c4ce86 R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard 5a6b0d828b R600: Reorganize lit tests and document how they should be organized 
llvm-svn: 179828
 2013-04-19 02:10:53 +00:00
Hal Finkel b12da6be75 Disable PPC comparison optimization by default 
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do
I'm disabling this for now.

llvm-svn: 179807
 2013-04-18 22:54:25 +00:00
Hal Finkel 82656cb200 Implement optimizeCompareInstr for PPC 
Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.

This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.

llvm-svn: 179802
 2013-04-18 22:15:08 +00:00
Benjamin Kramer c557828805 X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't available. 
This pattern started popping up in vectorized min/max reductions.

llvm-svn: 179797
 2013-04-18 21:37:45 +00:00
Derek Schuff a403d243d1 Allow misaligned stores in x86 fast-isel. 
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and
handled by the DAG-based ISel.  However, X86FastISel::X86SelectLoad() makes
no such requirement.  There doesn't appear to be an x86 architectural
correctness issue with allowing potentially unaligned store instructions.
This patch removes this restriction.

Patch by Jim Stichnot.

llvm-svn: 179774
 2013-04-18 17:41:08 +00:00
Hao Liu a2ff69863e Fix for PR14824, An ARM Load/Store Optimization bug 
llvm-svn: 179751
 2013-04-18 09:11:08 +00:00
Eli Bendersky 24a36eb331 This patch teaches x86 fast-isel to generate the native div/idiv instructions 
for the sdiv/srem/udiv/urem bitcode instructions.  This is done for the i8,
i16, and i32 types, as well as i64 for the x86_64 target.

Patch by Jim Stichnoth

llvm-svn: 179715
 2013-04-17 20:10:13 +00:00
Vincent Lejeune 2d5c341cee R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Richard Osborne ba79dfc390 [XCore] Extend test to check positve offsets are folded into addresses. 
llvm-svn: 179621
 2013-04-16 20:05:52 +00:00
Richard Osborne f29919d3f8 [XCore] Give test more generic name. 
I intend to extend the test with more offset folding checks

llvm-svn: 179620
 2013-04-16 19:56:55 +00:00
Richard Osborne 9a61da5ed4 [XCore] Convert a couple of tests to FileCheck. 
llvm-svn: 179619
 2013-04-16 19:41:19 +00:00
Logan Chien d8bb4b7e06 Implement ARM unwind opcode assembler. 
llvm-svn: 179591
 2013-04-16 12:02:21 +00:00
Jakob Stoklund Olesen 73d1739bc4 Add 64-bit multiply and divide instructions for SPARC v9. 
llvm-svn: 179582
 2013-04-16 02:57:02 +00:00
Tom Stellard cb97e3acfa R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard 3a7beafb32 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard 9991659fab R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
Tim Northover 943e9293b3 Avoid outputting temporary test file into source tree. 
llvm-svn: 179532
 2013-04-15 15:49:13 +00:00
Hal Finkel 6736988ae2 Fix PPC64 CR spill location for callee-saved registers 
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).

So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.

In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).

llvm-svn: 179500
 2013-04-15 02:07:05 +00:00
Jakob Stoklund Olesen eed1072ff8 Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

llvm-svn: 179477
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen c3c28f8599 Add support for the abs64 SPARC v9 code model. 
For when 16 TB just isn't enough.

llvm-svn: 179474
 2013-04-14 05:10:36 +00:00
Jakob Stoklund Olesen c8fc76b078 Add support for the SPARC v9 abs44 code model. 
This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.

llvm-svn: 179473
 2013-04-14 04:57:51 +00:00
Jakob Stoklund Olesen e0fc832b77 Also put target flags on SPARC constant pool references. 
Constant pool entries are accessed exactly the same way as global
variables.

llvm-svn: 179471
 2013-04-14 04:35:16 +00:00
Jakob Stoklund Olesen dc1ed57858 Fix patterns for 64-bit pointers. 
This fixes the pic32 code model for SPARC v9.

llvm-svn: 179469
 2013-04-14 01:53:23 +00:00
Jakob Stoklund Olesen 15b3e90081 Define SPARC code models. 
Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.

llvm-svn: 179463
 2013-04-13 19:02:23 +00:00
Hal Finkel d85a04b3df Spill and restore PPC CR registers using the FP when we have one 
For functions that need to spill CRs, and have dynamic stack allocations, the
value of the SP during the restore is not what it was during the save, and so
we need to use the FP in these cases (as for all of the other spills and
restores, but the CR restore has a special code path because its reserved slot,
like the link register, is specified directly relative to the adjusted SP).

llvm-svn: 179457
 2013-04-13 08:09:20 +00:00
Andrew Trick 3d957c0ead Further generalize this scheduler test. 
The order of copies depends on queue order, which is not very stable.

llvm-svn: 179456
 2013-04-13 07:37:27 +00:00
Andrew Trick e6f9fc0cdb Fix a dislexic regex. 
llvm-svn: 179455
 2013-04-13 07:29:21 +00:00
Andrew Trick 88a1285b4f Add a missing REQUIRES: asserts 
llvm-svn: 179453
 2013-04-13 06:12:46 +00:00
Andrew Trick e833e1cd6e MI-Sched: schedule physreg copies. 
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

llvm-svn: 179449
 2013-04-13 06:07:40 +00:00