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Author SHA1 Message Date
Craig Topper 7af39d7de0 Convert windows line endings to linux/unix line endings. 
llvm-svn: 179995
 2013-04-22 05:38:01 +00:00
Craig Topper 2172ad64f9 Fix indentation. No functional change. 
llvm-svn: 179994
 2013-04-22 04:24:02 +00:00
Craig Topper f15655b2d9 Put 'else' on same line as preceding curly brace per coding standards. No functional change. 
llvm-svn: 179993
 2013-04-22 04:22:40 +00:00
David Blaikie 8ddc2b50e8 Add a triple to make a test resilient to non-TLS hosts (eg: darwin10) 
Making the test introduced in r179962 resilient to being run on darwin10 hosts.

llvm-svn: 179992
 2013-04-22 04:18:25 +00:00
Craig Topper b5ba3d3b37 Remove an unreachable 'break' following a 'return'. 
llvm-svn: 179991
 2013-04-22 04:06:59 +00:00
Bill Wendling 9a9141aed5 Improve performance of file I/O. 
The fread / fwrite calls were happening for each timer. However, that could be
pretty expensive for a large number of timers. Instead, read and write the
timers in one call.

This gives ~10% speedup in compilation time.

llvm-svn: 179990
 2013-04-22 03:36:22 +00:00
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Jim Grosbach fb08e55cc1 ARM: Split out cost model vcvt testcases. 
They had a separate RUN line already, so may as well be in a separate file.

llvm-svn: 179988
 2013-04-21 23:47:37 +00:00
Jakob Stoklund Olesen 84ebe25db7 Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

llvm-svn: 179987
 2013-04-21 21:36:49 +00:00
Jim Grosbach d4db72db61 Tidy up comment grammar. 
llvm-svn: 179986
 2013-04-21 21:23:01 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Dmitri Gribenko 2dbe8f94a9 Fix return type of isBitfield in the binding definition 
Patch by Loïc Jaquemet.

llvm-svn: 179984
 2013-04-21 18:35:51 +00:00
Stephen Lin cda1028a39 Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned' 
llvm-svn: 179983
 2013-04-21 18:05:20 +00:00
Benjamin Kramer 0212dc27ed SROA: Don't crash on a select with two identical operands. 
This is an edge case that can happen if we modify a chain of multiple selects.
Update all operands in that case and remove the assert. PR15805.

llvm-svn: 179982
 2013-04-21 17:48:39 +00:00
Simon Atanasyan 4938ddb1ab [Mips] Convert a GNU style Mips ABI name to the name accepted by LLVM 
Mips backend.

llvm-svn: 179981
 2013-04-21 13:30:10 +00:00
Arnold Schwaighofer 6eb32b31bd Revert "SimplifyCFG: If convert single conditional stores" 
There is the temptation to make this tranform dependent on target information as
it is not going to be beneficial on all (sub)targets. Therefore, we should
probably do this in MI Early-Ifconversion.

This reverts commit r179957. Original commit message:

"SimplifyCFG: If convert single conditional stores

This transformation will transform a conditional store with a preceeding
uncondtional store to the same location:

a[i] =
may-alias with a[i] load
if (cond)
    a[i] = Y
into an unconditional store.

a[i] = X
may-alias with a[i] load
tmp = cond ? Y : X;
a[i] = tmp

We assume that on average the cost of a mispredicted branch is going to be
higher than the cost of a second store to the same location, and that the
secondary benefits of creating a bigger basic block for other optimizations to
work on outway the potential case were the branch would be correctly predicted
and the cost of the executing the second store would be noticably reflected in
performance.

hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With
this change we are on par with gcc's performance (gcc also performs this
transformation). There was a 1.2 % performance improvement on a ARM swift chip.
Other tests in the test-suite+external seem to be mostly uninfluenced in my
experiments:
This optimization was triggered on 41 tests such that the executable was
different before/after the patch. Only 1 out of the 40 tests (dealII) was
reproducable below 100% (by about .4%). Given that hmmer benefits so much I
believe this to be a fair trade off.

I am going to watch performance numbers across the builtbots and will revert
this if anything unexpected comes up."

llvm-svn: 179980
 2013-04-21 13:09:04 +00:00
Simon Atanasyan 9035898c21 [Mips] Do not add unnecessary Mips toolchain path to the list 
of system include directories with extern "C" semantics.

llvm-svn: 179979
 2013-04-21 12:55:59 +00:00
Tim Northover 4a58db65a5 ARM: fix part of test which actually needed an asserts build 
This should fix a buildbot failure that occurred after r179977.

llvm-svn: 179978
 2013-04-21 12:20:19 +00:00
Tim Northover 798697d662 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977
 2013-04-21 11:57:07 +00:00
Sylvestre Ledru cd4cd6ecc5 Remove the executable bit on cmake files 
llvm-svn: 179976
 2013-04-21 09:04:59 +00:00
Nadav Rotem c57af326a4 SLPVectorize: Add support for vectorization of casts. 
llvm-svn: 179975
 2013-04-21 08:05:59 +00:00
Nadav Rotem 98ad5f0f4c SLPVectorizer: Fix a bug in the code that scans the tree in search of nodes with multiple users. 
We did not terminate the switch case and we executed the search routine twice.

llvm-svn: 179974
 2013-04-21 07:37:56 +00:00
Michael Gottesman d5b701faf1 [objc-arc] Cleaned up tail-call-invariant-enforcement.ll. 
Specifically:

1. Added checks that unwind is being properly added to various instructions.
2. Fixed the declaration/calling of objc_release to have a return type of void.
3. Moved all checks to precede the functions and added checks to ensure that the
checks would only match inside the specific function that we are attempting to
check.

llvm-svn: 179973
 2013-04-21 02:59:44 +00:00
Michael Gottesman 77aa946321 [objc-arc] Check that objc-arc-expand properly handles all strictly forwarding calls and does not touch calls which are not strictly forwarding (i.e. objc_retainBlock). 
llvm-svn: 179972
 2013-04-21 01:57:46 +00:00
Michael Gottesman 524052fec1 [objc-arc] Renamed the test file clang-arc-used-intrinsic-removed-if-isolated.ll -> intrinsic-use-isolated.ll to match the other test file intrinsic-use.ll. 
llvm-svn: 179971
 2013-04-21 01:42:24 +00:00
Bill Wendling eaff0ce3a4 Remove tbaa metadata. 
llvm-svn: 179970
 2013-04-21 01:38:25 +00:00
Richard Smith 034185c2f9 The 'constexpr implies const' rule for non-static member functions is gone in 
C++1y, so stop adding the 'const' there. Provide a compatibility warning for
code relying on this in C++11, with a fix-it hint. Update our lazily-written
tests to add the const, except for those ones which were testing our
implementation of this rule.

llvm-svn: 179969
 2013-04-21 01:08:50 +00:00
Michael Gottesman 3eab2e43d2 When we strength reduce an objc_retainBlock call to objc_retain, increment NumPeeps and make sure that Changed is set to true. 
llvm-svn: 179968
 2013-04-21 00:50:27 +00:00
Michael Gottesman 1e43004295 Fixed comment typo. 
llvm-svn: 179967
 2013-04-21 00:44:46 +00:00
Michael Gottesman df110ac9ec [objc-arc] Fixed typo in debug message. 
llvm-svn: 179966
 2013-04-21 00:30:50 +00:00
Michael Gottesman cdb7c15ce8 [objc-arc] Fixed comment typo. 
llvm-svn: 179965
 2013-04-21 00:25:04 +00:00
Michael Gottesman fb9ece9a7c [objc-arc] Refactored OptimizeReturns so that it uses continue instead of a large multi-level nested if statement. 
llvm-svn: 179964
 2013-04-21 00:25:01 +00:00
Michael Gottesman 01338a442a [objc-arc] Added debug statement saying when we are resetting a sequence's progress. 
This will make it clearer when we are actually resetting a sequence's progress
vs just changing state. This is an important distinction because the former case
clears any pointers that we are tracking while the later does not.

llvm-svn: 179963
 2013-04-20 23:36:57 +00:00
Richard Smith 74d0c1eeef Disable VLA diagnostic in C++1y mode, and add some tests. 
Still to do here:
  - we have a collection of syntactic accepts-invalids to diagnose
  - support non-PODs in VLAs, including dynamic initialization /
    destruction
  - runtime checks (and throw std::bad_array_length) for bad bound
  - support VLA capture by reference in lambdas
  - properly support VLAs in range-based for (don't recompute bound)

llvm-svn: 179962
 2013-04-20 23:28:26 +00:00
Jakob Stoklund Olesen a41f91ea8e Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
 2013-04-20 22:49:16 +00:00
Nadav Rotem 8aca44a623 Fix PR15800. Do not try to vectorize vectors and structs. 
llvm-svn: 179960
 2013-04-20 22:29:43 +00:00
Richard Smith 51fe3a48aa Add another test I forgot to svn add. 
llvm-svn: 179959
 2013-04-20 22:23:29 +00:00
Richard Smith 852c9db72b C++1y: Allow aggregates to have default initializers. 
Add a CXXDefaultInitExpr, analogous to CXXDefaultArgExpr, and use it both in
CXXCtorInitializers and in InitListExprs to represent a default initializer.

There's an additional complication here: because the default initializer can
refer to the initialized object via its 'this' pointer, we need to make sure
that 'this' points to the right thing within the evaluation.

llvm-svn: 179958
 2013-04-20 22:23:05 +00:00
Arnold Schwaighofer 3546ccf465 SimplifyCFG: If convert single conditional stores 
This transformation will transform a conditional store with a preceeding
uncondtional store to the same location:

 a[i] =
 may-alias with a[i] load
 if (cond)
   a[i] = Y

into an unconditional store.

 a[i] = X
 may-alias with a[i] load
 tmp = cond ? Y : X;
 a[i] = tmp

We assume that on average the cost of a mispredicted branch is going to be
higher than the cost of a second store to the same location, and that the
secondary benefits of creating a bigger basic block for other optimizations to
work on outway the potential case were the branch would be correctly predicted
and the cost of the executing the second store would be noticably reflected in
performance.

hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With
this change we are on par with gcc's performance (gcc also performs this
transformation). There was a 1.2 % performance improvement on a ARM swift chip.
Other tests in the test-suite+external seem to be mostly uninfluenced in my
experiments:
This optimization was triggered on 41 tests such that the executable was
different before/after the patch. Only 1 out of the 40 tests (dealII) was
reproducable below 100% (by about .4%). Given that hmmer benefits so much I
believe this to be a fair trade off.

I am going to watch performance numbers across the builtbots and will revert
this if anything unexpected comes up.

llvm-svn: 179957
 2013-04-20 21:42:09 +00:00
Tim Northover d9d4211fe2 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956
 2013-04-20 19:31:00 +00:00
Nuno Lopes 36e827602a recommit tests 
llvm-svn: 179955
 2013-04-20 17:39:52 +00:00
Stephen Lin 8fccb8a772 Minor renaming of tests (for consistency with an in-development patch) 
llvm-svn: 179954
 2013-04-20 16:21:26 +00:00
Richard Smith f30c842a38 Update some stuff on the open projects page to reflect things we've already done. 
llvm-svn: 179953
 2013-04-20 16:20:44 +00:00
Tim Northover 56862bd6b2 AArch64: remove useless comment 
llvm-svn: 179952
 2013-04-20 15:57:41 +00:00
Richard Smith 95997207e0 Switch C++11 open project to C++1y :) 
llvm-svn: 179951
 2013-04-20 15:57:27 +00:00
Richard Smith 4cf9a1ee0b Add note that some of these links are dead for now. 
llvm-svn: 179950
 2013-04-20 13:22:50 +00:00
Richard Smith 33089cbdae VLAs in C++14! 
llvm-svn: 179949
 2013-04-20 13:20:33 +00:00
Stephen Lin 7577ed579c Move 'kw_align' case to proper section, reorganize function attribute keyword case statements to be consistent with r179119 
llvm-svn: 179948
 2013-04-20 13:16:13 +00:00
Richard Smith 7898d7ba96 Variable templates and generic lambdas are approved for C++14. 
llvm-svn: 179947
 2013-04-20 12:58:57 +00:00
Richard Smith d3a7386452 Clarifying memory allocation: approved for C++14. Move from N/A to no, since we currently relax 'operator new' calls which didn't come from new-expressions. 
llvm-svn: 179946
 2013-04-20 12:57:49 +00:00