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136 Commits

Author SHA1 Message Date
Andrew Lenharth 76a61eb054 Be sure to grab weak functions too, and make implicit defs comments 
llvm-svn: 32308
 2006-12-07 17:39:14 +00:00
Chris Lattner b974b0a3e1 silence warnings. 
llvm-svn: 31394
 2006-11-03 01:18:29 +00:00
Andrew Lenharth d8b59f67f6 fix 2006-11-01-vastart.ll 
llvm-svn: 31371
 2006-11-02 03:05:26 +00:00
Andrew Lenharth dfbf91e59d more shotenning 
llvm-svn: 31331
 2006-10-31 23:46:56 +00:00
Andrew Lenharth 8b20fa42da Let us play simplify the td file (and fix a few missed sub and mul patterns). 
llvm-svn: 31322
 2006-10-31 19:52:12 +00:00
Andrew Lenharth 692e4155aa Add all that branch mangling niftiness 
llvm-svn: 31313
 2006-10-31 16:49:55 +00:00
Evan Cheng ab51cf2e78 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Chris Lattner 0e0ee36f45 adjcallstack up/down clobbers the sp 
llvm-svn: 30910
 2006-10-12 18:00:14 +00:00
Chris Lattner 6487854b3f Use cute tblgen tricks to make zap handling more powerful. Specifically, 
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.

This compiles Alpha/zapnot4.ll into:

        sll $16,3,$0
        zapnot $0,3,$0
        ret $31,($26),1

instead of:

        ldah $0,1($31)
        lda $0,-8($0)
        sll $16,3,$1
        and $1,$0,$0
        ret $31,($26),1

It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha.  Make andrew will do this.

llvm-svn: 30875
 2006-10-11 05:13:56 +00:00
Chris Lattner 9f86f7c2ab Remove dead/redundant instructions. These are handled by ZAPNOTi 
llvm-svn: 30872
 2006-10-11 04:12:39 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Andrew Lenharth f007f21c8a catch constants more often 
llvm-svn: 30534
 2006-09-20 15:05:49 +00:00
Andrew Lenharth 3aa3ad780e Jump tables on Alpha 
llvm-svn: 30463
 2006-09-18 18:01:03 +00:00
Evan Cheng 81b645a76b CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Evan Cheng 2af3a67902 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Andrew Lenharth 80528499cf Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth b47461350c ignore ordered/unordered for now 
llvm-svn: 28679
 2006-06-04 00:25:51 +00:00
Andrew Lenharth df7abf8b74 support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 
llvm-svn: 27370
 2006-04-03 04:19:17 +00:00
Andrew Lenharth 4e2c073a33 mul by const conversion sequences. more coming soon 
llvm-svn: 27368
 2006-04-03 03:18:59 +00:00
Andrew Lenharth 70236fc12f fcopysign for mixed mode 
llvm-svn: 26651
 2006-03-09 17:56:33 +00:00
Andrew Lenharth 4a87e7d9a3 alpha and llvm have different oppinions on which arg is the sign bit 
llvm-svn: 26647
 2006-03-09 17:41:50 +00:00
Andrew Lenharth 16b96d2cb4 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth ed7a293b44 fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
llvm-svn: 26641
 2006-03-09 14:58:25 +00:00
Andrew Lenharth 1318240fd0 isStoreToStackSlot 
llvm-svn: 25925
 2006-02-03 03:07:37 +00:00
Andrew Lenharth 4b1c726fbb Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Chris Lattner 1b09c6ba87 cmovle != cmovlt 
llvm-svn: 25761
 2006-01-29 03:47:30 +00:00
Chris Lattner 1240574609 PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Andrew Lenharth 0a01374299 minor renaming 
llvm-svn: 25640
 2006-01-26 03:24:15 +00:00
Andrew Lenharth 153f808f53 allow R28 to be used for frame calculations without entirely removing it from circulation 
llvm-svn: 25639
 2006-01-26 03:22:07 +00:00
Andrew Lenharth fef7dec9cc added stores to lsmark 
llvm-svn: 25552
 2006-01-23 21:51:33 +00:00
Andrew Lenharth 208bbe9ca9 fix up more lsmark stuff 
llvm-svn: 25550
 2006-01-23 21:23:26 +00:00
Andrew Lenharth ba97ea52d4 yea, lowering this stuff will basically work 
llvm-svn: 25549
 2006-01-23 20:59:50 +00:00
Andrew Lenharth 5df67bcd50 typo 
llvm-svn: 25464
 2006-01-19 21:10:38 +00:00
Andrew Lenharth 688ea707d8 nasty nasty patterns 
llvm-svn: 25463
 2006-01-19 20:49:37 +00:00
Andrew Lenharth cfd9c6e526 fix short immediate loads 
llvm-svn: 25371
 2006-01-16 21:41:39 +00:00
Andrew Lenharth 91eda00a7a this pattern was bogus 
llvm-svn: 25197
 2006-01-11 03:33:06 +00:00
Andrew Lenharth 599e73f21c Int immediate loading fix 
llvm-svn: 25182
 2006-01-10 19:12:47 +00:00
Andrew Lenharth 32e7d1ed4a proper branch not equal sequence 
llvm-svn: 25159
 2006-01-09 19:49:58 +00:00
Chris Lattner da56ae98a9 unbreak the build, these are now in TargetSelectionDAG.td 
llvm-svn: 25109
 2006-01-05 04:48:15 +00:00
Andrew Lenharth 6bec63aac9 Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. 
llvm-svn: 25057
 2006-01-01 22:16:14 +00:00
Andrew Lenharth 60ab61fcfc improve constant loading. Still sucks, but oh well 
llvm-svn: 25047
 2005-12-30 02:30:02 +00:00
Andrew Lenharth 50d9caf6a4 let us get some do what I meant not what I said stuff checked in. You would think the alpha backend would be 64bit clean 
llvm-svn: 25040
 2005-12-29 01:06:12 +00:00
Andrew Lenharth 34e4782c95 Fix up immediate handling 
llvm-svn: 25039
 2005-12-29 00:50:08 +00:00
Andrew Lenharth 5bd1c2783b Restore some happiness to the JIT 
llvm-svn: 25026
 2005-12-27 06:25:50 +00:00
Andrew Lenharth 962dcbd572 Fix alpha regressions. 
llvm-svn: 25025
 2005-12-27 03:53:58 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Andrew Lenharth f520093eb3 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 
llvm-svn: 25011
 2005-12-25 17:36:48 +00:00
Andrew Lenharth 0fce613eff All that just to lower div and rem 
llvm-svn: 25008
 2005-12-25 01:34:27 +00:00
Andrew Lenharth 5b18ed9e60 All addressing modes are now exposed. The only remaining relocated forms 
are for function prologue.

TODO: move external symbols over to using RelLit.
    : have a pattern that matches constpool|globaladdr
    : have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0
llvm-svn: 25003
 2005-12-24 08:29:32 +00:00
Andrew Lenharth b9aaea3564 Unify the patterns for loads and stores. Now offset addressing should be 
supported.  This almost completes memory operations.

llvm-svn: 25002
 2005-12-24 07:34:33 +00:00