Commit Graph

468 Commits

Author SHA1 Message Date
Richard Sandiford f2404164ba [SystemZ] Add LOCR and LOCGR
llvm-svn: 187113
2013-07-25 09:11:15 +00:00
Richard Sandiford 09a8cf3604 [SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).

llvm-svn: 187112
2013-07-25 09:04:52 +00:00
Richard Sandiford a68e6f5660 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.

llvm-svn: 187111
2013-07-25 08:57:02 +00:00
Richard Sandiford dd170bd977 [SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.

llvm-svn: 186690
2013-07-19 16:44:32 +00:00
Richard Sandiford fac8b10a84 [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689
2013-07-19 16:37:00 +00:00
Richard Sandiford 7d6a453623 [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687
2013-07-19 16:32:12 +00:00
Richard Sandiford c575df6dcc [SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.

llvm-svn: 186686
2013-07-19 16:26:39 +00:00
Richard Sandiford c57e586792 [SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.

llvm-svn: 186685
2013-07-19 16:24:22 +00:00
Richard Sandiford 0175b4a353 [SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.

llvm-svn: 186683
2013-07-19 16:21:55 +00:00
Richard Sandiford ff6c5a5609 [SystemZ] Use SLLK, SRLK and SRAK for codegen
This patch uses the instructions added in r186680 for codegen.

llvm-svn: 186681
2013-07-19 16:12:08 +00:00
Richard Sandiford 5109321042 [SystemZ] Use RNSBG
This should be the last of the R.SBG patches for now.

llvm-svn: 186573
2013-07-18 10:40:35 +00:00
Richard Sandiford 297f7d2724 [SystemZ] Generalize RxSBG SRA case
The original code only folded SRA into ROTATE ... SELECTED BITS
if there was no outer shift.  This patch splits out that check
and generalises it slightly.  The extra cases aren't really that
interesting, but this is paving the way for RNSBG support.

llvm-svn: 186571
2013-07-18 10:14:55 +00:00
Richard Sandiford 7878b852e6 [SystemZ] Use RXSBG
Extend the previous R.SBG patches to handle XORs.

llvm-svn: 186570
2013-07-18 10:06:15 +00:00
Richard Sandiford 885140c951 [SystemZ] Use ROSBG and non-zero form of RISBG for OR nodes
llvm-svn: 186405
2013-07-16 11:55:57 +00:00
Richard Sandiford 82ec87dbdb [SystemZ] Use RISBG for (shift (and ...))
Another patch in the series to make more use of R.SBG.  This one extends
r186072 and r186073 to handle cases where the AND is inside the shift.

llvm-svn: 186399
2013-07-16 11:02:24 +00:00
Stephen Lin d24ab20e9b Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done

llvm-svn: 186280
2013-07-14 06:24:09 +00:00
Richard Sandiford 17276d3567 [SystemZ] Add test missing from r186148
Sigh, twice in two days sorry.  One day I'll remember...

llvm-svn: 186150
2013-07-12 09:20:14 +00:00
Richard Sandiford 6d4bd28322 [SystemZ] Optimize sign-extends of vector setccs
Normal (sext (setcc ...)) sequences are optimised into
(select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND.
However, this is deliberately not done for vectors, and after
vector type legalization we have (sext_inreg (setcc ...)) instead.

I wondered about trying to extend DAGCombiner to handle this case too,
but it seemed to be a loss on some other targets I tried, even those for
which SETCC isn't "legal" and SELECT_CC is.

llvm-svn: 186149
2013-07-12 09:17:10 +00:00
Richard Sandiford 3f0edc2903 [SystemZ] Improve spilling of LGDR and LDGR
If the source of these instructions is spilled we should load the destination.
If the destination is spilled we should store the source.

llvm-svn: 186147
2013-07-12 08:37:17 +00:00
Richard Sandiford 4209e7f6c6 [SystemZ] Add testcase missing from r186073
llvm-svn: 186074
2013-07-11 09:10:38 +00:00
Richard Sandiford ea9b6aa20b [SystemZ] Use zeroing form of RISBG for shift-and-AND sequences
Extend r186072 to handle shifts and ANDs.

llvm-svn: 186073
2013-07-11 09:10:09 +00:00
Richard Sandiford 84f54a3bc9 [SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.

It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.

llvm-svn: 186072
2013-07-11 08:59:12 +00:00
Richard Sandiford 9784649157 [SystemZ] Use MVC for simple load/store pairs
Look for patterns of the form (store (load ...), ...) in which the two
locations are known not to partially overlap.  (Identical locations are OK.)
These sequences are better implemented by MVC unless either the load or
the store could use RELATIVE LONG instructions.

The testcase showed that we weren't using LHRL and LGHRL for extload16,
only sextloadi16.  The patch fixes that too.

llvm-svn: 185919
2013-07-09 09:46:39 +00:00
Richard Sandiford 47660c148c [SystemZ] Use "STC;MVC" for memset
Use "STC;MVC" for memsets that are too big for two STCs or MV...Is yet
small enough for a single MVC.  As with memcpy, I'm leaving longer cases
till later.

The number of tests might seem excessive, but f33 & f34 from memset-04.ll
failed the first cut because I'd not added the "?:" on the calculation
of Size1.

llvm-svn: 185918
2013-07-09 09:32:42 +00:00
Richard Sandiford d131ff8cf8 [SystemZ] Use MVC for memcpy
Use MVC for memcpy in cases where a single MVC is enough.  Using MVC is
a win for longer copies too, but I'll leave that for later.

llvm-svn: 185802
2013-07-08 09:35:23 +00:00
Richard Sandiford c40f27b52d [SystemZ] Remove no-op MVCs
The stack coloring pass has code to delete stores and loads that become
trivially dead after coloring.  Extend it to cope with single instructions
that copy from one frame index to another.

The testcase happens to show an example of this kicking in at the moment.
It did occur in Real Code too though.

llvm-svn: 185705
2013-07-05 14:38:48 +00:00
Richard Sandiford b5d9bd6f59 Fix double renaming bug in stack coloring pass
The stack coloring pass renumbered frame indexes with a loop of the form:

  for each frame index FI
    for each instruction I that uses FI
      for each use of FI in I
        rename FI to FI'

This caused problems if an instruction used two frame indexes F0 and F1
and if F0 was renamed to F1 and F1 to F2.  The first time we visited the
instruction we changed F0 to F1, then we changed both F1s to F2.

In other words, the problem was that SSRefs recorded which instructions
used an FI, but not which MachineOperands and MachineMemOperands within
that instruction used it.

This is easily fixed for MachineOperands by walking the instructions
once and processing each operand in turn.  There's already a loop to
do that for dead store elimination, so it seemed more efficient to
fuse the two at the block level.

MachineMemOperands are more tricky because they can be shared between
instructions.  The patch handles them by making SSRefs an array of
MachineMemOperands rather than an array of MachineInstrs.  We might end
up processing the same MachineMemOperand twice, but that's OK because
we always know from the SSRefs index what the original frame index was.

llvm-svn: 185703
2013-07-05 14:24:47 +00:00
Richard Sandiford 8976ea72ab [SystemZ] Enable the use of MVC for frame-to-frame spills
...now that the problem that prompted the restriction has been fixed.

The original spill-02.py was a compromise because at the time I couldn't
find an example that actually failed without the two scavenging slots.
The version included here did.

llvm-svn: 185701
2013-07-05 14:02:01 +00:00
Richard Sandiford 23943229f6 [SystemZ] Allocate a second register scavenging slot
This is another prerequisite for frame-to-frame MVC copies.
I'll commit the patch that makes use of the slot separately.

The downside of trying to test many corner cases with each of the
available addressing modes is that a fair few tests need to account
for the new frame layout.  I do still think it's useful to have all
these tests though, since it's something that wouldn't get much coverage
otherwise.

llvm-svn: 185698
2013-07-05 13:11:52 +00:00
Richard Sandiford ed1fab6b5b [SystemZ] Fold more spills
Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>.  Use it to cut down on the number of spill loads.

Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.

This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch.  Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).

llvm-svn: 185529
2013-07-03 10:10:02 +00:00
Richard Sandiford e6e7885591 [SystemZ] Use DSGFR over DSGR in more cases
Fixes some cases where we were using full 64-bit division for (sdiv i32, i32)
and (sdiv i64, i32).

The "32" in "SDIVREM32" just refers to the second operand.  The first operand
of all *DIVREM*s is a GR128.

llvm-svn: 185435
2013-07-02 15:40:22 +00:00
Richard Sandiford f6bae1e434 [SystemZ] Use MVC to spill loads and stores
Try to use MVC when spilling the destination of a simple load or the source
of a simple store.  As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet.  spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.

I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...

Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}.  It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.

llvm-svn: 185434
2013-07-02 15:28:56 +00:00
Richard Sandiford ec8693d5f3 [SystemZ] Fix some embarrassing test typos
llvm-svn: 185070
2013-06-27 09:49:34 +00:00
Richard Sandiford 891a7e7454 [SystemZ] Allow LA and LARL to be rematerialized
llvm-svn: 185069
2013-06-27 09:42:10 +00:00
Richard Sandiford a57e13b670 [SystemZ] Allow immediate moves to be rematerialized
llvm-svn: 185068
2013-06-27 09:38:48 +00:00
Richard Sandiford b86a83488e [SystemZ] Add conditional store patterns
Add pseudo conditional store instructions, so that we use:

    branch foo:
    store
foo:

instead of:

    load
    branch foo:
    move
foo:
    store

z196 has real 32-bit and 64-bit conditional stores, but we don't use
any z196 instructions yet.

llvm-svn: 185065
2013-06-27 09:27:40 +00:00
Richard Sandiford 30efd87f6e [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses
Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times.  This means that they are not suitable
for volatile loads and stores.

This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.

Other instructions continue to allow volatile operands.  I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.

llvm-svn: 183002
2013-05-31 13:25:22 +00:00
Richard Sandiford 46af5a2cdc [SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was
already there, so this is mostly just a switch-on-and-test process.

llvm-svn: 182920
2013-05-30 09:45:42 +00:00
Richard Sandiford ba97c34bb6 [SystemZ] Two tests missing from previous commit
llvm-svn: 182847
2013-05-29 11:59:26 +00:00
Richard Sandiford e1d9f00f09 [SystemZ] Immediate compare-and-branch support
This patch adds support for the CIJ and CGIJ instructions.

llvm-svn: 182846
2013-05-29 11:58:52 +00:00
Richard Sandiford 0fb90ab0cb [SystemZ] Register compare-and-branch support
This patch adds support for the CRJ and CGRJ instructions.  Support for
the immediate forms will be a separate patch.

The architecture has a large number of comparison instructions.  I think
it's generally better to concentrate on using the "best" comparison
instruction first and foremost, then only use something like CRJ if
CR really was the natual choice of comparison instruction.  The patch
therefore opportunistically converts separate CR and BRC instructions
into a single CRJ while emitting instructions in ISelLowering.

llvm-svn: 182764
2013-05-28 10:41:11 +00:00
Richard Sandiford 586f41777e [SystemZ] Tighten branch tests
After r182274, the branches in these tests must always be short.

llvm-svn: 182358
2013-05-21 08:53:17 +00:00
Richard Sandiford 312425f32d [SystemZ] Add long branch pass
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

llvm-svn: 182274
2013-05-20 14:23:08 +00:00
Richard Sandiford ffd144174d [SystemZ] Make use of SUBTRACT HALFWORD
Thanks to Ulrich Weigand for noticing that this instruction was missing.

llvm-svn: 181893
2013-05-15 15:05:29 +00:00
Ulrich Weigand 9e3577ff44 [SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target.

This version of the patch incorporates feedback from a review by
Sean Silva.  Thanks to all reviewers!

Patch by Richard Sandiford.

llvm-svn: 181204
2013-05-06 16:17:29 +00:00
Dan Gohman dfc96aea90 Remove the SystemZ backend.
llvm-svn: 142878
2011-10-24 23:48:32 +00:00
Chris Lattner b90ed2233c manually upgrade a bunch of tests to modern syntax, and remove some that
are either unreduced or only test old syntax.

llvm-svn: 133228
2011-06-17 03:14:27 +00:00
Jakob Stoklund Olesen 5977109f14 Remove custom allocation orders in SystemZ.
Note that this actually changes code generation, and someone who
understands this target better should check the changes.

- R12Q is now allocatable. I think it was omitted from the allocation
  order by mistake since it isn't reserved. It as apparently used as a
  GOT pointer sometimes, and it should probably be reserved if that is
  the case.

- The GR64 registers are allocated in a different order now. The
  register allocator will automatically put the CSRs last. There were
  other changes to the order that may have been significant.

The test fix is because r0 and r1 swapped places in the allocation order.

llvm-svn: 133067
2011-06-15 18:02:56 +00:00
Jakob Stoklund Olesen 903baeac27 Fix SystemZ tests
llvm-svn: 128686
2011-03-31 23:02:12 +00:00
Devang Patel c24048a718 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
llvm-svn: 121059
2010-12-06 22:39:26 +00:00
Duncan Sands 68c30907cc Correct bogus module triple specifications.
llvm-svn: 112469
2010-08-30 10:48:29 +00:00
Bill Wendling 0160e55893 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829
2010-05-14 22:17:42 +00:00
Chris Lattner 3ae2dd2ba5 add newlines at the end of files.
llvm-svn: 100705
2010-04-07 22:53:17 +00:00
Dale Johannesen f118f9788b Split big test into multiple directories to cater to
those who don't build all targets.

llvm-svn: 100688
2010-04-07 20:43:35 +00:00
Evan Cheng 166a4e6caa Teach dag combine to fold the following transformation more aggressively:
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849
2010-01-06 19:38:29 +00:00
Anton Korobeynikov d91a14dba5 Fix invalid chain folding for memory variant of sdiv / udiv
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
Anton Korobeynikov 48e4a6c739 Add missing RUN line
llvm-svn: 79707
2009-08-22 00:28:50 +00:00
Anton Korobeynikov 5f47ecb918 Reduce the test
llvm-svn: 79703
2009-08-22 00:18:11 +00:00
Anton Korobeynikov f31a44ec01 Add fcopysign instructions
llvm-svn: 79664
2009-08-21 20:02:37 +00:00
Anton Korobeynikov a39f96c6ed Handle 'r' inline asm constraint
llvm-svn: 79648
2009-08-21 18:15:41 +00:00
Dan Gohman ef3d457126 Various AsmWriter output cleanups. Use WriteAsOperand instead of
PrintUnmangledNameSafely.

llvm-svn: 78878
2009-08-13 01:36:44 +00:00
Anton Korobeynikov f6e25b3039 Add testcases for reg-mem arithemtics added recently
llvm-svn: 78214
2009-08-05 17:04:32 +00:00
Anton Korobeynikov be47ccffef Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
llvm-svn: 78212
2009-08-05 16:50:53 +00:00
Chris Lattner 8e55200089 convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"
llvm-svn: 76591
2009-07-21 17:36:24 +00:00
Evan Cheng e20cbf3068 Enable cross register class coalescing.
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
Anton Korobeynikov 77a50bd3a8 Make xfail proper
llvm-svn: 76065
2009-07-16 14:53:47 +00:00
Anton Korobeynikov 73fcd3d962 Temporary disable 16 bit bswap
llvm-svn: 76063
2009-07-16 14:35:57 +00:00
Anton Korobeynikov 902facfe96 Add bswap patterns
llvm-svn: 76061
2009-07-16 14:34:52 +00:00
Anton Korobeynikov 3ae30e08ef Fix logic inversion for RI-mode address selection
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
Anton Korobeynikov 6c2c47ecb2 Unbreak the test
llvm-svn: 76051
2009-07-16 14:30:49 +00:00
Anton Korobeynikov 4121039bef Expand 32-bit bitconverts via memory
llvm-svn: 76050
2009-07-16 14:30:29 +00:00
Anton Korobeynikov bc2ead6ea3 Fix incomin arg stack frame offset in case we need to generate stack frame
llvm-svn: 76049
2009-07-16 14:29:57 +00:00
Anton Korobeynikov bd41c83ab0 Revert the commit, it just hides the real bug
llvm-svn: 76045
2009-07-16 14:28:26 +00:00
Anton Korobeynikov 2acdac0f8e Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects
llvm-svn: 76035
2009-07-16 14:24:41 +00:00
Anton Korobeynikov b25949b0f5 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
Anton Korobeynikov 091872cb37 Implement 'large' PIC model
llvm-svn: 76006
2009-07-16 14:16:05 +00:00
Anton Korobeynikov 569a94c4d0 Implement shifts properly (hopefilly - finally!)
llvm-svn: 76005
2009-07-16 14:15:24 +00:00
Anton Korobeynikov fe8df8ff61 Properly handle divides. As a bonus - implement memory versions of them.
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
Anton Korobeynikov 34ad780d0d 32 bit shifts have only 12 bit displacements
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
Anton Korobeynikov 1eb6262b4b Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
Anton Korobeynikov 62f8515b1c Add support for 12 bit displacements
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
Anton Korobeynikov 43d33bd6d2 Emit proper lowering of load from arg stack slot
llvm-svn: 75986
2009-07-16 14:08:42 +00:00
Anton Korobeynikov a8197bb651 Implement dynamic allocas
llvm-svn: 75985
2009-07-16 14:08:15 +00:00
Anton Korobeynikov 7193e2670e Add jump tables
llvm-svn: 75984
2009-07-16 14:07:50 +00:00
Anton Korobeynikov 2ff298fad0 Add rotates
llvm-svn: 75981
2009-07-16 14:06:49 +00:00
Anton Korobeynikov 9362d9aa76 Add patterns for integer negate
llvm-svn: 75980
2009-07-16 14:06:27 +00:00
Anton Korobeynikov f07c7941f0 Provide proper patterns for and with imm instructions. Tune the tests accordingly.
llvm-svn: 75979
2009-07-16 14:06:00 +00:00
Anton Korobeynikov 59049d9176 Add 32 bit and reg-imm and disable invalid patterns for now
llvm-svn: 75978
2009-07-16 14:05:32 +00:00
Anton Korobeynikov 2d218394c6 Add z9 and z10 target processors. Mark z10-only instructions as such.
llvm-svn: 75977
2009-07-16 14:05:00 +00:00
Anton Korobeynikov d568f6dce2 Proper lower 'small' results
llvm-svn: 75962
2009-07-16 13:58:24 +00:00
Anton Korobeynikov f1bf3176c6 Completel forgot about unconditional branches
llvm-svn: 75961
2009-07-16 13:57:52 +00:00
Anton Korobeynikov 15d6e8785b Lower addresses of globals
llvm-svn: 75960
2009-07-16 13:57:27 +00:00
Anton Korobeynikov a442cdfb04 Test (incomplete) for easy muls
llvm-svn: 75959
2009-07-16 13:57:03 +00:00
Anton Korobeynikov f0d7d6ce65 Provide "wide" muls and divs/rems
llvm-svn: 75958
2009-07-16 13:56:42 +00:00
Anton Korobeynikov b04a4fa5c1 Tests for cmp / br_cc / select_cc
llvm-svn: 75949
2009-07-16 13:53:15 +00:00
Anton Korobeynikov 8695a30066 Emit callee-saved regs spills / restores
llvm-svn: 75943
2009-07-16 13:51:12 +00:00
Anton Korobeynikov d694b9ff8b Some preliminary call lowering
llvm-svn: 75941
2009-07-16 13:50:21 +00:00
Anton Korobeynikov 018599fc0b Prologue / epilogue emission
llvm-svn: 75940
2009-07-16 13:49:49 +00:00
Anton Korobeynikov 09890bd434 Add simple frame index elimination
llvm-svn: 75939
2009-07-16 13:49:25 +00:00
Anton Korobeynikov 5dc5629100 Provide proper test :)
llvm-svn: 75938
2009-07-16 13:48:59 +00:00
Anton Korobeynikov 405833dfb6 Add address computation stuff
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
Anton Korobeynikov df99232d27 Add mem-imm stores
llvm-svn: 75933
2009-07-16 13:47:14 +00:00
Anton Korobeynikov 44f8bbfb3f Add stores and truncstores
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
Anton Korobeynikov 11b91b4e2e Add patterns for various extloads
llvm-svn: 75930
2009-07-16 13:44:30 +00:00
Anton Korobeynikov 04be818918 Add shifts and reg-imm address matching
llvm-svn: 75927
2009-07-16 13:43:18 +00:00
Anton Korobeynikov cf7ea6a94f Add bunch of 32-bit patterns... Uffff :)
llvm-svn: 75926
2009-07-16 13:42:31 +00:00
Anton Korobeynikov ebe2de0e14 Add bunch of reg-imm movs
llvm-svn: 75921
2009-07-16 13:34:50 +00:00
Anton Korobeynikov 28234bcde2 Provide masked reg-imm 'or' and 'and'
llvm-svn: 75919
2009-07-16 13:33:57 +00:00
Anton Korobeynikov 1c4c7823ae Fix test running lines
llvm-svn: 75918
2009-07-16 13:33:21 +00:00
Anton Korobeynikov 0d76b17a78 Add reg-reg and pattern
llvm-svn: 75917
2009-07-16 13:32:49 +00:00
Anton Korobeynikov f9fe4036f2 Add sub reg-reg pattern
llvm-svn: 75916
2009-07-16 13:32:16 +00:00
Anton Korobeynikov a083d7af53 Add xor reg-reg pattern
llvm-svn: 75915
2009-07-16 13:31:28 +00:00
Anton Korobeynikov 65096d6a60 Add or reg-reg pattern.
llvm-svn: 75914
2009-07-16 13:30:53 +00:00
Anton Korobeynikov 18172d786f Add add reg-reg and reg-imm patterns
llvm-svn: 75913
2009-07-16 13:30:15 +00:00
Anton Korobeynikov 09082fa01a Add simple reg-reg and reg-imm moves
llvm-svn: 75912
2009-07-16 13:29:38 +00:00
Anton Korobeynikov cf4ba97dba Minimal lowering for formal_arguments / ret
llvm-svn: 75911
2009-07-16 13:28:59 +00:00
Anton Korobeynikov a3ceeaeda5 Add testsuite dir for systemz stuff
llvm-svn: 75910
2009-07-16 13:28:22 +00:00