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Author SHA1 Message Date
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Fraser Cormack 09db958e37 [RISCV] Improve scalable-vector shift tests (NFC) 
All i8/i16 and several i32 tests were testing immediate shift amounts
which exceeded the bits in the vector elements, creating poison values.
Amend the tests to test well-behaved shift amounts.
 2021-01-12 11:40:21 +00:00
Fraser Cormack f7f09e2b1c [RISCV] Fill out basic integer RVV ISel patterns 
This complements the existing RVV ISel patterns for arithmetic, bitwise
and shifts with the remaining operations in those categories: sub, and,
xor, sra.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93852
 2020-12-29 19:32:18 +00:00