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Author SHA1 Message Date
Craig Topper fdf10e6197 [RISCV] Use X0 as destination of inserted vsetvli when possible. 
We aren't going to connect the result to anything so we might
as well avoid allocating a register.

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D102031
 2021-05-26 13:08:51 -07:00
Jessica Clarke d63d662d3c [RISCV] Remove --riscv-no-aliases from RVV tests 
This serves no useful purpose other than to clutter things up. Diff
summary as the real diff is extremely unwieldy:

   24844 -; CHECK-NEXT:    jalr zero, 0(ra)
   24844 +; CHECK-NEXT:    ret
       8 -; CHECK-NEXT:    vl4re8.v v28, (a0)
       8 +; CHECK-NEXT:    vl4r.v v28, (a0)
      64 -; CHECK-NEXT:    vl8re8.v v24, (a0)
      64 +; CHECK-NEXT:    vl8r.v v24, (a0)
     392 -; RUN:   --riscv-no-aliases < %s | FileCheck %s
     392 +; RUN:   < %s | FileCheck %s
       1 -; RUN:   -verify-machineinstrs --riscv-no-aliases < %s \
       1 +; RUN:   -verify-machineinstrs < %s \

As discussed in D103004.
 2021-05-26 17:59:38 +01:00
Hsiangkai Wang c7189ba785 [RISCV] Add new vector instructions in v0.10. 
* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781
 2021-02-03 13:28:58 +08:00