4 Commits

Author	SHA1	Message	Date
Craig Topper	fdf10e6197	[RISCV] Use X0 as destination of inserted vsetvli when possible. ... We aren't going to connect the result to anything so we might as well avoid allocating a register. Reviewed By: frasercrmck, HsiangKai Differential Revision: https://reviews.llvm.org/D102031	2021-05-26 13:08:51 -07:00
Jessica Clarke	d63d662d3c	[RISCV] Remove --riscv-no-aliases from RVV tests ... This serves no useful purpose other than to clutter things up. Diff summary as the real diff is extremely unwieldy: 24844 -; CHECK-NEXT: jalr zero, 0(ra) 24844 +; CHECK-NEXT: ret 8 -; CHECK-NEXT: vl4re8.v v28, (a0) 8 +; CHECK-NEXT: vl4r.v v28, (a0) 64 -; CHECK-NEXT: vl8re8.v v24, (a0) 64 +; CHECK-NEXT: vl8r.v v24, (a0) 392 -; RUN: --riscv-no-aliases < %s | FileCheck %s 392 +; RUN: < %s | FileCheck %s 1 -; RUN: -verify-machineinstrs --riscv-no-aliases < %s \ 1 +; RUN: -verify-machineinstrs < %s \ As discussed in D103004.	2021-05-26 17:59:38 +01:00
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. ... The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Zakk Chen	351c216f36	[RISCV] Define vector mask-register logical intrinsics. ... Define vector mask-register logical intrinsics and lower them to V instructions. Also define pseudo instructions vmmv.m and vmnot.m. We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D93705	2020-12-24 18:59:05 -08:00