c7522f31f1
[Hexagon] Replacing old version of convert and load f64.
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llvm-svn: 226057
2015-01-14 23:07:36 +00:00
11a34b385d
[Hexagon] Removing old, unused !tstbit instructions.
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llvm-svn: 226036
2015-01-14 20:26:15 +00:00
c91fabc233
[Hexagon] Removing old versions of cmph and updating references.
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llvm-svn: 226013
2015-01-14 18:26:14 +00:00
ffacc6eac6
[Hexagon] Removing old versions of cmpb and updating references.
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llvm-svn: 226006
2015-01-14 18:05:44 +00:00
fa947906bf
[Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references.
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llvm-svn: 226003
2015-01-14 16:49:12 +00:00
d9903888d9
[cleanup] Re-sort all the #include lines in LLVM using
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utils/sort_includes.py.
I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.
llvm-svn: 225974
2015-01-14 11:23:27 +00:00
2b6917b020
[SelectionDAG] Allow targets to specify legality of extloads' result
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type (in addition to the memory type).
The *LoadExt* legalization handling used to only have one type, the
memory type. This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.
However, this isn't always the case. For instance, on X86, with AVX,
this is legal:
v4i32 load, zext from v4i8
but this isn't:
v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.
Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.
Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.
Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior. The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)
No functional change intended.
Differential Revision: http://reviews.llvm.org/D6532
llvm-svn: 225421
2015-01-08 00:51:32 +00:00
92b49c3e39
[Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.
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llvm-svn: 225377
2015-01-07 20:43:38 +00:00
627df427eb
[Hexagon] Adding floating point classification and creation.
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llvm-svn: 225374
2015-01-07 20:28:57 +00:00
290ece7d4c
[Hexagon] Adding encodings for v5 floating point instructions.
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llvm-svn: 225372
2015-01-07 20:24:09 +00:00
777abcb1d7
[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
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llvm-svn: 225371
2015-01-07 20:07:28 +00:00
507dd32703
[Hexagon] Adding compound jump encodings.
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llvm-svn: 225291
2015-01-06 20:03:31 +00:00
68b2e050f0
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
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llvm-svn: 225283
2015-01-06 19:03:20 +00:00
d9c605ddae
[Hexagon] Adding encoding information for absolute address loads.
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llvm-svn: 225279
2015-01-06 18:38:26 +00:00
243a5481d9
[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
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llvm-svn: 225270
2015-01-06 16:52:38 +00:00
1445553474
[Hexagon] Adding dealloc_return encoding and absolute address stores.
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llvm-svn: 225267
2015-01-06 16:15:15 +00:00
dacf057bdc
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
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llvm-svn: 225210
2015-01-05 21:36:38 +00:00
28bb02a8c7
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
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llvm-svn: 225201
2015-01-05 20:56:41 +00:00
abdf2b37d8
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
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llvm-svn: 225199
2015-01-05 20:35:54 +00:00
3acfddd6b5
[Hexagon] Adding V4 logic-logic instructions and tests.
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llvm-svn: 225198
2015-01-05 20:14:58 +00:00
ff10c8c95c
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
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llvm-svn: 225197
2015-01-05 20:04:40 +00:00
5e079577e1
[Hexagon] Adding round reg/imm and bitsplit instructions.
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llvm-svn: 225188
2015-01-05 18:08:21 +00:00
d3c02f177a
Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
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llvm-svn: 225160
2015-01-05 10:15:49 +00:00
5691eb5ee7
Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon
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llvm-svn: 225047
2014-12-31 17:14:35 +00:00
79e8ebada2
[Hexagon] Removing assertion to appease buildbot until I can reproduce the problem
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llvm-svn: 225045
2014-12-31 16:20:00 +00:00
94272611ac
[Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds.
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llvm-svn: 225043
2014-12-31 15:57:38 +00:00
bc405294f0
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
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llvm-svn: 225024
2014-12-31 00:08:34 +00:00
8971e055ae
[Hexagon] Adding double-logic on predicate instructions.
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llvm-svn: 225018
2014-12-30 23:22:39 +00:00
65f3e12ed1
[Hexagon] Adding newvalue compare and jumps.
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llvm-svn: 225015
2014-12-30 23:04:21 +00:00
0cba5f1b43
[Hexagon] Adding postincrement register newvalue stores.
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llvm-svn: 225010
2014-12-30 22:34:08 +00:00
9014890819
[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
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llvm-svn: 225009
2014-12-30 22:28:31 +00:00
820d5cb608
[Hexagon] Adding indexed store new-value variants.
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llvm-svn: 225007
2014-12-30 22:00:26 +00:00
2bad4a7177
[Hexagon] Adding indexed store of immediates.
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llvm-svn: 225006
2014-12-30 21:01:38 +00:00
94a498bf0e
[Hexagon] Adding indexed stores.
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llvm-svn: 225005
2014-12-30 20:42:23 +00:00
9161d47476
[Hexagon] Adding reg-reg indexed load forms.
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llvm-svn: 224997
2014-12-30 18:58:47 +00:00
82fb8cba16
[Hexagon] Dropping old combine instructions without encodings.
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llvm-svn: 224992
2014-12-30 17:53:54 +00:00
377ac65340
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
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llvm-svn: 224991
2014-12-30 17:39:24 +00:00
d7a56fd9ff
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
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llvm-svn: 224989
2014-12-30 15:44:17 +00:00
651b72095b
[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
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llvm-svn: 224957
2014-12-29 21:33:45 +00:00
488b6f7bbc
[Hexagon] Fixing 224952 where an addressing mode update was missed.
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llvm-svn: 224955
2014-12-29 21:18:02 +00:00
bda31b42a0
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
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llvm-svn: 224952
2014-12-29 20:44:51 +00:00
9a3cd3f58c
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
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llvm-svn: 224951
2014-12-29 20:00:43 +00:00
3d34afb32d
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
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llvm-svn: 224949
2014-12-29 19:42:14 +00:00
8233fb002d
[Hexagon] Adding auto-incrementing loads with and without byte reversal.
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llvm-svn: 224871
2014-12-26 21:09:25 +00:00
0a721cd4e1
[Hexagon] Adding locked loads.
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llvm-svn: 224870
2014-12-26 20:42:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
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llvm-svn: 224869
2014-12-26 20:30:58 +00:00
c83cbbf6a1
[Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
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llvm-svn: 224868
2014-12-26 19:31:46 +00:00
fe9612e09d
[Hexagon] Adding post-increment unsigned byte loads.
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llvm-svn: 224867
2014-12-26 19:12:11 +00:00
96976a10a3
[Hexagon] Adding post-increment signed byte loads with tests.
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llvm-svn: 224866
2014-12-26 18:57:13 +00:00
e193e1c48b
[Hexagon] Removing old classes.
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llvm-svn: 224795
2014-12-24 00:43:00 +00:00
Colin LeMahieu