592638ae05
Allow symbols to start from the digit if target requests it. This allows, e.g. pinning
...
variables to specified absolute address. Make use of this feature for MSP430.
This unbreaks PR4776.
llvm-svn: 82227
2009-09-18 16:57:42 +00:00
7fc4ad6a63
make this testcase check darwin32 also
...
llvm-svn: 82182
2009-09-17 23:56:41 +00:00
2ba262b7e8
rename test
...
llvm-svn: 82181
2009-09-17 23:55:12 +00:00
bf2fd768f9
convert to filecheck
...
llvm-svn: 82179
2009-09-17 23:54:26 +00:00
4a1c8fc061
rename file
...
llvm-svn: 82178
2009-09-17 23:42:06 +00:00
94cb6144d2
Remove test cases using -regalloc=simple.
...
llvm-svn: 82130
2009-09-17 06:37:07 +00:00
f56b0482c4
Fix PR4910: Broken logic in coalescer means when a physical register liveness is being shortened, the sub-registers were not. The symptom is the register allocator could not find a free register for this particular test.
...
llvm-svn: 82108
2009-09-17 00:57:15 +00:00
0bf35c25fe
Convert more tests to FileCheck.
...
llvm-svn: 81915
2009-09-15 20:58:02 +00:00
db4916a123
fix PR4984 by ensuring that fastisel adds properly sign extended GEP displacement
...
values to machineinstrs.
llvm-svn: 81886
2009-09-15 18:27:02 +00:00
c25359e1a3
rename test
...
llvm-svn: 81884
2009-09-15 18:23:37 +00:00
2503b50e4d
convert to filecheck
...
llvm-svn: 81882
2009-09-15 18:23:23 +00:00
f3369c22a7
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
...
llvm-svn: 81878
2009-09-15 17:53:11 +00:00
840c700654
several major improvements to the sparc backend: support for weak linkage
...
and PIC codegen. Patch by Venkatraman Govindaraju!
llvm-svn: 81877
2009-09-15 17:46:24 +00:00
d29cafc083
Restore a comment that was lost in the merge.
...
llvm-svn: 81857
2009-09-15 15:09:54 +00:00
30fceaba05
this is failing on linux hosts, force a triple.
...
llvm-svn: 81833
2009-09-15 04:27:29 +00:00
170c116aa7
merge one more in.
...
llvm-svn: 81824
2009-09-15 02:27:23 +00:00
42aaa6e443
merge some more cmov tests into cmov.ll
...
llvm-svn: 81823
2009-09-15 02:25:21 +00:00
baf78e5b52
merge two cmov tests into one.
...
llvm-svn: 81822
2009-09-15 02:22:47 +00:00
520a6856ba
Don't pull a load through a callseq_start if the load's chain
...
has multiple uses, as one of the other uses may be on a path
to a different node above the callseq_start, because that
leads to a cyclic graph. This problem is exposed when
-combiner-global-alias-analysis is used. This fixes PR4880.
llvm-svn: 81821
2009-09-15 01:22:01 +00:00
65829a4ccb
On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of
...
its result if the condition is false.
llvm-svn: 81814
2009-09-15 00:14:11 +00:00
033d31165d
merge the linux cpool/jtbl pic tests into pic.ll and convert to filecheck.
...
Change the picbase symbol on non-darwin systems from ".Lllvm$4.$piclabel" to
".L4$pb". The actual name doesn't matter and the darwin name is shorter.
llvm-svn: 81688
2009-09-13 18:46:37 +00:00
6c89da7027
Define proper subreg sets for arm - this should fix bunch of subtle problems
...
with subreg - superreg mapping and also fix PR4965.
llvm-svn: 81657
2009-09-13 00:59:43 +00:00
f437e68058
Add -mattr=+sse2 to the -march=x86 version of this test. Without
...
sse, this code falls back to SelectionDAG isel which uses an x87
instruction, which is fine, but not what this test is testing for.
llvm-svn: 81656
2009-09-12 23:45:47 +00:00
b165c11021
Remove an unnecessary -f.
...
llvm-svn: 81546
2009-09-11 18:41:06 +00:00
a080159a7c
Convert more tests to avoid llvm-as.
...
llvm-svn: 81545
2009-09-11 18:36:27 +00:00
1880092722
Change tests from "opt %s" to "opt < %s" so that opt doesn't see the
...
input filename so that opt doesn't print the input filename in the
output so that grep lines in the tests don't unintentionally match
strings in the input filename.
llvm-svn: 81537
2009-09-11 18:01:28 +00:00
992e42b606
turn on -experimental-asm-printer for x86 / AT&T by default.
...
llvm-svn: 81532
2009-09-11 17:07:27 +00:00
74a3231de4
Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.
...
llvm-svn: 81496
2009-09-11 01:01:31 +00:00
3cad6283b8
It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
...
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.
rdar://7170444
llvm-svn: 81494
2009-09-11 00:39:26 +00:00
89b090e51e
Reapply r81171 with a fix: don't try to use i64 when it
...
isn't legal.
llvm-svn: 81492
2009-09-11 00:34:46 +00:00
39f51320ca
Don't swap the operands of a subtraction when trying to create a
...
post-decrement load/store.
llvm-svn: 81464
2009-09-10 22:09:31 +00:00
59e4c84c6f
Revert r81171 which was causing pr4927.
...
llvm-svn: 81415
2009-09-10 00:49:22 +00:00
a2e8333eed
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
...
See the bug report for details.
llvm-svn: 81397
2009-09-09 23:14:54 +00:00
16ad903fcf
When widening a vector load, use the correct chain. This fixes PR4891.
...
llvm-svn: 81343
2009-09-09 14:22:57 +00:00
a40184aa77
Add testcase for r81322 (PR4933).
...
llvm-svn: 81327
2009-09-09 09:34:43 +00:00
d5f2b3f543
add a testacse for the objc problem that required required r81305
...
to be temporarily disabled.
llvm-svn: 81320
2009-09-09 06:19:34 +00:00
afa12db8a6
disable the new asmprinter by default. Both the Mangler and MCSymbol
...
printing stuff are quoting symbols now, breaking objc testcases.
llvm-svn: 81319
2009-09-09 06:11:14 +00:00
cf61d68eaf
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
...
llvm-svn: 81318
2009-09-09 06:05:16 +00:00
ba0d9f538f
turn the mcinst asmprinter on by default for x86, tweaking two tests to
...
expect the slight syntax differences in the generated code.
llvm-svn: 81305
2009-09-09 00:41:36 +00:00
5fdb699f13
this got merged into lea.ll
...
llvm-svn: 81298
2009-09-09 00:22:31 +00:00
68d3d61ec1
filecheckize
...
llvm-svn: 81297
2009-09-09 00:19:46 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
...
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
40503396da
Eliminate more uses of llvm-as and llvm-dis.
...
llvm-svn: 81290
2009-09-08 23:54:48 +00:00
f87421f088
update various tests for signedness changes in .s file.
...
llvm-svn: 81289
2009-09-08 23:51:06 +00:00
9ef94277f1
adjust for signedness change. I'd appreciate it if an ARM flavored person
...
could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)
llvm-svn: 81288
2009-09-08 23:44:53 +00:00
6837964819
merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes.
...
llvm-svn: 81285
2009-09-08 23:41:06 +00:00
9e5674ae3f
tweak this to pass on linux.
...
llvm-svn: 81273
2009-09-08 23:32:40 +00:00
dae3e56cb7
convert to filecheck syntax
...
llvm-svn: 81267
2009-09-08 23:16:26 +00:00
e819cfbc71
change selectiondag to add the sign extended versions of immediate operands
...
to instructions instead of zero extended ones. This makes the asmprinter
print signed values more consistently. This apparently only really affects
the X86 backend.
llvm-svn: 81265
2009-09-08 23:05:44 +00:00
7697d37777
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
...
llvm-svn: 81262
2009-09-08 22:51:43 +00:00
7896c8ba58
filecheckize some tests
...
llvm-svn: 81259
2009-09-08 22:38:46 +00:00
72a13d2476
Use opt -S instead of piping bitcode output through llvm-dis.
...
llvm-svn: 81257
2009-09-08 22:34:10 +00:00
9737a63ed8
Change these tests to feed the assembly files to opt directly, instead
...
of using llvm-as, now that opt supports this.
llvm-svn: 81226
2009-09-08 16:50:01 +00:00
59e2b8e894
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
...
makes the code faster.
llvm-svn: 81220
2009-09-08 15:22:32 +00:00
758f8c690d
Unbreak
...
llvm-svn: 81205
2009-09-08 07:30:03 +00:00
a7afdda65d
When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.
...
llvm-svn: 81204
2009-09-08 06:39:07 +00:00
a8cb3dffe9
disable some irrelevant eh emission
...
llvm-svn: 81200
2009-09-08 06:26:40 +00:00
b2fcd070e2
fix PR4767, a crash because fp stackifier visited blocks in
...
depth first order, so it wouldn't process unreachable blocks.
When compiling at -O0, late dead block elimination isn't done
and the bad instructions got to isel.
llvm-svn: 81187
2009-09-08 04:55:44 +00:00
f4a0f0f033
Fix an abort on a store of an empty struct member. getValue returns
...
null in the case of an empty struct, so don't try to call getNumValues
on it.
llvm-svn: 81180
2009-09-08 01:44:02 +00:00
2512a42548
Fix a thinko: When lowering fneg with xor, bitcast the operands
...
from floating-point to integer first, and bitcast the result
back to floating-point. Previously, this test was passing by
falling back to SelectionDAG lowering. The resulting code isn't
as nice, but it's correct and CodeGen now stays on the fast path.
llvm-svn: 81171
2009-09-07 23:47:14 +00:00
b9a562b7c4
Don't depend on arch specific global prefix.
...
llvm-svn: 81084
2009-09-05 11:53:06 +00:00
b9ea94c990
Eliminate uses of %prcontext.
...
- I'd appreciate it if someone else eyeballs my changes to make sure I captured
the intent of the test.
llvm-svn: 81083
2009-09-05 11:35:16 +00:00
7f20002993
Stabilize the order of live intervals in the priority_queue used by the
...
linear scan reg alloc. This fixes a problem I ran into where extracting
a function from a larger file caused the generated code to change (masking
the problem I was trying to debug) because the allocator behaved differently.
This changes the results for two X86 regression checks. stack-color-with-reg
is improved, with one less instruction, but pr3495 is worse, with one more
copy. As far as I can tell, these tests were just getting lucky or unlucky,
so I've changed the expected results.
llvm-svn: 81060
2009-09-05 01:19:16 +00:00
3d2fce01aa
Run branch folding if if-converter make some transformations.
...
llvm-svn: 80994
2009-09-04 07:47:40 +00:00
30e30587eb
Remove stale greps.
...
llvm-svn: 80986
2009-09-04 05:07:52 +00:00
36d8c75eca
Convert tests to FileCheck.
...
llvm-svn: 80983
2009-09-04 04:07:19 +00:00
e072f8eedb
Convert a test to FileCheck.
...
llvm-svn: 80975
2009-09-04 00:32:31 +00:00
aa92dc1e61
LLVM currently represents floating-point negation as -0.0 - x. Fix
...
FastISel to recognize this pattern and emit a floating-point
negation using xor.
llvm-svn: 80963
2009-09-03 22:53:57 +00:00
abf2bb683a
Remove dead greps.
...
llvm-svn: 80946
2009-09-03 20:59:02 +00:00
d0d5e685da
Recognize more opportunities to use SSE min and max instructions,
...
swapping the operands if necessary.
llvm-svn: 80940
2009-09-03 20:34:31 +00:00
eadd21ea3c
Test cases for vector shifts changes r80935
...
Changed the old vector shift test to use FileCheck
llvm-svn: 80936
2009-09-03 19:57:35 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
...
llvm-svn: 80904
2009-09-03 07:04:02 +00:00
cdb6fd2c7c
merge all the basic linux/32 pic tests together into one test.
...
llvm-svn: 80902
2009-09-03 06:29:23 +00:00
4f101f98d1
rename test
...
llvm-svn: 80901
2009-09-03 06:16:49 +00:00
f0da41c3e4
More missed vdup patterns
...
llvm-svn: 80838
2009-09-02 21:21:28 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
...
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
39dc89b458
Fix incorrect declarations of intrinsics in this test.
...
llvm-svn: 80705
2009-09-01 18:50:43 +00:00
ff69320427
Add test for vld{234}_lane instructions.
...
llvm-svn: 80658
2009-09-01 04:27:10 +00:00
33b408a10f
Fix pr4843: When an instruction has multiple destination registers that are
...
tied to different source registers, the TwoAddressInstructionPass needs to
be smarter. Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.
llvm-svn: 80654
2009-09-01 04:18:40 +00:00
f09e8d5497
SJLJ is arm/darwin only for now. force the triple for the test
...
llvm-svn: 80651
2009-09-01 02:34:49 +00:00
20eac92d88
Clean up LSDA name generation and use for SJLJ exception handling. This
...
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
llvm-svn: 80649
2009-09-01 01:57:56 +00:00
c8985204d9
Don't mark a register live at an undef use.
...
llvm-svn: 80621
2009-08-31 20:47:02 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
...
llvm-svn: 80615
2009-08-31 20:14:07 +00:00
b284f7b1d9
eliminate some uses of prcontext. Any help here would be appreciated :)
...
llvm-svn: 80520
2009-08-30 21:45:23 +00:00
3681144bd8
Add missed pattern
...
llvm-svn: 80502
2009-08-30 19:06:39 +00:00
eab572a8ff
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
...
Remove the assertion and generalize the code for ARM NEON stuff.
llvm-svn: 80498
2009-08-30 17:14:54 +00:00
ca73326f56
CMOV_GR8 clobbers EFLAGS when its expansion involves an xor to set
...
a register to 0. This fixes PR4814.
llvm-svn: 80445
2009-08-29 22:19:15 +00:00
ece642a54c
Do not assert on too wide splats we don't support.
...
llvm-svn: 80409
2009-08-29 00:08:18 +00:00
cd41d07f29
Add missed extract_element pattern
...
llvm-svn: 80408
2009-08-28 23:41:26 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
...
llvm-svn: 80404
2009-08-28 23:18:09 +00:00
6da267de23
v4, v5 does not support sxtb / sxth.
...
llvm-svn: 80322
2009-08-28 00:31:43 +00:00
205cac837f
scalar_to_vector is fully legal now (implemented as subreg accesses)
...
llvm-svn: 80249
2009-08-27 16:04:47 +00:00
d0b0262edf
Ok, sometimes it's profitable to turn scalar_to_vector stuff into subreg access.
...
Add a testcase.
llvm-svn: 80246
2009-08-27 14:51:42 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
...
llvm-svn: 80191
2009-08-27 01:23:50 +00:00
7f0ca9a34c
X86FastISel support for loading and storing values of type i1.
...
llvm-svn: 80186
2009-08-27 00:31:47 +00:00
f1abb5511b
Expand i8 selects into control flow instead of 16-bit conditional
...
moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.
subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.
llvm-svn: 80184
2009-08-27 00:14:12 +00:00
faebdee4dd
Convert some more Neon tests to FileCheck.
...
llvm-svn: 80120
2009-08-26 18:11:50 +00:00
f582ac7c11
Alter 79292 to produce output that actually assembles.
...
llvm-svn: 80119
2009-08-26 18:10:32 +00:00
0f756b27ae
Expand scalar_to_vector - we don't have any isel logic for it now
...
llvm-svn: 80107
2009-08-26 16:26:09 +00:00
6c23fa2442
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it
...
leads to partial-register definitions. To help avoid redundant
zero-extensions, also teach the h-register matching patterns that
use movzbl to match anyext as well as zext.
llvm-svn: 80099
2009-08-26 14:59:13 +00:00
a0e01bec87
Add dummy inline asm handling for 'r' constraint. This fixes PR4778
...
llvm-svn: 80085
2009-08-26 13:44:29 +00:00
c5dd8bd8d2
Updated i128 sext support for CellSPU backend, contributed by Ken Werner (IBM)
...
llvm-svn: 80042
2009-08-25 22:37:34 +00:00
3e6c7946df
remove some dead lines.
...
llvm-svn: 80031
2009-08-25 21:01:56 +00:00
88093c7594
convert to filecheck style
...
llvm-svn: 80029
2009-08-25 20:57:38 +00:00
6d9d5a9c94
convert to filecheck
...
llvm-svn: 80025
2009-08-25 20:49:04 +00:00
9cc4970ed3
Switch abi-isel.ll to FileCheck; it's not much faster, but it now tests a lot
...
more and is much nicer to the OS.
- Dan, please check. If there are parts of the test you think I should strip
out so it doesn't cause random failures let me know (there are still some PIC
label numbers in it, for example).
llvm-svn: 80019
2009-08-25 18:45:03 +00:00
ae6bc8214a
Fixup register kills after scheduling.
...
llvm-svn: 80002
2009-08-25 17:03:05 +00:00
271cdda8e1
Provide dynamic_stackalloc lowering for MSP430.
...
This fixes PR4769
llvm-svn: 80001
2009-08-25 17:00:23 +00:00
0d4bbf2c4a
Remove obsolete -f flags.
...
llvm-svn: 79992
2009-08-25 15:38:29 +00:00
f8d37c6b81
Fix PR 4751, another difficulty with %a modifier on x86.
...
llvm-svn: 79961
2009-08-25 00:16:14 +00:00
ec89f0c41a
- Remove SelectSEXTi128 from SPUISelDAGToDAG.cpp, evidently, this is redundant
...
code, according to Anton (I'm not totally convinced, but we can always
resurrect patches if we need to do so.)
- Start moving CellSPU's tests to prefer FileCheck.
llvm-svn: 79958
2009-08-24 23:57:35 +00:00
e208c9458d
Prefer 'FileCheck' over 'grep'.
...
llvm-svn: 79953
2009-08-24 22:49:22 +00:00
8d1602af86
128-bit sign extension and vector shift cleanups, contributed by Ken Werner
...
(IBM).
llvm-svn: 79949
2009-08-24 22:28:53 +00:00
9054d25808
Fix a typo. Somehow I thought this had passed before, but I guess not.
...
llvm-svn: 79937
2009-08-24 21:17:17 +00:00
5fe1d38607
Convert slow test to use FileCheck.
...
llvm-svn: 79935
2009-08-24 20:33:47 +00:00
6969df0fab
Convert two gratuitous abuses of poor helpless CPU cycles to FileCheck.
...
llvm-svn: 79933
2009-08-24 20:08:27 +00:00
fbc9a2e33b
Split test into 3.
...
llvm-svn: 79926
2009-08-24 17:51:19 +00:00
6bbeda41b9
Make linkerprivate work for ARM and PPC. Testcase covers
...
all Darwin targets; could be split into separate tests for
the chip subdirectories, but from Chris' last mail on testing
I assume he'd rather have only one test. Generic seems to be
the best available, maybe there should be a Darwin subdirectory?
llvm-svn: 79877
2009-08-24 01:03:42 +00:00
a9e1d3f065
Rerevert (r75663 and r76805), seems there is more non-determinism.
...
llvm-svn: 79856
2009-08-23 17:26:24 +00:00
972c8fab51
Fix PR4753.
...
When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a
sub-register being used. The MachineOperand::getSubReg() method is only valid
for virtual registers, so we have to recover the sub-register index manually.
llvm-svn: 79855
2009-08-23 13:01:45 +00:00
2982196fca
Speculatively revert r76823 (i.e., reapply r75663 and r76805) to see if the real
...
problem is fixed by the TableGen determinism fix.
llvm-svn: 79851
2009-08-23 10:44:51 +00:00
682d8c1881
Make x86 test actually test x86 code generation. Fix the
...
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
2009-08-22 03:13:10 +00:00
f09250f1b1
rename test, make more specific.
...
llvm-svn: 79712
2009-08-22 00:44:24 +00:00
48e4a6c739
Add missing RUN line
...
llvm-svn: 79707
2009-08-22 00:28:50 +00:00
5f47ecb918
Reduce the test
...
llvm-svn: 79703
2009-08-22 00:18:11 +00:00
616335f6c1
Use CHECK-NEXT to make sure we're only getting one copy of each shuffle
...
instruction.
llvm-svn: 79702
2009-08-22 00:13:23 +00:00
a70623102e
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
...
now using shuffles instead of intrinsics.
llvm-svn: 79673
2009-08-21 20:54:19 +00:00
f31a44ec01
Add fcopysign instructions
...
llvm-svn: 79664
2009-08-21 20:02:37 +00:00
a39f96c6ed
Handle 'r' inline asm constraint
...
llvm-svn: 79648
2009-08-21 18:15:41 +00:00
f73af72d30
Add some tests for vext.16 and vext.32.
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llvm-svn: 79638
2009-08-21 16:35:24 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
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vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
fa2b97e61a
Use FileCheck even though this means testing for something
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that has nothing to do with the point of the test, per Chris.
llvm-svn: 79569
2009-08-20 22:12:08 +00:00
05046085b6
Fix an x86 code size regression: prefer RIP-relative addressing
...
over absolute addressing even in non-PIC mode (unless the address
has an index or something else incompatible), because it has a
smaller encoding.
llvm-svn: 79553
2009-08-20 18:23:44 +00:00
01de985ae6
Fix an obvious copy-n-paste bug.
...
llvm-svn: 79535
2009-08-20 17:01:04 +00:00
d16abc09c4
Use FileCheck for the test run where it's appropriate.
...
llvm-svn: 79534
2009-08-20 16:58:04 +00:00
1d764f61ef
Handle 'a' modifier in X86 asms. PR 4742.
...
llvm-svn: 79484
2009-08-19 22:44:41 +00:00
6c528bc7ae
Make this test platform neutral.
...
llvm-svn: 79447
2009-08-19 18:51:45 +00:00
ac33a9061d
Add an x86 peep that narrows TEST instructions to forms that use
...
a smaller encoding. These kinds of patterns are very frequent in
sqlite3, for example.
llvm-svn: 79439
2009-08-19 18:16:17 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
...
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
1e008c173a
PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.
...
llvm-svn: 79415
2009-08-19 08:46:10 +00:00
4906f73a9f
Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and
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SRA_PARTS, as is done for SRL, SHL, and SRA.
llvm-svn: 79380
2009-08-18 23:36:17 +00:00
2349fb4d45
Add support for mergeable sections back into the XCore backend.
...
llvm-svn: 79368
2009-08-18 21:14:31 +00:00
934d61648b
Put data with relocations in the same sections as data without relocations.
...
llvm-svn: 79351
2009-08-18 17:58:17 +00:00
b85ad63727
Make this test less sensitive to assembler differences.
...
llvm-svn: 79348
2009-08-18 17:19:46 +00:00
8b0e164aa6
force a triple so this passes on darwin
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llvm-svn: 79345
2009-08-18 16:55:45 +00:00
a41fa35992
Make tail merging handle blocks with repeated predecessors correctly, and
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remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.
Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.
test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.
Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.
llvm-svn: 79338
2009-08-18 15:18:18 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
4a50e68b65
PowerPC inline asm was emitting two output operands
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for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible. 7144566.
llvm-svn: 79292
2009-08-18 00:18:39 +00:00
94a2c1acae
Update getSectionForConstant() to to allow mergable sections to be nulled out
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if not supported by the ELF subtarget.
llvm-svn: 79249
2009-08-17 16:37:11 +00:00
b4d7312249
Fix test on Linux.
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llvm-svn: 79140
2009-08-15 21:28:17 +00:00
bae6b2cca3
Reapply r79127. It was fixed by d0k.
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llvm-svn: 79136
2009-08-15 21:21:19 +00:00
d3fade656f
Revert r79127. It was causing compilation errors.
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llvm-svn: 79135
2009-08-15 21:14:01 +00:00
52d4e64711
Change allowsUnalignedMemoryAccesses to take type argument since some targets
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
2009-08-15 19:23:44 +00:00
da108b4ed4
implement support for CHECK-NEXT: in filecheck.
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llvm-svn: 79123
2009-08-15 18:32:21 +00:00
ffa73acfec
Refine EarlyClobber assert in register scavenger.
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It is legal for an inline asm operand to use an earlyclobber register if the
use operand is tied to the earlyclobber operand. The issue is discussed here:
http://gcc.gnu.org/ml/gcc/1999-04n/msg00431.html
We should perhaps let only the machine code verifier worry about these finer
details. EarlyClobber operands are not really interesting to the scavenger.
This fixes PR4528 for the third time.
llvm-svn: 79122
2009-08-15 18:16:58 +00:00
c6a803be7c
specify a target triple so global variable manglings are consistent etc.
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llvm-svn: 79118
2009-08-15 17:35:05 +00:00
3838c2dabf
convert to filecheck.
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llvm-svn: 79117
2009-08-15 17:28:09 +00:00
bb193ecec8
rename this test to sse2.ll
...
llvm-svn: 79116
2009-08-15 17:24:09 +00:00
d3954e2790
merge a bunch more sse3 tests into sse3.ll
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llvm-svn: 79115
2009-08-15 17:21:44 +00:00
9bae01ec47
convert test to filecheck format.
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llvm-svn: 79114
2009-08-15 17:05:03 +00:00
912aa19c25
rename test
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llvm-svn: 79113
2009-08-15 17:01:44 +00:00
e5b9130efe
this is a test for sse3, simplify it.
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llvm-svn: 79112
2009-08-15 17:01:19 +00:00
4af3c864bc
Don't setCalleeSavedInfoValid() until spills are interted.
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In a naked function, the flag is never set and getPristineRegs() returns an
empty list. That means naked functions are able to clobber callee saved
registers, but that is the whole point of naked functions.
This fixes PR4716.
llvm-svn: 79096
2009-08-15 13:10:46 +00:00
e31228e636
Add XFAIL testcase for setcc undef.
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llvm-svn: 79093
2009-08-15 12:10:22 +00:00
46da62b174
Add XFAIL test case for a scavenger assert.
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llvm-svn: 79092
2009-08-15 12:09:56 +00:00
abff8fcb1c
Update LocalRewriter::DistanceMap when inserting stack loads.
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In the included test case, a stack load was not included in DistanceMap. That
caused TransferDeadness to ignore the instruction, leading to a scavenger
assert.
llvm-svn: 79090
2009-08-15 11:03:03 +00:00
d7e1a79eea
Fix tests.
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llvm-svn: 79086
2009-08-15 08:23:11 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
93980d68e4
use XCore-specific section with xcore specific cp/dp flags to restore
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support for globals going into the appropriate sections with the flags.
This hopefully finishes unbreaking the previous behavior that I broke before.
llvm-svn: 79079
2009-08-15 06:09:35 +00:00
0700a56860
On x86-64, for a varargs function, don't store the xmm registers to
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the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.
llvm-svn: 79061
2009-08-15 01:38:56 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
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llvm-svn: 79039
2009-08-14 20:48:13 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
75821f7c69
Properly handle indirect win64 args when they're passed in memory
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llvm-svn: 79009
2009-08-14 18:19:10 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
62e6a8bbe6
Remove HasCrazyBSS and add a flag in TAI to indicate that '.section'
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must be emitted for PowerPC-Linux '.bss' section
llvm-svn: 78958
2009-08-13 23:30:21 +00:00
86c065dd68
Revert 78892 and 78895, these break generating working executables on
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x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
llvm-svn: 78919
2009-08-13 17:03:38 +00:00
68535f7603
reintroduce support for Mips "small" section handling. This is
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implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.
llvm-svn: 78900
2009-08-13 06:28:06 +00:00
f59e9f4288
tPOP_RET now has predicate operands.
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llvm-svn: 78898
2009-08-13 06:05:07 +00:00
00a8de054c
fix typo, add 10.6 version of test for my previous patch.
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llvm-svn: 78895
2009-08-13 05:43:33 +00:00
e5801bd220
It's ok to spill a tGPR register as long as it's still allocated a low register.
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llvm-svn: 78893
2009-08-13 05:40:51 +00:00
607cd3b63a
Change MCSectionELF to represent a section semantically instead of
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syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
llvm-svn: 78890
2009-08-13 05:07:35 +00:00
ef3d457126
Various AsmWriter output cleanups. Use WriteAsOperand instead of
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PrintUnmangledNameSafely.
llvm-svn: 78878
2009-08-13 01:36:44 +00:00
1c0e13fe66
Use WriteAsOperand to print BasicBlock names.
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llvm-svn: 78838
2009-08-12 20:56:56 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
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llvm-svn: 78835
2009-08-12 20:51:55 +00:00
58043874ce
Test for 78821, sort of. While that bug is nondeterministic,
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this test failed consistently on a Darwin build.
llvm-svn: 78822
2009-08-12 17:43:47 +00:00
1235f20744
one last (?) bad x86 triple test.
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llvm-svn: 78801
2009-08-12 06:49:44 +00:00
6628e17344
fix some pastos in triple lines.
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llvm-svn: 78800
2009-08-12 06:49:12 +00:00
0ea6e4cc7f
another bogus triple
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llvm-svn: 78798
2009-08-12 06:36:52 +00:00
8c2d846a42
fix another broken target triple.
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llvm-svn: 78796
2009-08-12 06:29:18 +00:00
d4a70aedb0
fix an incorrect target triple.
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llvm-svn: 78795
2009-08-12 06:28:51 +00:00
774a88aa77
add nounwind
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llvm-svn: 78791
2009-08-12 05:44:03 +00:00
608d92c943
Remove an Darwin assembler workaround.
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llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
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llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
0c533d909a
now that these are in file-check format, we can merge them together
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into one bigger test (which runs faster)
llvm-svn: 78672
2009-08-11 15:54:17 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
...
llvm-svn: 78659
2009-08-11 09:37:40 +00:00
b39a5aa794
Rebuild RegScavenger::DistanceMap each time it is needed.
...
The register scavenger maintains a DistanceMap that maps MI pointers to their
distance from the top of the current MBB. The DistanceMap is built
incrementally in forward() and in bulk in findFirstUse(). It is used by
scavengeRegister() to determine which candidate register has the longest
unused interval.
Unfortunately the DistanceMap contents can become outdated. The first time
scavengeRegister() is called, the DistanceMap is filled to cover the MBB. If
then instructions are inserted in the MBB (as they always are following
scavengeRegister()), the recorded distances are too short. This causes bad
behaviour in the included test case where a register use /after/ the current
position is ignored because findFirstUse() thinks is is /before/ the current
position. A "using an undefined register" assertion follows promptly.
The fix is to build a fresh DistanceMap at the top of scavengeRegister(), and
discard it after use. This means that DistanceMap is no longer needed as a
RegScavenger member variable, and forward() doesn't need to update it.
The fix then discloses issue number two in the same test case: The candidate
search in scavengeRegister() finds a CSR that has been saved in the prologue,
but is currently unused. It would be both inefficient and wrong to spill such
a register in the emergency spill slot. In the present case, the emergency
slot restore is placed immediately before the normal epilogue restore, leading
to a "Redefining a live register" assertion.
Fix number two: When scavengerRegister() stumbles upon an unused register that
is overwritten later in the MBB, return that register early. It is important
to verify that the register is defined later in the MBB, otherwise it might be
an unspilled CSR.
llvm-svn: 78650
2009-08-11 06:25:12 +00:00
8f5c447bfa
Convert more Neon tests to use FileCheck.
...
llvm-svn: 78648
2009-08-11 05:51:19 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
...
llvm-svn: 78622
2009-08-10 23:56:04 +00:00
9d26c85bdc
Fix a bug in the DAGCombiner's handling of multiple linked
...
MERGE_VALUES nodes. Replacing the result values with the
operands in one MERGE_VALUES node may cause another
MERGE_VALUES node be CSE'd with the first one, and bring
its uses along, so that the first one isn't dead, as this
code expects. Fix this by iterating until the node is
really dead. This fixes PR4699.
llvm-svn: 78619
2009-08-10 23:43:19 +00:00
d9aedcae23
Use FileCheck.
...
llvm-svn: 78614
2009-08-10 23:14:14 +00:00
bdf1a1d1a2
Use FileCheck... its good for you...
...
llvm-svn: 78613
2009-08-10 23:06:57 +00:00
9e7c7e748f
Fix test.
...
llvm-svn: 78611
2009-08-10 22:58:08 +00:00
108b522912
Fix test.
...
llvm-svn: 78606
2009-08-10 22:31:04 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
...
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
676d115ce5
Add nounwind keywords.
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llvm-svn: 78568
2009-08-10 16:48:40 +00:00
cb307a27bf
Make the big switch: Change MCSectionMachO to represent a section *semantically*
...
instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
llvm-svn: 78547
2009-08-10 01:39:42 +00:00
7fc63417d7
Add tests for Neon VZIP and VUZP instructions.
...
llvm-svn: 78529
2009-08-09 06:48:29 +00:00
f60c8807e8
Add a test for Neon VTRN instructions.
...
llvm-svn: 78528
2009-08-09 06:30:46 +00:00
7dfa9f2e56
Add crc32 instruction and intrinsics. Add a new class of prefix
...
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
llvm-svn: 78508
2009-08-08 21:55:08 +00:00
e2dc8a46e9
Add support for READCYCLECOUNTER in Blackfin back-end.
...
llvm-svn: 78506
2009-08-08 21:42:22 +00:00
dc6bccbaa6
Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().
...
Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.
llvm-svn: 78497
2009-08-08 20:42:17 +00:00
ac51533b8a
Simplify RegScavenger::forward a bit more.
...
Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
2009-08-08 13:18:47 +00:00
674ffc1e59
Do not generate 32-bit call on win64 when imm does not fit
...
llvm-svn: 78443
2009-08-07 23:59:21 +00:00
6eceb7c85d
rename test
...
llvm-svn: 78441
2009-08-07 23:57:30 +00:00
ff8d04e815
merge a bunch of tests together into one, convert to filecheck which
...
is more tolerant of whitespace differences.
llvm-svn: 78439
2009-08-07 23:56:42 +00:00
97262e01d5
Convert more Neon tests to use FileCheck.
...
llvm-svn: 78433
2009-08-07 23:45:02 +00:00
742db6a6d4
Make NEON single-precision FP support the default for cortex-a8 (again).
...
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
23b28cb824
2 more vdup.32 cases
...
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
...
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
...
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
b1aeeed03e
Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
...
llvm-svn: 78376
2009-08-07 07:14:14 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
3a127ce1d8
Add the testcase from PR 4668. This works at the
...
moment, but it's a fragile area.
llvm-svn: 78358
2009-08-07 00:04:42 +00:00
15a5fad94b
Fix PR 4626, a crash in branch folding after OptimizeBlock
...
produced a CFG it wasn't prepared for.
llvm-svn: 78351
2009-08-06 22:56:40 +00:00
0127031c20
Implement Neon VST[234] operations.
...
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
e3ec5b6d76
Fix incorrect intrinsic declarations.
...
llvm-svn: 78329
2009-08-06 18:46:26 +00:00
b4764e5b7f
Tidy up this testcase.
...
llvm-svn: 78322
2009-08-06 17:11:55 +00:00
a7e2662770
reduce testcase.
...
llvm-svn: 78315
2009-08-06 16:14:33 +00:00
ee902509a8
Remove an over-aggressive assert. Functions with empty struct return
...
types don't have any return values, from CodeGen's perspective.
This fixes PR4688.
llvm-svn: 78311
2009-08-06 15:07:58 +00:00
644caa0cdb
Add tests for X86-64 code model handling. Small and kernel for now.
...
llvm-svn: 78300
2009-08-06 12:25:20 +00:00
130e2c7aed
Fix a bug in x86's PreprocessForRMW logic that was exposed
...
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.
llvm-svn: 78297
2009-08-06 09:22:57 +00:00
5758e1e92a
Fix a few places in DAGCombiner that were creating all-ones-bits
...
and high-bits values in ways that weren't correct for integer
types wider than 64 bits. This fixes a miscompile in
PPMacroExpansion.cpp in clang on x86-64.
llvm-svn: 78295
2009-08-06 09:18:59 +00:00
87754848ab
this passes.
...
llvm-svn: 78281
2009-08-06 03:55:49 +00:00
aee88e46c1
XFAIL it while it is being worked on.
...
llvm-svn: 78275
2009-08-06 02:19:20 +00:00
3389c2f7d0
Add tests for new NEON vld instructions.
...
llvm-svn: 78264
2009-08-06 00:38:31 +00:00
dd611f44cb
Convert more Neon tests to FileCheck.
...
llvm-svn: 78261
2009-08-05 23:51:20 +00:00
22ef75155e
Missed pieces for ARM HardFP ABI.
...
Patch by Sandeep Patel!
llvm-svn: 78225
2009-08-05 19:04:42 +00:00
df7ea32af7
Enable the new no-SP register classes by default. This is to address
...
PR4572. A few tests have some minor code regressions due to different
coalescing.
llvm-svn: 78217
2009-08-05 17:40:24 +00:00
f6e25b3039
Add testcases for reg-mem arithemtics added recently
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llvm-svn: 78214
2009-08-05 17:04:32 +00:00
be47ccffef
Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
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llvm-svn: 78212
2009-08-05 16:50:53 +00:00
477fd55c9a
Fix a bug in the PIC16 backend.
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llvm-svn: 78211
2009-08-05 16:46:43 +00:00
2bebfc38af
Change these tests to use function attributes rather than special llc
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command-line options.
llvm-svn: 78204
2009-08-05 16:37:27 +00:00
abde7f9d27
checking in broken testcases is not such a good idea.
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llvm-svn: 78201
2009-08-05 16:04:18 +00:00
63c5ede173
Quite a few tests crashed in llc after 78142. This is just one of them. I hope to add a few more.
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llvm-svn: 78198
2009-08-05 15:52:14 +00:00
ea2b82b8fc
Disable stack coloring with register for now. It's not able to set kill markers.
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llvm-svn: 78179
2009-08-05 07:26:17 +00:00
Anton Korobeynikov