Commit Graph

336 Commits

Author SHA1 Message Date
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
2009-06-29 07:51:04 +00:00
David Goodwin 34f7ede9e7 ORN and BIC tests.
llvm-svn: 74289
2009-06-26 16:20:06 +00:00
Evan Cheng 7779156b39 Fix tests: Count -> count.
llvm-svn: 74282
2009-06-26 07:05:57 +00:00
Evan Cheng 34c8c7414f Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
llvm-svn: 74276
2009-06-26 05:59:16 +00:00
Evan Cheng 97727a61f9 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
llvm-svn: 74228
2009-06-25 23:34:10 +00:00
Evan Cheng c7ea8df67e ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
llvm-svn: 74200
2009-06-25 20:59:23 +00:00
Evan Cheng d76d0aa68a Move thumb and thumb2 tests into separate directories.
llvm-svn: 74068
2009-06-24 06:36:07 +00:00
Evan Cheng 4983e4550e Proper patterns for thumb2 shift and rotate instructions.
llvm-svn: 73987
2009-06-23 19:39:13 +00:00
Bob Wilson 2e076c4e02 Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
2009-06-22 23:27:02 +00:00
Evan Cheng 16ee19738c It's coalescer, not coaleser.
llvm-svn: 73902
2009-06-22 21:09:17 +00:00
Bob Wilson 4582530a2c For Darwin on ARMv6 and newer, make register r9 available for use as a
caller-saved register.

llvm-svn: 73901
2009-06-22 21:01:46 +00:00
Evan Cheng 8cbbc7944d Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.
llvm-svn: 73898
2009-06-22 20:49:32 +00:00
Evan Cheng 3d75d6af57 hasFP should return true if frame address is taken.
llvm-svn: 73893
2009-06-22 18:38:48 +00:00
Evan Cheng c6a8d0dbe9 Fix PR4419: handle defs of partial uses.
llvm-svn: 73816
2009-06-20 04:34:51 +00:00
Evan Cheng b4b20bbb7d Enable arm pre-allocation load / store multiple optimization pass.
llvm-svn: 73791
2009-06-19 23:17:27 +00:00
Eli Friedman d984158320 Mark a few Thumb instructions commutable; just happened to spot this
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.

llvm-svn: 73746
2009-06-19 01:43:08 +00:00
Anton Korobeynikov 02bb33c58d Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622
2009-06-17 18:13:58 +00:00
Anton Korobeynikov 469e8217d4 Make the test target-neutral
llvm-svn: 73547
2009-06-16 20:25:25 +00:00
Anton Korobeynikov 5d28cb204f GNU as refuses to assemble "pop {}" instruction. Do not emit such
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529
2009-06-16 18:49:08 +00:00
Evan Cheng cc21a5415a If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.

llvm-svn: 73478
2009-06-16 07:12:58 +00:00
Evan Cheng b9bff5880a ifcvt should ignore cfg where true and false successors are the same.
llvm-svn: 73423
2009-06-15 21:24:34 +00:00
Evan Cheng 1283c6a066 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
2009-06-15 08:28:29 +00:00
Evan Cheng 185c9ef0a2 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
2009-06-13 09:12:55 +00:00
Evan Cheng b6cf8dbb96 If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
llvm-svn: 73255
2009-06-12 21:34:26 +00:00
Evan Cheng d93b5b672f Mark some pattern-less instructions as neverHasSideEffects.
llvm-svn: 73252
2009-06-12 20:46:18 +00:00
Anton Korobeynikov c745132865 Add testcase for register scanveger assertion fix in r72755
(double def due to livevars)

llvm-svn: 73096
2009-06-08 22:54:15 +00:00
Evan Cheng 3158790e32 Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
llvm-svn: 72955
2009-06-05 19:08:58 +00:00
Dan Gohman a5b9645c4b Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00
Evan Cheng 60fdf787a7 A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
llvm-svn: 72888
2009-06-04 20:25:48 +00:00
Evan Cheng 7f5976e11b Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
llvm-svn: 72826
2009-06-04 01:15:28 +00:00
Evan Cheng ab0c710fae Temporarily revert 72756 for now.
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
Evan Cheng dfe6e689fd Fold preceding / trailing base inc / dec into the single load / store as well.
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
Bob Wilson e666cc5206 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
the stack.  Patch by Sandeep Patel.

llvm-svn: 72106
2009-05-19 10:02:36 +00:00
Bob Wilson a2c462bbe9 Fix pr4091: Add support for "m" constraint in ARM inline assembly.
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
Dan Gohman b81dd48fd2 Add nounwind to a few tests.
llvm-svn: 72002
2009-05-18 15:16:49 +00:00
Bob Wilson 9e3d48f10d Fix pr4195: When iterating through predecessor blocks, break out of the loop
after finding the (unique) layout predecessor.  Sometimes a block may be listed
more than once, and processing it more than once in this loop can lead to
inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not
clear these values.  There's no point in continuing the loop regardless.
The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource
test.

llvm-svn: 71536
2009-05-12 03:48:10 +00:00
Bob Wilson e20be4183c Fix pr4100. Do not remove no-op copies when they are dead. The register
scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.

Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move.  Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move.  The move ends up being a no-op, copying R3 to R3, so it is
deleted.  But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.

Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
  Regs have values: 
  Reloading %reg1028 into R3
  Last use of R3[%reg1028], removing it from live set
  Assigning R3 to %reg1025
  Register R3 [%reg1025] is never used, removing it from live set

Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy.  I couldn't see an easy way to do
either of those, though.

llvm-svn: 71196
2009-05-07 23:47:03 +00:00
Evan Cheng cfc0513080 Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
llvm-svn: 71098
2009-05-06 18:25:01 +00:00
Dan Gohman ff08995589 Previously, RecursivelyDeleteDeadInstructions provided an option
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.

Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.

This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.

llvm-svn: 70636
2009-05-02 18:29:22 +00:00
Bob Wilson 9c1ec76084 Rename file to have the correct suffix.
llvm-svn: 69380
2009-04-17 20:40:20 +00:00
Bob Wilson a4c2290e5f Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM.  Patch by Sandeep Patel.

llvm-svn: 69371
2009-04-17 19:07:39 +00:00
Dan Gohman 0a40ad93a9 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.

Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.

Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.

llvm-svn: 69258
2009-04-16 03:18:22 +00:00
Dale Johannesen b866ce73b2 Use the output of the asm so the optimizer won't
delete it.

llvm-svn: 69018
2009-04-14 01:51:40 +00:00
Chris Lattner 4d59f88e60 move a target-specific test into its directory so it isn't run if you
don't configure the ARM target in.

llvm-svn: 68843
2009-04-10 23:58:38 +00:00
Bob Wilson 51856173c8 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Bob Wilson 8462791237 Add testcase for PR3795.
llvm-svn: 68620
2009-04-08 18:00:55 +00:00
Duncan Sands 5a82613db0 Soft float support for FREM.
llvm-svn: 68614
2009-04-08 16:20:57 +00:00
Duncan Sands fb438caac6 Soft float support for undef. Reported by Xerxes Rånby.
llvm-svn: 68607
2009-04-08 13:33:37 +00:00
Bob Wilson 0669f6d295 Handle 'a' modifier in ARM inline assembly.
Patch by Richard Pennington.

llvm-svn: 68464
2009-04-06 21:46:51 +00:00
Bob Wilson cf1ec2cc68 Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
assembly.

llvm-svn: 68218
2009-04-01 17:58:54 +00:00
Evan Cheng a774a99245 Do not emit comments unless -asm-verbose.
llvm-svn: 67580
2009-03-24 00:17:40 +00:00
Chris Lattner 7b87e542dc add no-unwind, remove duplicate run line.
llvm-svn: 66775
2009-03-12 05:56:37 +00:00
Evan Cheng ce5dfb692a ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
llvm-svn: 66429
2009-03-09 19:15:00 +00:00
Evan Cheng ec415efb44 Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
llvm-svn: 66365
2009-03-08 04:02:49 +00:00
Evan Cheng de22116f39 If a MI uses the same register more than once, only mark one of them as 'kill'.
llvm-svn: 66363
2009-03-08 03:58:35 +00:00
Evan Cheng 398dee1c4a Last commit accidentially deleted this code.
llvm-svn: 65679
2009-02-28 06:02:14 +00:00
Evan Cheng ca2d65467b The last commit was overly conservative. It's ok to reuse value that's already marked livein.
llvm-svn: 65498
2009-02-26 03:02:21 +00:00
Evan Cheng e779595af0 If a use operand is marked isKill, don't forget to add kill to its live interval as well.
llvm-svn: 65279
2009-02-22 08:35:56 +00:00
Evan Cheng f505cd5ebb A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.
llvm-svn: 64745
2009-02-17 06:41:03 +00:00
Evan Cheng 3a14efacb6 Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite.
llvm-svn: 64369
2009-02-12 08:59:45 +00:00
Evan Cheng ce3bbe515b Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated.
llvm-svn: 64210
2009-02-10 08:30:11 +00:00
Evan Cheng f736bd9c79 Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed.
llvm-svn: 64126
2009-02-09 08:45:39 +00:00
Bill Wendling 5469ec1072 Revert r63999. It was breaking self-hosting builds.
llvm-svn: 64062
2009-02-08 00:58:05 +00:00
Evan Cheng 9571621665 Enable machine sinking pass in non-fast mode.
llvm-svn: 63999
2009-02-07 01:57:46 +00:00
Evan Cheng 409c25f78d Turn on machine LICM in non-fast mode.
llvm-svn: 63855
2009-02-05 08:46:33 +00:00
Rafael Espindola 6de96a1b5d Add the private linkage.
llvm-svn: 62279
2009-01-15 20:18:42 +00:00
Evan Cheng ab85feb91c Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
llvm-svn: 60621
2008-12-06 02:00:55 +00:00
Evan Cheng c22215a090 - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.

llvm-svn: 59697
2008-11-20 02:32:35 +00:00
Evan Cheng 3095c32c89 Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later.
llvm-svn: 59559
2008-11-18 22:28:38 +00:00
Evan Cheng e3827d9061 Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
llvm-svn: 58725
2008-11-04 22:19:55 +00:00
Evan Cheng 297b32a367 Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
llvm-svn: 58714
2008-11-04 19:57:48 +00:00
Devang Patel 9eb525d4f9 Implement function notes as function attributes.
llvm-svn: 56716
2008-09-26 23:51:19 +00:00
Evan Cheng f3fcd7a464 Unallocatable registers do not have live intervals.
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
Dan Gohman 3c7b9ba547 Re-enable SelectionDAG CSE for calls. It matters in the case of
libcalls, as in this testcase on ARM.

llvm-svn: 56226
2008-09-15 19:46:03 +00:00
Evan Cheng 02acc35abd Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
Evan Cheng f4e5de4583 Legalizer was missing code that expand fpow to a libcall.
llvm-svn: 56028
2008-09-09 23:02:14 +00:00
Evan Cheng 655fa0fec4 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
Anton Korobeynikov 9dbbd75068 Print section flags ok on platforms, which use '@' as comment string. Fix test.
llvm-svn: 54460
2008-08-07 09:55:06 +00:00
Owen Anderson 04c047ddca This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding.
llvm-svn: 54355
2008-08-05 17:52:54 +00:00
Owen Anderson 252fa16db1 Remove the need for -disable-correct-folding from this test.
llvm-svn: 54354
2008-08-05 17:49:52 +00:00
Owen Anderson 5018bd032a Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these.
llvm-svn: 54334
2008-08-04 23:55:29 +00:00
Evan Cheng c90a11256e Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
llvm-svn: 54004
2008-07-25 00:55:17 +00:00
Duncan Sands 6b418e750d Softfloat support for FDIV. Patch by
Richard Pennington.

llvm-svn: 53773
2008-07-18 21:18:48 +00:00
Gabor Greif 1e427c3264 sabre brings to my attention that the 'tr' suffix is also obsolete
llvm-svn: 51349
2008-05-20 21:00:03 +00:00
Gabor Greif f45ff35bfe Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too.
llvm-svn: 51328
2008-05-20 19:52:04 +00:00
Evan Cheng 0609ab646b More local spiller complexity!
If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.

llvm-svn: 51306
2008-05-20 08:13:21 +00:00
Evan Cheng c8b028daa4 Don't spill dead def.
llvm-svn: 51305
2008-05-20 08:10:37 +00:00
Evan Cheng 33281864c1 If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy.
llvm-svn: 49543
2008-04-11 17:54:45 +00:00
Evan Cheng b53d560150 New test.
llvm-svn: 49514
2008-04-10 23:49:09 +00:00
Evan Cheng b5fdc923d3 1. IMPLICIT_DEF can *re-define* any register.
2. Coalescer can now create an interesting situation where a register def can
   reaches itself without being killed.

llvm-svn: 49246
2008-04-05 01:27:09 +00:00
Evan Cheng 0bd72c5ccd More soft fp fixes.
llvm-svn: 49016
2008-04-01 02:18:22 +00:00
Evan Cheng 86e476b7cb Unbreak ARM / Thumb soft FP support.
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
Evan Cheng 39a3221e27 Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
llvm-svn: 48024
2008-03-07 20:12:54 +00:00
Evan Cheng a3cb090446 Constant fold SIGN_EXTEND_INREG with ashr not lshr.
llvm-svn: 47992
2008-03-06 08:20:51 +00:00
Bill Wendling 16f1e0be3d DCE'ed this testcase.
llvm-svn: 47760
2008-02-29 19:28:11 +00:00
Bill Wendling 811153a551 If we reload a virtual register that's already been assigned, we want to mark
that instruction as its "last use". This fixes PR1925.

llvm-svn: 47758
2008-02-29 18:52:01 +00:00
Tanya Lattner f697c03883 Remove llvm-upgrade.
llvm-svn: 47238
2008-02-17 20:02:20 +00:00
Evan Cheng 127b41500c It's PR1925, not PR1609.
llvm-svn: 46825
2008-02-06 22:07:17 +00:00
Evan Cheng 1ec748c784 Fix a number of local register allocator issues: PR1609.
llvm-svn: 46821
2008-02-06 19:16:53 +00:00
Chris Lattner 34d6b6a319 Update this test. Due to dag combiner improvements, we now compile
f7/f11 to:

_f7:
	eor r0, r0, #2, 2 @ -2147483648
	bx lr
_f11:
	bic r0, r0, #2, 2 @ -2147483648
	bx lr

instead of:

_f7:
	fmsr s0, r0
	fnegs s0, s0
	fmrs r0, s0
	bx lr

_f11:
	fmsr s0, r0
	fabss s0, s0
	fmrs r0, s0
	bx lr

llvm-svn: 46423
2008-01-27 23:26:37 +00:00
Evan Cheng ddc9af11f0 Remove xfail. This is fixed.
llvm-svn: 45254
2007-12-20 02:25:21 +00:00
Evan Cheng 8393dc7378 Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta.
llvm-svn: 44660
2007-12-06 08:54:31 +00:00
Evan Cheng 7fc1d98353 Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate.
llvm-svn: 44644
2007-12-06 00:01:56 +00:00
Evan Cheng 37ed3e6320 Update tests.
llvm-svn: 44435
2007-11-29 10:03:54 +00:00
Chris Lattner e04dc1fa4d update this test after the fmrrd fix
llvm-svn: 44393
2007-11-28 05:27:07 +00:00
Tanya Lattner 8f342f8ef3 Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines.
XFAILed 3 arm regressions (will file bugs)

llvm-svn: 44389
2007-11-28 04:57:00 +00:00
Chris Lattner f247e27666 commit testcase I forgot to svn add.
llvm-svn: 44383
2007-11-27 22:43:37 +00:00
Lauro Ramos Venancio f6a67bf700 [ARM] Implement __builtin_thread_pointer.
llvm-svn: 43892
2007-11-08 17:20:05 +00:00
Lauro Ramos Venancio 1a30c18e88 [ARM] Fix code generation for:
static __thread struct {
    int a;
    int b;
} teste = {0, 0};

llvm-svn: 43722
2007-11-05 18:33:37 +00:00
Evan Cheng 1f2dd35898 Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
llvm-svn: 43234
2007-10-22 22:11:27 +00:00
Chris Lattner 2ce649ebea new testcase
llvm-svn: 42953
2007-10-13 06:56:18 +00:00
Evan Cheng 723dab1005 Disable if-conversion for this test.
llvm-svn: 42170
2007-09-20 18:06:22 +00:00
Evan Cheng 77d4771405 -enable-arm-if-conversion is gone.
llvm-svn: 42169
2007-09-20 18:03:23 +00:00
Dale Johannesen 6480cc6f8c Change all floating constants that are not exactly
representable to use hex format.

llvm-svn: 41722
2007-09-05 17:50:36 +00:00
Duncan Sands 6820abe101 Testcases for PR1628.
llvm-svn: 41719
2007-09-05 11:53:04 +00:00
Lauro Ramos Venancio a392cd2fde Implement FPOWI ExpandOp.
Fix PR1287.

llvm-svn: 41112
2007-08-15 22:13:27 +00:00
Evan Cheng 2047077272 Test case for PR1609.
llvm-svn: 41110
2007-08-15 20:30:10 +00:00
Dan Gohman 413a23d257 This test used "wc | grep ..."; convert it to use the count script.
llvm-svn: 41101
2007-08-15 13:55:47 +00:00
Dan Gohman ada7205b76 Convert tests using "grep -c ... | grep ..." to use the count script.
llvm-svn: 41100
2007-08-15 13:49:33 +00:00
Dan Gohman f9dd170e36 Convert tests using "| wc -l | grep ..." to use the count script.
llvm-svn: 41097
2007-08-15 13:36:28 +00:00
Evan Cheng 7fe896120e New test.
llvm-svn: 41087
2007-08-14 23:34:50 +00:00
Lauro Ramos Venancio 0db4418a5f Expand unaligned loads/stores when the target doesn't support them. (PR1548)
llvm-svn: 40682
2007-08-01 19:34:21 +00:00
Reid Spencer 314e1cb7ee For PR1553:
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.

llvm-svn: 40069
2007-07-19 23:13:04 +00:00
Dan Gohman 5740239998 Add explicit triples to these tests so that llc behaves as expected on
non-Apple hosts.

llvm-svn: 38455
2007-07-09 13:42:32 +00:00
John Criswell 2660cef6d7 Convert .cvsignore files
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
Dan Gohman 0de7694de6 Fix an assertion failure in legalizing bitcast operators on targets where
vectors are split down to single elements as part of legalization.

llvm-svn: 37785
2007-06-29 00:09:08 +00:00
Evan Cheng e15ea75168 Fix tests.
llvm-svn: 37693
2007-06-21 18:22:42 +00:00
Evan Cheng 5fcb5a5c74 New tests.
llvm-svn: 37686
2007-06-21 07:40:00 +00:00
Evan Cheng 85010166a6 Added some if-conversion tests.
llvm-svn: 37672
2007-06-20 18:26:15 +00:00
Lauro Ramos Venancio 5a3e6fe365 Add a test for PR1424.
llvm-svn: 37372
2007-05-31 18:36:07 +00:00
Evan Cheng b58bf97603 Add a new test case.
llvm-svn: 37317
2007-05-24 02:31:15 +00:00
Dale Johannesen a7120dde08 new testcases for -enable-tail-merge default handling
llvm-svn: 37287
2007-05-22 17:19:23 +00:00
Chris Lattner c5900bd25b testcase that crashes llc
llvm-svn: 37059
2007-05-15 01:13:42 +00:00
Evan Cheng 4c28ec187e Test for PR1406.
llvm-svn: 37051
2007-05-14 21:12:43 +00:00
Lauro Ramos Venancio 3551928a2b Enable aliases on arm-linux.
llvm-svn: 37042
2007-05-14 18:32:56 +00:00
Dale Johannesen b42c11265c Another test for tail mergeing
llvm-svn: 36967
2007-05-10 01:04:28 +00:00
Evan Cheng db214c77b4 Can't fold bit_convert into truncating store.
llvm-svn: 36963
2007-05-09 21:54:34 +00:00
Dale Johannesen 882a6019af testcase for CodeGenPrepare bug fixed yesterday
llvm-svn: 36940
2007-05-08 17:44:36 +00:00
Chris Lattner 4ef41c1054 move this out of Codegen/Generic, because it requires the ARM backend to be
linked into llc

llvm-svn: 36919
2007-05-08 02:19:56 +00:00
Evan Cheng ef409e2780 Fix tests.
llvm-svn: 36913
2007-05-07 21:50:07 +00:00
Evan Cheng 2d828d2e3c Add some tests for (conv (load x)) -> (load (conv*)x) xform.
llvm-svn: 36912
2007-05-07 21:49:35 +00:00
Lauro Ramos Venancio 34b2735f20 Fix PR1390.
Don't spill extra register to align the stack.

llvm-svn: 36814
2007-05-05 23:44:41 +00:00
Chris Lattner 1c0af142a9 remove xfailed testcase (attached to pr)
llvm-svn: 36797
2007-05-05 21:57:34 +00:00
Evan Cheng 726e66f734 Test load global in static mode.
llvm-svn: 36719
2007-05-04 00:29:34 +00:00
Evan Cheng 579abf45bb New test case.
llvm-svn: 36717
2007-05-03 23:53:36 +00:00
Dale Johannesen 89200ce0f0 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
llvm-svn: 36693
2007-05-03 20:54:42 +00:00
Chris Lattner 483dc2bf08 match a reassociated form of fnmul
llvm-svn: 36659
2007-05-03 00:31:40 +00:00
Evan Cheng 8a16201953 Test a dag combiner crasher.
llvm-svn: 36605
2007-05-01 00:40:38 +00:00
Reid Spencer e7449654d1 For PR1370:
Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.

llvm-svn: 36587
2007-04-30 05:11:58 +00:00