f3369c22a7
Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
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llvm-svn: 81878
2009-09-15 17:53:11 +00:00
6c89da7027
Define proper subreg sets for arm - this should fix bunch of subtle problems
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with subreg - superreg mapping and also fix PR4965.
llvm-svn: 81657
2009-09-13 00:59:43 +00:00
b165c11021
Remove an unnecessary -f.
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llvm-svn: 81546
2009-09-11 18:41:06 +00:00
a080159a7c
Convert more tests to avoid llvm-as.
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llvm-svn: 81545
2009-09-11 18:36:27 +00:00
39f51320ca
Don't swap the operands of a subtraction when trying to create a
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post-decrement load/store.
llvm-svn: 81464
2009-09-10 22:09:31 +00:00
a2e8333eed
Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
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See the bug report for details.
llvm-svn: 81397
2009-09-09 23:14:54 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
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llvm-svn: 81293
2009-09-09 00:09:15 +00:00
7697d37777
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
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llvm-svn: 81262
2009-09-08 22:51:43 +00:00
59e2b8e894
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
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makes the code faster.
llvm-svn: 81220
2009-09-08 15:22:32 +00:00
30e30587eb
Remove stale greps.
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llvm-svn: 80986
2009-09-04 05:07:52 +00:00
36d8c75eca
Convert tests to FileCheck.
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llvm-svn: 80983
2009-09-04 04:07:19 +00:00
e072f8eedb
Convert a test to FileCheck.
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llvm-svn: 80975
2009-09-04 00:32:31 +00:00
1b38952c99
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
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llvm-svn: 80904
2009-09-03 07:04:02 +00:00
f0da41c3e4
More missed vdup patterns
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llvm-svn: 80838
2009-09-02 21:21:28 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
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llvm-svn: 80707
2009-09-01 18:51:56 +00:00
39dc89b458
Fix incorrect declarations of intrinsics in this test.
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llvm-svn: 80705
2009-09-01 18:50:43 +00:00
ff69320427
Add test for vld{234}_lane instructions.
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llvm-svn: 80658
2009-09-01 04:27:10 +00:00
33b408a10f
Fix pr4843: When an instruction has multiple destination registers that are
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tied to different source registers, the TwoAddressInstructionPass needs to
be smarter. Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.
llvm-svn: 80654
2009-09-01 04:18:40 +00:00
f09e8d5497
SJLJ is arm/darwin only for now. force the triple for the test
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llvm-svn: 80651
2009-09-01 02:34:49 +00:00
20eac92d88
Clean up LSDA name generation and use for SJLJ exception handling. This
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
llvm-svn: 80649
2009-09-01 01:57:56 +00:00
c8985204d9
Don't mark a register live at an undef use.
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llvm-svn: 80621
2009-08-31 20:47:02 +00:00
3681144bd8
Add missed pattern
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llvm-svn: 80502
2009-08-30 19:06:39 +00:00
eab572a8ff
EXTRACT_VECTOR_ELEMENT can have result type different from element type.
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Remove the assertion and generalize the code for ARM NEON stuff.
llvm-svn: 80498
2009-08-30 17:14:54 +00:00
ece642a54c
Do not assert on too wide splats we don't support.
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llvm-svn: 80409
2009-08-29 00:08:18 +00:00
cd41d07f29
Add missed extract_element pattern
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llvm-svn: 80408
2009-08-28 23:41:26 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
6da267de23
v4, v5 does not support sxtb / sxth.
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llvm-svn: 80322
2009-08-28 00:31:43 +00:00
205cac837f
scalar_to_vector is fully legal now (implemented as subreg accesses)
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llvm-svn: 80249
2009-08-27 16:04:47 +00:00
d0b0262edf
Ok, sometimes it's profitable to turn scalar_to_vector stuff into subreg access.
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Add a testcase.
llvm-svn: 80246
2009-08-27 14:51:42 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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llvm-svn: 80191
2009-08-27 01:23:50 +00:00
faebdee4dd
Convert some more Neon tests to FileCheck.
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llvm-svn: 80120
2009-08-26 18:11:50 +00:00
0f756b27ae
Expand scalar_to_vector - we don't have any isel logic for it now
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llvm-svn: 80107
2009-08-26 16:26:09 +00:00
ae6bc8214a
Fixup register kills after scheduling.
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llvm-svn: 80002
2009-08-25 17:03:05 +00:00
0d4bbf2c4a
Remove obsolete -f flags.
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llvm-svn: 79992
2009-08-25 15:38:29 +00:00
fbc9a2e33b
Split test into 3.
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llvm-svn: 79926
2009-08-24 17:51:19 +00:00
682d8c1881
Make x86 test actually test x86 code generation. Fix the
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construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
2009-08-22 03:13:10 +00:00
616335f6c1
Use CHECK-NEXT to make sure we're only getting one copy of each shuffle
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instruction.
llvm-svn: 79702
2009-08-22 00:13:23 +00:00
a70623102e
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
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now using shuffles instead of intrinsics.
llvm-svn: 79673
2009-08-21 20:54:19 +00:00
f73af72d30
Add some tests for vext.16 and vext.32.
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llvm-svn: 79638
2009-08-21 16:35:24 +00:00
51c7aa04ec
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
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vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
bae6b2cca3
Reapply r79127. It was fixed by d0k.
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llvm-svn: 79136
2009-08-15 21:21:19 +00:00
d3fade656f
Revert r79127. It was causing compilation errors.
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llvm-svn: 79135
2009-08-15 21:14:01 +00:00
52d4e64711
Change allowsUnalignedMemoryAccesses to take type argument since some targets
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
llvm-svn: 79127
2009-08-15 19:23:44 +00:00
ffa73acfec
Refine EarlyClobber assert in register scavenger.
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It is legal for an inline asm operand to use an earlyclobber register if the
use operand is tied to the earlyclobber operand. The issue is discussed here:
http://gcc.gnu.org/ml/gcc/1999-04n/msg00431.html
We should perhaps let only the machine code verifier worry about these finer
details. EarlyClobber operands are not really interesting to the scavenger.
This fixes PR4528 for the third time.
llvm-svn: 79122
2009-08-15 18:16:58 +00:00
4af3c864bc
Don't setCalleeSavedInfoValid() until spills are interted.
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In a naked function, the flag is never set and getPristineRegs() returns an
empty list. That means naked functions are able to clobber callee saved
registers, but that is the whole point of naked functions.
This fixes PR4716.
llvm-svn: 79096
2009-08-15 13:10:46 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
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llvm-svn: 78835
2009-08-12 20:51:55 +00:00
0c533d909a
now that these are in file-check format, we can merge them together
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into one bigger test (which runs faster)
llvm-svn: 78672
2009-08-11 15:54:17 +00:00
8f5c447bfa
Convert more Neon tests to use FileCheck.
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llvm-svn: 78648
2009-08-11 05:51:19 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
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the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
Sandeep Patel