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3 Commits

Author SHA1 Message Date
Sebastian Neubauer 3bc7ffdaab [AMDGPU] Use v3f32 type in image instructions 
This should lower the amount of used registers for gfx9.

I updated some of the changed tests with the update script because
changing them by hand is tedious.

Differential Revision: https://reviews.llvm.org/D73884
 2020-02-05 10:35:41 +01:00
Nicolai Hähnle ba8110161d AMDGPU/GFX10: Fix NSA reassign pass when operands are undef 
Summary:
Virtual registers that are undef have an empty LiveInterval at this
point, which means beginIndex() and endIndex() cannot be used. We
only need those indices to determine the range in which to scan for
affected other NSA instructions, and undef operands cannot contribute
to that range.

Reviewers: arsenm, rampitec, mareko

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73831
 2020-02-01 22:41:40 +01:00
Stanislav Mekhanoshin 692560dc98 [AMDGPU] gfx1010 MIMG implementation 
Differential Revision: https://reviews.llvm.org/D61339

llvm-svn: 359698
 2019-05-01 16:32:58 +00:00