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Author SHA1 Message Date
Artem Tamazov 135487767b [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. 
Another step for unification llvm assembler/disassembler with sp3.
Besides, CodeGen output is a bit improved, thus changes in CodeGen tests.
Assembler/Disassembler tests updated/added.

Differential Revision: http://reviews.llvm.org/D20796

llvm-svn: 271900
 2016-06-06 15:23:43 +00:00
Tom Stellard 46937ca4e7 [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler 
Historically, AMD internal sp3 assembler has flat_store* addr, data
format. To match existing code and to enable reuse, change LLVM
definitions to match.  Also update MC and CodeGen tests.

Differential Revision: http://reviews.llvm.org/D16927

Patch by: Nikolay Haustov

llvm-svn: 260694
 2016-02-12 17:57:54 +00:00
Matt Arsenault 9c47dd583a AMDGPU: Remove some old intrinsic uses from tests 
llvm-svn: 260493
 2016-02-11 06:02:01 +00:00
Matt Arsenault 33e3ecee0c AMDGPU: Reduce 64-bit SRAs 
llvm-svn: 258096
 2016-01-18 22:09:04 +00:00
Matt Arsenault 5e0bdb8b95 AMDGPU: Implement {{s|u}}int_to_fp i64 -> f32 
The old lowering for uint_to_fp failed opencl conformance.
It might be OK for fast math mode, but I'm not sure.

llvm-svn: 257393
 2016-01-11 22:01:48 +00:00