Commit Graph

90093 Commits

Author SHA1 Message Date
Sanjoy Das 12c91dc4c8 [ValueTracking] Use guards to prove non-nullness of a value
Reviewers: apilipenko, majnemer, reames

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D20044

llvm-svn: 269008
2016-05-10 02:35:44 +00:00
Sanjoy Das d47f42435a [BasicAA] Guard intrinsics don't write to memory
Summary:
The idea is very close to what we do for assume intrinsics: we mark the
guard intrinsics as writing to arbitrary memory to maintain control
dependence, but under the covers we teach AA that they do not mod any
particular memory location.

Reviewers: chandlerc, hfinkel, gbiv, reames

Subscribers: george.burgess.iv, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19575

llvm-svn: 269007
2016-05-10 02:35:41 +00:00
Matthias Braun 47cf918e20 LLVMTargetMachine: Add functions to create MIModuleInfo/MIFunction; NFC
Add convenience function to create MachineModuleInfo and
MachineFunctionAnalysis passes and add them to a pass manager.

Despite factoring out some shared code in
LiveIntervalTest/LLVMTargetMachine this will be used by my upcoming llc
change.

llvm-svn: 269002
2016-05-10 01:32:40 +00:00
Quentin Colombet ee5f36bd54 [X86][AVX512] Use the proper load/store for AVX512 registers.
When loading or storing AVX512 registers we were not using the AVX512
variant of the load and store for VR128 and VR256 like registers.
Thus, we ended up with the wrong encoding and actually were dropping the
high bits of the instruction. The result was that we load or store the
wrong register. The effect is visible only when we emit the object file
directly and disassemble it. Then, the output of the disassembler does
not match the assembly input.

This is related to llvm.org/PR27481.

llvm-svn: 269001
2016-05-10 01:09:14 +00:00
Sanjoy Das 0b6518d24e [SCEVExpander] Clang format expressions; NFC
The boolean expressions are somewhat hard to read otherwise.

llvm-svn: 268998
2016-05-10 00:32:31 +00:00
Sanjoy Das 2512d0c837 [SCEV] Use guards to prove predicates
We can use calls to @llvm.experimental.guard to prove predicates,
relying on the fact that in all locations domianted by a call to
@llvm.experimental.guard the predicate it is guarding is known to be
true.

llvm-svn: 268997
2016-05-10 00:31:49 +00:00
Justin Lebar 50deb6d028 Minor formatting fixes in LoopUnroll.cpp.
llvm-svn: 268995
2016-05-10 00:31:23 +00:00
Justin Lebar 87a174c9f9 [NVPTX] Change begin/end inline asm comments to "begin/end inline asm".
Previously it was just "// inline asm", which made it tricky to read
code with lots of inline assembly.

llvm-svn: 268994
2016-05-10 00:31:22 +00:00
Derek Schuff 138943fe25 [WebAssembly] Disable 128-bit shift libcalls
Currently the signature of the functions
i128(i128, i32) aka void(i32, i64, i64, i32) doesn't match the signature
of the call emitted by the default lowering, void(i32, i64, i64).

llvm-svn: 268991
2016-05-10 00:14:07 +00:00
Justin Bogner ffb273d21a SDAG: Stop relying on Select's return value in SystemZ's splitLargeImmediate. NFC
The call to Select on Upper here happens in an unusual order in order
to defeat the constant folding that getNode() does. Add a comment
explaining why we can't just move the Select to later to avoid a
Handle, and wrap the call to SelectCode in a handle so we don't need
its return value.

This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.

llvm-svn: 268990
2016-05-09 23:54:23 +00:00
Eugene Zelenko 417d4c508b Fix some Clang-tidy modernize-deprecated-headers and Include What You Use warnings; other minor fixes.
Differential revision: http://reviews.llvm.org/D20042

llvm-svn: 268989
2016-05-09 23:11:38 +00:00
Adam Nemet 0a77dfad95 [LV] Hint at the new loop distribution pragma in optimization remark
When we encounter unsafe memory dependencies, loop distribution could
help.

Even though, the diagnostics is in LAA, it's only currently emitted in
the vectorizer.

llvm-svn: 268987
2016-05-09 23:03:44 +00:00
Adam Nemet c6bbd80d59 [IndirectCallPromotion] Remove duplicate comment. NFC
llvm-svn: 268986
2016-05-09 23:03:06 +00:00
Quentin Colombet 739614839f [X86] Fix the AllRegs AVX calling convention.
We used to list registers that were not in the AVX space. In other
words, we were pushing registers that the ISA cannot encode
(YMM16-YMM31).

This is part of llvm.org/PR27481.

llvm-svn: 268983
2016-05-09 22:37:05 +00:00
Sanjay Patel 0f153424a9 [Inliner] don't assume that a Constant alloca size is a ConstantInt (PR27277)
Differential Revision: http://reviews.llvm.org/D20077

llvm-svn: 268980
2016-05-09 21:51:53 +00:00
Chad Rosier 58919cc6f8 Typo. NFC.
llvm-svn: 268975
2016-05-09 21:37:43 +00:00
Xinliang David Li dfa21c310d Cleanup followup of r268710 - [PM] port IR based PGO prof-gen pass to new pass manager
llvm-svn: 268974
2016-05-09 21:37:12 +00:00
Quentin Colombet b47b9b2de7 [X86] Strengthen the setting of inline asm constraints for fp regclasses.
This is similar to r268953, but for floating point and vector register
classes.

Explanations:
The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.

llvm-svn: 268973
2016-05-09 21:24:31 +00:00
Simon Pilgrim eec3a95f95 [X86][SSE] Improve cost model for i64 vector comparisons on pre-SSE42 targets
As discussed on PR24888, until SSE42 we don't have access to PCMPGTQ for v2i64 comparisons, but the cost models don't reflect this, resulting in over-optimistic vectorizaton.

This patch adds SSE2 'base level' costs that match what a typical target is capable of and only reduces the v2i64 costs at SSE42.

Technically SSE41 provides a PCMPEQQ v2i64 equality test, but as getCmpSelInstrCost doesn't give us a way to discriminate between comparison test types we can't easily make use of this, otherwise we could split the cost of integer equality and greater-than tests to give better costings of each.

Differential Revision: http://reviews.llvm.org/D20057

llvm-svn: 268972
2016-05-09 21:14:38 +00:00
Rong Xu a12f6d3c7b [PGO] Fix __llvm_profile_raw_version linkage in MACHO
IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to
overwrite the same symbol in profile run-time to distinguish IR profiles from
Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the
lack of COMDAT support.

But LinkOnceODR linkage might have .weak_def_can_be_hidden assembly directive,
while the weak variable in run-time has a .weak_definition directive. Linker
will not merge these two symbols even they have the same name. The end result
is IR profiles are not properly flagged in MACHO.

This patch changes the linkage for __llvm_profile_raw_version in each module to
LinkOnceAny so that it has same .weak_definition directive as in the run-time.

Differential Revision: http://reviews.llvm.org/D20078

llvm-svn: 268969
2016-05-09 21:03:06 +00:00
Kostya Serebryany ca9694ba2c [libFuzzer] add a test for libFuzzer+ubsan, extend the docs on using libFuzzer+ubsan
llvm-svn: 268968
2016-05-09 21:02:36 +00:00
Marcin Koscielnicki 60b3cbe095 [MSan] [AArch64] Fix vararg helper for >1 or non-int fixed arguments.
This fixes http://llvm.org/PR27646 on AArch64.

There are three issues here:

- The GR save area is 7 words in size, instead of 8.  This is not enough
  if none of the fixed arguments is passed in GRs (they're all floats or
  aggregates).
- The first argument is ignored (which counteracts the above if it's passed
  in GR).
- Like x86_64, fixed arguments landing in the overflow area are wrongly
  counted towards the overflow offset.

Differential Revision: http://reviews.llvm.org/D20023

llvm-svn: 268967
2016-05-09 20:57:36 +00:00
Adrian Prantl e36561855c Separate the Verifier into an analysis and a transformation pass and
allow the transformation to strip invalid debug info.

This patch separates the Verifier into an analysis and a transformation
pass, with the transformation pass optionally stripping malformed
debug info.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info. We want
to be able to make the verifier stricter without having to worry about
breaking bitcode compatibility with existing producers. For example, we
don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

http://reviews.llvm.org/D19988
rdar://problem/25818489

This reapplies r268937 without modifications.

llvm-svn: 268966
2016-05-09 19:57:29 +00:00
Adrian Prantl fe7a382453 Allow the LTO code generator to strip invalid debug info from the input.
This patch introduces a new option -lto-strip-invalid-debug-info, which
drops malformed debug info from the input.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info. We want
to be able to make the verifier stricter without having to worry about
breaking bitcode compatibility with existing producers. For example, we
don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

rdar://problem/25818489
http://reviews.llvm.org/D19987

This reapplies 268936 with a test case fix for Linux (-exported-symbol foo)

llvm-svn: 268965
2016-05-09 19:57:15 +00:00
Quentin Colombet 3126db6fd7 [X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.
The only 64-bit register in that register class is RIP and it will not
get spilled in the current ABIs.

llvm-svn: 268963
2016-05-09 19:50:30 +00:00
Chad Rosier 131a42ccdf [InstCombine] Fold icmp eq/ne (udiv i32 A, B), 0 -> icmp ugt/ule B, A.
Differential Revision: http://reviews.llvm.org/D20036

llvm-svn: 268960
2016-05-09 19:30:20 +00:00
Kostya Serebryany 61b07ac75b [libFuzzer] better document the -merge=1 flag
llvm-svn: 268957
2016-05-09 19:11:36 +00:00
Quentin Colombet 86098ab10b Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
This reapplies commit r268796, with a fix for the setting of the inline asm
constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the
regular processing of the GR operands (setting of the subregisters) happens.

Original commit log:
[X86] Add a new LOW32_ADDR_ACCESS_RBP register class.

ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
The new register class reflects those constraints when choosing a
register class for a address access.

llvm-svn: 268955
2016-05-09 19:01:46 +00:00
Quentin Colombet bb15ce3d1f [X86] Strengthen the setting of inline asm constraints.
The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.

llvm-svn: 268953
2016-05-09 19:01:35 +00:00
Nemanja Ivanovic 6e29baf7f5 [Power9] Add support for -mcpu=pwr9 in the back end
This patch corresponds to review:
http://reviews.llvm.org/D19683

Simply adds the bits for being able to specify -mcpu=pwr9 to the back end.

llvm-svn: 268950
2016-05-09 18:54:58 +00:00
Krzysztof Parzyszek 7c7bb538cb [Hexagon] Treat all conditional branches as predicted (not-taken by default)
llvm-svn: 268946
2016-05-09 18:22:07 +00:00
Zachary Turner 06c2b4be25 [pdb] Parse the module info stream for each module.
Differential Revision: http://reviews.llvm.org/D20026
Reviewed By: rnk

llvm-svn: 268942
2016-05-09 17:45:21 +00:00
Zachary Turner 9073ed6e5a Make TypeIterator generic so it can iterate symbols too.
Reviewed By: amccarth
Differential Revision: http://reviews.llvm.org/D20038

llvm-svn: 268941
2016-05-09 17:44:58 +00:00
Adrian Prantl 6d80100c6a Revert "Allow the LTO code generator to strip invalid debug info from the input."
This reverts commit 268936 while investigating buildbot breakage.

llvm-svn: 268940
2016-05-09 17:43:30 +00:00
Adrian Prantl 614d411a0d Revert "Separate the Verifier into an analysis and a transformation pass and"
This reverts commit 268937 while investigating build bot breakage.

llvm-svn: 268939
2016-05-09 17:43:24 +00:00
Daniel Sanders da43f0e76f [mips] Fix a partially initialized member variable that was introduced in r268896.
llvm-svn: 268938
2016-05-09 17:42:04 +00:00
Adrian Prantl ec45b437a7 Separate the Verifier into an analysis and a transformation pass and
allow the transformation to strip invalid debug info.

This patch separates the Verifier into an analysis and a transformation
pass, with the transformation pass optionally stripping malformed
debug info.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info. We want
to be able to make the verifier stricter without having to worry about
breaking bitcode compatibility with existing producers. For example, we
don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

http://reviews.llvm.org/D19988
rdar://problem/25818489

llvm-svn: 268937
2016-05-09 17:37:42 +00:00
Adrian Prantl 4a9292b127 Allow the LTO code generator to strip invalid debug info from the input.
This patch introduces a new option -lto-strip-invalid-debug-info, which
drops malformed debug info from the input.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info. We want
to be able to make the verifier stricter without having to worry about
breaking bitcode compatibility with existing producers. For example, we
don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

rdar://problem/25818489
http://reviews.llvm.org/D19987

llvm-svn: 268936
2016-05-09 17:37:33 +00:00
Sanjay Patel c7b91e65d8 [CGP] avoid crashing from weightlessness
It's possible that we have branch weights with 0 values.
In that case, don't try to create an impossible BranchProbability.

llvm-svn: 268935
2016-05-09 17:31:55 +00:00
Matt Arsenault 1af53a91c0 DivergenceAnalysis: Fix crash with no return blocks
The post dominator tree does not have a root node in this case.

llvm-svn: 268933
2016-05-09 16:57:08 +00:00
Sanjay Patel 91592568f9 [TargetLowering] make helper function for SetCC + and optimizations (NFC)
After looking at D19087 again, it occurred to me that we can do better. If we consolidate
the valueHasExactlyOneBitSet() transforms, we won't incur extra overhead from calling it a
2nd time, and we can shrink SimplifySetCC() a bit. No functional change intended.

Differential Revision: http://reviews.llvm.org/D20050

llvm-svn: 268932
2016-05-09 16:42:50 +00:00
Simon Pilgrim 0a81921cdb Fixed unused but set variable warning
llvm-svn: 268931
2016-05-09 16:42:23 +00:00
Matt Arsenault a949dc619c AMDGPU: Fold shift into cvt_f32_ubyteN
llvm-svn: 268930
2016-05-09 16:29:50 +00:00
Sanjay Patel 0fb9880bf5 fix spelling; NFC
llvm-svn: 268929
2016-05-09 16:07:45 +00:00
Daniel Sanders 108823bc35 [mips] Try to fix 'truncation from FindBestPredicateResult to bool' reported by MSVC
llvm-svn: 268928
2016-05-09 15:50:15 +00:00
Daniel Sanders cc9a2cf7ee [mips][ias] Attempt to fix 'not all control paths return a value' reported by MSVC.
llvm-svn: 268927
2016-05-09 15:37:52 +00:00
Joerg Sonnenberger 8ffe7ab7c2 Optimize a printf with a double procent to putchar.
llvm-svn: 268922
2016-05-09 14:36:16 +00:00
James Molloy 5c20e27b7f [VectorUtils] Query number of sign bits to allow more truncations
When deciding if a vector calculation can be done in a smaller bitwidth, use sign bit information from ValueTracking to add more information and allow more truncations.

llvm-svn: 268921
2016-05-09 14:32:30 +00:00
Daniel Sanders e473dc937f [mips][micromips] Make getPointerRegClass() result depend on the instruction.
Summary:
Previously, it returned the GPR16MMRegClass for all instructions which was
incorrect for instructions like lwsp/lwgp and unnecesarily restricted the
permitted registers for instructions like lw32.

This fixes quite a few of the -verify-machineinstrs errors reported in PR27458.
I've only added -verify-machineinstrs to one test in this change since I
understand there is a plan to enable the verifier by default.

Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19873

llvm-svn: 268918
2016-05-09 13:38:25 +00:00
Rafael Espindola 484983f453 Fix bug where temporary file would be left behind every time an archive was updated.
When updating an existing archive, llvm-ar opens the old archive into a
`MemoryBuffer`, does its thing, and writes the results to a temporary
file. That file is then renamed to the original archive filename, thus
replacing it with the updated contents. However, on Windows at least,
what would happen is that the `MemoryBuffer` for the old archive would
actually be an mmap'ed view of the file, so when it came time to do the
rename via Win32's `ReplaceFile`, it would succeed but would be unable
to fully replace the file since there would still be a handle open on
it; instead, the old version got renamed to a random temporary name and
left behind.

Patch by Cameron!

llvm-svn: 268916
2016-05-09 13:31:11 +00:00