unsigned overflow (e.g. "gep P, -1"), and while they can have
signed wrap in theoretical situations, modelling an AddRec as
not having signed wrap is going enough for any case we can
think of today. In the future if this isn't enough, we can
revisit this. Modeling them as having NUW isn't causing any
known problems either FWIW.
llvm-svn: 125410
The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.
llvm-svn: 125391
Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant
with the ARM Arch Manual which uses Rt for the destination register.
llvm-svn: 125390
is unqualified but its initialized is qualified.
This is for c only and fixes the imm. problem.
c++ is more involved and is wip.
// rdar://8979379
llvm-svn: 125386
This patch contains:
- making some of the existing comments more accurate in the presence
of virtual files/directories.
- renaming some private data members of FileManager to match their roles better.
- creating 'DirectorEntry's for the parent directories of virtual
files, such that we can tell whether two virtual files are from the
same directory. This is useful for injecting virtual files whose
directories don't exist in the real file system.
- minor clean-ups and adding comments for class
FileManager::UniqueDirContainer and FileManager::UniqueFileContainer.
- adding statistics on virtual files to FileManager::PrintStats().
- adding unit tests to verify the existing and new behavior of FileManager.
llvm-svn: 125384
Add new utility function, WriteBits32Unknown
Modify the LDM* instruction emulation functions to call WriteBits32Unknown.
Add missing overview comments to the LDM* instruction emulation functions.
Add code to emulate LDMDA Arm instruction.
llvm-svn: 125377
This
define float @foo(float %x, float %y) nounwind readnone {
entry:
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
ret float %0
}
Was compiled to:
vmov s0, r1
bic r0, r0, #-2147483648
vmov s1, r0
vcmpe.f32 s0, #0
vmrs apsr_nzcv, fpscr
it lt
vneglt.f32 s1, s1
vmov r0, s1
bx lr
This fails to copy the sign of -0.0f because it's lost during the float to int
conversion. Also, it's sub-optimal when the inputs are in GPR registers.
Now it uses integer and + or operations when it's profitable. And it's correct!
lsrs r1, r1, #31
bfi r0, r1, #31, #1
bx lr
rdar://8984306
llvm-svn: 125357
causing the deserialization of a large number of declarations when
writing the visible-updates record for the translation unit in C. This
takes us from:
*** AST File Statistics:
2 stat cache hits
6 stat cache misses
1/64463 source location entries read (0.001551%)
15606/16956 types read (92.038216%)
59266/89334 declarations read (66.342041%)
38952/61393 identifiers read (63.446976%)
0/7778 selectors read (0.000000%)
24192/34644 statements read (69.830276%)
388/8809 macros read (4.404586%)
2095/5189 lexical declcontexts read (40.373867%)
0/4587 visible declcontexts read (0.000000%)
0/7716 method pool entries read (0.000000%)
0 method pool misses
to
*** AST File Statistics:
2 stat cache hits
6 stat cache misses
1/64463 source location entries read (0.001551%)
26/16956 types read (0.153338%)
18/89334 declarations read (0.020149%)
145/61393 identifiers read (0.236183%)
0/7778 selectors read (0.000000%)
21/34644 statements read (0.060617%)
0/8809 macros read (0.000000%)
0/5189 lexical declcontexts read (0.000000%)
0/4587 visible declcontexts read (0.000000%)
0/7716 method pool entries read (0.000000%)
0 method pool misses
when generating a chained PCH for a header that #includes Cocoa.h
(from a PCH file) and adds one simple function declaration. The
generated PCH file is now only 9580 bytes (down from > 2MB).
llvm-svn: 125326
we would deserialize all of the macro definitions we knew about while
serializing the macro definitions at the end of the AST/PCH file. Even
though we skipped most of them (since they were unchanged), it's still
a performance problem.
Now, we do the standard AST/PCH chaining trick: watch what identifiers
are deserialized as macro names, and consider only those identifiers
(along with macro definitions that have been deserialized/written in
the source) when serializing the preprocessor state.
llvm-svn: 125324
Chris Lattner