Commit Graph

1570 Commits

Author SHA1 Message Date
Craig Topper d33ee1b960 [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt class. Implement them without memory allocation for multiword
This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation.

Differential Revision: https://reviews.llvm.org/D31565

llvm-svn: 299362
2017-04-03 16:34:59 +00:00
Krzysztof Parzyszek d04c9b999c [Hexagon] Remove unused variables
Found by PVS-Studio. Fixes llvm.org/PR31676.

llvm-svn: 299262
2017-03-31 21:03:59 +00:00
Krzysztof Parzyszek b326411fdc [Hexagon] Fix typo in HexagonEarlyIfCConv.cpp
Found by PVS-Studio. Fixes llvm.org/PR32480.

llvm-svn: 299258
2017-03-31 20:36:00 +00:00
Krzysztof Parzyszek 10fbac009d [Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognition
- Avoid explosive growth of the simplification queue by not queuing
  expressions that are alredy in it.
- Add an iteration counter and abort after a sufficiently large number
  of iterations (assuming that it's a symptom of an infinite loop).

llvm-svn: 298655
2017-03-23 23:01:22 +00:00
Krzysztof Parzyszek d033d1fd82 Recommit r298282 with fixes for memory allocation/deallocation
[Hexagon] Recognize polynomial-modulo loop idiom again

Regain the ability to recognize loops calculating polynomial modulo
operation. This ability has been lost due to some changes in the
preceding optimizations. Add code to preprocess the IR to a form
that the pattern matching code can recognize.

llvm-svn: 298400
2017-03-21 17:09:27 +00:00
Reid Kleckner b518054b87 Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.

Rename AttributeSetImpl to AttributeListImpl to follow suit.

It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.

Reviewers: sanjoy, javed.absar, chandlerc, pete

Reviewed By: pete

Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits

Differential Revision: https://reviews.llvm.org/D31102

llvm-svn: 298393
2017-03-21 16:57:19 +00:00
Vitaly Buka c12716e742 Revert "[Hexagon] Recognize polynomial-modulo loop idiom again"
Fix memory leaks on check-llvm tests detected by Asan.

This reverts commit r298282.

llvm-svn: 298329
2017-03-21 00:59:51 +00:00
Krzysztof Parzyszek 8490251de3 [Hexagon] Recognize polynomial-modulo loop idiom again
Regain the ability to recognize loops calculating polynomial modulo
operation. This ability has been lost due to some changes in the
preceding optimizations. Add code to preprocess the IR to a form
that the pattern matching code can recognize.

llvm-svn: 298282
2017-03-20 18:12:58 +00:00
Nirav Dave ac6081cb67 Make library calls sensitive to regparm module flag (Fixes PR3997).
Reviewers: mkuper, rnk

Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D27050

llvm-svn: 298179
2017-03-18 00:44:07 +00:00
Nirav Dave 6de2c77944 Capitalize ArgListEntry fields. NFC.
llvm-svn: 298178
2017-03-18 00:43:57 +00:00
Colin LeMahieu ddebad956e [Hexagon] Updating inline saturate lanes for v62 version.
llvm-svn: 297920
2017-03-16 00:35:28 +00:00
Krzysztof Parzyszek 9416abbc4a [Hexagon] Fix a condition in HexagonEarlyIfConv.cpp
This fixes llvm.org/PR32265.

llvm-svn: 297745
2017-03-14 15:21:33 +00:00
Krzysztof Parzyszek 0e7b1f83b7 [RDF] Remove the map of reaching defs from copy propagation
Use Liveness::getNearestAliasedRef to find the reaching def instead.

llvm-svn: 297526
2017-03-10 22:44:24 +00:00
Krzysztof Parzyszek 0b8f184d12 [RDF] Implement Liveness::getNearestAliasedRef(Reg, Inst)
This function will find the closest ref node aliased to Reg that is
in an instruction preceding Inst. This could be used to identify the
hypothetical reaching def of Reg, if Reg was a member of Inst.

llvm-svn: 297524
2017-03-10 22:42:17 +00:00
Krzysztof Parzyszek 544210304f [Hexagon] Fixes to the bitsplit generation
- Fix the insertion point, which occasionally could have been incorrect.
- Avoid creating multiple bitsplits with the same operands, if an old one
  could be reused.

llvm-svn: 297414
2017-03-09 22:02:14 +00:00
Krzysztof Parzyszek fe267a37f4 [Hexagon] Refactor the DAG preprocessing code, NFC
Extract individual transformations into their own functions.

llvm-svn: 297401
2017-03-09 19:14:23 +00:00
Krzysztof Parzyszek 7a0981aa38 [Hexagon] Add -mhvx option to the Hexagon backend
llvm-svn: 297393
2017-03-09 17:05:11 +00:00
Krzysztof Parzyszek 78c4fcf12e [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
(op ... (zext i1 c) ...) -> (select c (op ... 1 ...),
                                      (op ... 0 ...))

llvm-svn: 297391
2017-03-09 16:29:30 +00:00
Krzysztof Parzyszek 1b7197e690 [Hexagon] Use correct offset when extracting from the high word
When extracting a bitfield from the high register in a register pair,
the final offset should be relative to the high register (for 32-bit
extracts).

llvm-svn: 297288
2017-03-08 15:46:28 +00:00
Krzysztof Parzyszek 434d50a796 [Hexagon] Check for presence before looking registers up in bit tracker
llvm-svn: 297240
2017-03-07 23:12:04 +00:00
Krzysztof Parzyszek 8e4d2e0512 [Hexagon] Generate bitsplit instruction
llvm-svn: 297239
2017-03-07 23:08:35 +00:00
Krzysztof Parzyszek 3cceffb752 [Hexagon] Do not insert instructions before PHI nodes
llvm-svn: 297141
2017-03-07 14:20:19 +00:00
Krzysztof Parzyszek 8a4c601abc [Hexagon] Early-if-convert branches that may exit the loop
Merge the tail block into the loop in cases where the main loop body
exits early, subject to profitability constraints. This will coalesce
the loop body into fewer blocks.

For example:
  loop:                           loop:
    // loop body                      // loop body
    if (...) jump exit      -->       // more body
  more:                               if (...) jump exit
    // more body                      jump loop
    jump loop

llvm-svn: 297033
2017-03-06 17:24:04 +00:00
Krzysztof Parzyszek e16ce15687 [Hexagon] Mark dead defs as <dead> in expand-condsets
The code in updateDeadFlags removed unnecessary <dead> flags, but there
can be cases where such a flag is not set, and yet a register has become
dead. For example, if a mux with identical inputs is replaced with a COPY,
the predicate register may no longer be used after that.

llvm-svn: 297032
2017-03-06 17:09:06 +00:00
Krzysztof Parzyszek 143158b72e [Hexagon] Pick a dot-old instruction that matches the architecture
llvm-svn: 297031
2017-03-06 17:03:16 +00:00
Krzysztof Parzyszek cc31871dc4 Make TargetInstrInfo::isPredicable take a const reference, NFC
llvm-svn: 296901
2017-03-03 18:30:54 +00:00
Krzysztof Parzyszek e720feb1c6 [Hexagon] Pick the right branch opcode depending on branch probabilities
Specifically, pick the opcode with the correct branch prediction, i.e.
jump:t or jump:nt.

llvm-svn: 296821
2017-03-02 21:49:49 +00:00
Krzysztof Parzyszek 056c945a5d [Hexagon] Skip blocks that define vector predicate registers in early-if
llvm-svn: 296777
2017-03-02 18:10:59 +00:00
Krzysztof Parzyszek fcbb7d10fe [Hexagon] Properly handle 'q' constraint in 128-byte vector mode
llvm-svn: 296772
2017-03-02 17:50:24 +00:00
Krzysztof Parzyszek 8144f37dd8 [RDF] Replace {} with explicit constructor, since not all compilers like it
llvm-svn: 296666
2017-03-01 19:59:28 +00:00
Krzysztof Parzyszek ebabd99adb [RDF] Add recursion limit to getAllReachingDefsRec
For large programs this function can take significant amounts of time.
Let it abort gracefully when the program is too complex.

llvm-svn: 296662
2017-03-01 19:30:42 +00:00
Krzysztof Parzyszek 8f23dd6d68 [Hexagon] Fix lowering of formal arguments of type i1
On Hexagon, values of type i1 are passed in registers of type i32,
even though i1 is not a legal value for these registers. This is a
special case and needs special handling to maintain consistency of
the lowering information.

This fixes PR32089.

llvm-svn: 296645
2017-03-01 17:30:10 +00:00
Krzysztof Parzyszek 33fd0bbbe8 [Hexagon] Generate extract instructions more aggressively
llvm-svn: 296537
2017-02-28 23:27:33 +00:00
Krzysztof Parzyszek f208681731 [Hexagon] Fix instruction selection for sign-extending i1 to i64
llvm-svn: 296532
2017-02-28 22:37:01 +00:00
Krzysztof Parzyszek e9be35596e [Hexagon] Defs and clobbers can overlap
llvm-svn: 296365
2017-02-27 18:03:35 +00:00
Krzysztof Parzyszek 0d67b10a3c [Hexagon] Undo shift folding where it could simplify addressing mode
For example, avoid (single shift):
  r0 = and(##536870908,lsr(r0,#3))
  r0 = memw(r1+r0<<#0)

in favor of (two shifts):
  r0 = lsr(r0,#5)
  r0 = memw(r1+r0<<#2)

llvm-svn: 296196
2017-02-24 23:34:24 +00:00
Krzysztof Parzyszek be5028aed3 [Hexagon] Prettify code in HexagonDAGToDAGISel::Select
llvm-svn: 296187
2017-02-24 23:00:40 +00:00
Krzysztof Parzyszek 128e191eac [Hexagon] Handle saturations in Hexagon bit tracker
llvm-svn: 296026
2017-02-23 22:11:52 +00:00
Krzysztof Parzyszek 998e49e5c8 [Hexagon] Allow setting register in BitVal without storing into map
In the bit tracker, references to other bit values in which the register
is 0 are prohibited. This means that generating self-referential register
cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order
to get a self-referential cell, it had to be stored into a map and then
reloaded from it. To avoid this step, add a function that will set the
register to a given value without going through the map.

llvm-svn: 296025
2017-02-23 22:08:50 +00:00
Krzysztof Parzyszek 2cfc7a48de [Hexagon] Avoid IMPLICIT_DEFs as new-value producers
llvm-svn: 295997
2017-02-23 17:47:34 +00:00
Krzysztof Parzyszek af5ff65d67 [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
llvm-svn: 295981
2017-02-23 15:02:09 +00:00
Krzysztof Parzyszek ab57c2bad3 [Hexagon] Implement @llvm.readcyclecounter()
llvm-svn: 295892
2017-02-22 22:28:47 +00:00
Krzysztof Parzyszek 3596a81c69 [RDF] Support for partial structural aliases in RegisterAggr
llvm-svn: 295883
2017-02-22 21:42:15 +00:00
Krzysztof Parzyszek 65971d97b0 [Hexagon] Add intrinsics for masked vector stores
Patch by Harsha Jagasia.

llvm-svn: 295879
2017-02-22 21:23:09 +00:00
Krzysztof Parzyszek ace1b89060 [RDF] Skip undef uses when calculating kill flags
llvm-svn: 295856
2017-02-22 18:29:16 +00:00
Krzysztof Parzyszek ba36b92bef [RDF] Only access block live-ins when tracking liveness
llvm-svn: 295855
2017-02-22 18:27:36 +00:00
Simon Pilgrim ee6ef4d6dd Fix 'variable set but not used' warning when assertions are disabled.
llvm-svn: 295585
2017-02-19 00:03:46 +00:00
Krzysztof Parzyszek 1aaf41af54 [Hexagon] Start using regmasks on calls
Reapply r295371 with a fix for the Windows bot failures.

llvm-svn: 295504
2017-02-17 22:14:51 +00:00
Rafael Espindola 6eab4044b9 Revert "[Hexagon] Start using regmasks on calls"
This reverts commit r295371.

It broke windows bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio

llvm-svn: 295402
2017-02-17 02:08:58 +00:00
David Blaikie fc4857f80b Fix -Wunused-lambda-capture by removing some unused lambda captures
llvm-svn: 295373
2017-02-16 20:55:48 +00:00