Commit Graph

6714 Commits

Author SHA1 Message Date
Justin Bogner d3eccb54b1 update_mir_test_checks: Drop support for vreg block checks
Since vregs are printed in the instruction stream now, checking the
vreg block is always redundant. Remove the temporary feature that
allowed us to do that.

This reverts r316134

llvm-svn: 326284
2018-02-28 00:44:46 +00:00
Ilya Biryukov d9d9bf8d13 Revert r326092: [gtest] Add PrintTo overload for StringRef.
It seems to break the following buildbot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/24729

Will resubmit after investigating and fixing it.

llvm-svn: 326096
2018-02-26 15:54:59 +00:00
Ilya Biryukov ab6554fefb [gtest] Add PrintTo overload for StringRef.
Summary:
It was printed using code for generic containers before, resulting in
unreadable output.

Reviewers: sammccall, labath

Reviewed By: sammccall, labath

Subscribers: labath, zturner, llvm-commits

Differential Revision: https://reviews.llvm.org/D43330

llvm-svn: 326092
2018-02-26 15:19:26 +00:00
Benjamin Kramer b941ababce Shrink various scheduling tables by using narrower types.
16 bits ought to be enough for everyone. This shrinks clang by ~1MB.

llvm-svn: 325941
2018-02-23 19:32:56 +00:00
Geoff Berry f8bf2ec0a8 [MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers.  This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.

Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.

Clear the IsRenamable bit when changing an operand's register value.

Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.

Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.

Reviewers: qcolombet, MatzeB

Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D43042

llvm-svn: 325931
2018-02-23 18:25:08 +00:00
Pavel Labath 3b17b84b9c Resubmit r325107 (case folding DJB hash)
The issue was that the has function was generating different results depending
on the signedness of char on the host platform. This commit fixes the issue by
explicitly using an unsigned char type to prevent sign extension and
adds some extra tests.

The original commit message was:

This patch implements a variant of the DJB hash function which folds the
input according to the algorithm in the Dwarf 5 specification (Section
6.1.1.4.5), which in turn references the Unicode Standard (Section 5.18,
"Case Mappings").

To achieve this, I have added a llvm::sys::unicode::foldCharSimple
function, which performs this mapping. The implementation of this
function was generated from the CaseMatching.txt file from the Unicode
spec using a python script (which is also included in this patch). The
script tries to optimize the function by coalescing adjecant mappings
with the same shift and stride (terms I made up). Theoretically, it
could be made a bit smarter and merge adjecant blocks that were
interrupted by only one or two characters with exceptional mapping, but
this would save only a couple of branches, while it would greatly
complicate the implementation, so I deemed it was not worth it.

Since we assume that the vast majority of the input characters will be
US-ASCII, the folding hash function has a fast-path for handling these,
and only whips out the full decode+fold+encode logic if we encounter a
character outside of this range. It might be possible to implement the
folding directly on utf8 sequences, but this would also bring a lot of
complexity for the few cases where we will actually need to process
non-ascii characters.

Reviewers: JDevlieghere, aprantl, probinson, dblaikie

Subscribers: mgorny, hintonda, echristo, clayborg, vleschuk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42740

llvm-svn: 325732
2018-02-21 22:36:31 +00:00
Mikhail Maltsev 581a7f0bef [vim] Recognize more FileCheck comments
Summary:
Currently vim syntax highlighting recognizes 'CHECK:' as a special
comment, but not CHECK-DAG, CHECK-NOT and other CHECKs. This patch
adds rules for these comments.

Reviewers: chandlerc, compnerd, rogfer01

Reviewed By: rogfer01

Subscribers: rogfer01, llvm-commits

Differential Revision: https://reviews.llvm.org/D43289

llvm-svn: 325599
2018-02-20 17:27:44 +00:00
Simon Pilgrim e4d40f9b7d Fix signed/unsigned comparison warning in AsmGenMatcher generated code. NFCI.
llvm-svn: 325428
2018-02-17 12:29:47 +00:00
Rui Ueyama 7c9ad29304 Remove "--full-shutdown" and instead use an environment variable LLD_IN_TEST.
We are running lld tests with "--full-shutdown" option because we don't
want to call _exit() in lld if it is running tests. Regular shutdown
is needed for leak sanitizer.

This patch changes the way how we tell lld that it is running tests.
Now "--full-shutdown" is removed, and LLD_IN_TEST environment variable
is used instead.

This patch enables full shutdown on all ports, e.g. ELF, COFF and wasm.
Previously, we enabled it only for ELF.

Differential Revision: https://reviews.llvm.org/D43410

llvm-svn: 325413
2018-02-16 23:41:48 +00:00
Aditya Nandakumar b63e763847 [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG
This patch changes GlobalISelEmitter to rank patterns similar to how the
DAG does it (ie it computes a score for a pattern and adds the added
complexity to it).
This is so that the decision tree for GISelSelector remains compatible
with that of SelectionDAG.

https://reviews.llvm.org/D43270

llvm-svn: 325401
2018-02-16 22:37:15 +00:00
Rui Ueyama 14ee1140c1 Make sure we invoke ld64.lld and ld-wasm in the build directory.
llvm-svn: 325397
2018-02-16 22:19:38 +00:00
Rafael Auler de9ad4ba84 [X86][3DNOW] Teach decoder about AMD 3DNow! instrs
Summary:
This patch makes the decoder understand old AMD 3DNow!
instructions that have never been properly supported in the X86
disassembler, despite being supported in other subsystems. Hopefully
this should make the X86 decoder more complete with respect to binaries
containing legacy code.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits, maksfb, bruno

Differential Revision: https://reviews.llvm.org/D43311

llvm-svn: 325295
2018-02-15 21:20:31 +00:00
Pavel Labath 918f60056a Revert r325107 (case folding DJB hash) and subsequent build fix
The "knownValuesUnicode" test in the patch fails on ppc64 and arm64
bots. Reverting while I investigate.

llvm-svn: 325115
2018-02-14 11:06:39 +00:00
Pavel Labath f1440978a1 Implement a case-folding version of DJB hash
Summary:
This patch implements a variant of the DJB hash function which folds the
input according to the algorithm in the Dwarf 5 specification (Section
6.1.1.4.5), which in turn references the Unicode Standard (Section 5.18,
"Case Mappings").

To achieve this, I have added a llvm::sys::unicode::foldCharSimple
function, which performs this mapping. The implementation of this
function was generated from the CaseMatching.txt file from the Unicode
spec using a python script (which is also included in this patch). The
script tries to optimize the function by coalescing adjecant mappings
with the same shift and stride (terms I made up). Theoretically, it
could be made a bit smarter and merge adjecant blocks that were
interrupted by only one or two characters with exceptional mapping, but
this would save only a couple of branches, while it would greatly
complicate the implementation, so I deemed it was not worth it.

Since we assume that the vast majority of the input characters will be
US-ASCII, the folding hash function has a fast-path for handling these,
and only whips out the full decode+fold+encode logic if we encounter a
character outside of this range. It might be possible to implement the
folding directly on utf8 sequences, but this would also bring a lot of
complexity for the few cases where we will actually need to process
non-ascii characters.

Reviewers: JDevlieghere, aprantl, probinson, dblaikie

Subscribers: mgorny, hintonda, echristo, clayborg, vleschuk, llvm-commits

Differential Revision: https://reviews.llvm.org/D42740

llvm-svn: 325107
2018-02-14 10:05:09 +00:00
Craig Topper df99baa4df [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.
Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

llvm-svn: 324985
2018-02-13 04:19:26 +00:00
Sam McCall 2d8242d60d [gtest] Support raw_ostream printing functions more comprehensively.
Summary:
These are functions like operator<<(raw_ostream&, Foo).

Previously these were only supported for messages. In the assertion
  EXPECT_EQ(A, B) << C;
the local modifications would explicitly try to use raw_ostream printing for C.
However A and B would look for a std::ostream printing function, and often fall
back to gtest's default "168 byte object <00 01 FE 42 ...>".

This patch pulls out the raw_ostream support into a new header under `custom/`.

I changed the mechanism: instead of a convertible stream, we wrap the printed
value in a proxy object to allow it to be sent to a std::ostream.
I think the new way is clearer.

I also changed the policy: we prefer raw_ostream printers over std::ostream
ones. This is because the fallback printers are defined using std::ostream,
while all the raw_ostream printers should be "good".

Reviewers: ilya-biryukov, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43091

llvm-svn: 324876
2018-02-12 10:20:09 +00:00
Fangrui Song 4f0f426d1f [utils] Refactor utils/update_{,llc_}test_checks.py to share more code
Summary:
This revision refactors 1. parser 2. CHECK line adder of utils/update_{,llc_}test_checks.py
so that thir functionality can be re-used by other utility scripts (e.g.  D42712)

Reviewers: asb, craig.topper, RKSimon, echristo

Subscribers: llvm-commits, spatel

Differential Revision: https://reviews.llvm.org/D42805

llvm-svn: 324803
2018-02-10 05:01:33 +00:00
Clement Courbet 873aa11dd9 [TargetSchedule] Fix r324582.
Increment was using the wrong NumUnits (the one from the ProcResGroup
and not the subunit).

llvm-svn: 324727
2018-02-09 10:28:46 +00:00
Victor Leschuk 33b9fa7caa [lit] Pass CLANG env var to testing configuration
Allow CLANG environment variable be copied into the testing configuration
and proper support testing with a custom path to the clang executable.

Signed-off-by: Vladimir Vereschaka <vvereschaka@accesssoftek.com>
llvm-svn: 324706
2018-02-09 05:28:38 +00:00
David Blaikie e6503d87da Fix missing field initializer warning in TableGen SubtargetEmitter
llvm-svn: 324643
2018-02-08 19:57:05 +00:00
Clement Courbet 39911e2ee6 [TargetSchedule] Expose sub-units of a ProcResGroup in MCProcResourceDesc.
Summary:
Right now using a ProcResource automatically counts as usage of all
super ProcResGroups. All this is done during codegen, so there is no
way for schedulers to get this information at runtime.

This adds the information of which individual ProcRes units are
contained in a ProcResGroup in MCProcResourceDesc.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43023

llvm-svn: 324582
2018-02-08 08:46:48 +00:00
Clement Courbet eb4f5d2890 [CodeGenSchedule][NFC] Always emit ProcResourceUnits.
Summary:
Right now only the ProcResourceUnits that are directly referenced by
instructions are emitted. This change emits all of them, so that
analysis passes can use the information.
This has no functional impact. It typically adds a few entries (e.g. 4
for X86/haswell) to the generated ProcRes table.

Reviewers: gchatelet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42903

llvm-svn: 324228
2018-02-05 12:23:51 +00:00
Sander de Smalen 5b691a10c0 [TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases
Summary:
This is a bit of a reimplementation the work done in
https://reviews.llvm.org/D41446, since that patch only really works for
tied operands of instructions, not aliases.

Instead of checking the constraints based on the matched instruction's opcode,
this patch uses the match-info's convert function to check the operand
constraints for that specific instruction/alias.
This is based on the matched operands for the instruction, not the
resulting opcode of the MCInst.

This patch adds the following enum/table to the *GenAsmMatcher.inc file:
  enum {
    Tie0_1_1,
    Tie0_1_2,
    Tie0_1_5,
    ...
  };

  const char TiedAsmOperandTable[][3] = {
    /* Tie0_1_1 */ { 0, 1, 1 },
    /* Tie0_1_2 */ { 0, 1, 2 },
    /* Tie0_1_5 */ { 0, 1, 5 },
    ...
  };

And it is referenced directly in the ConversionTable, like this:
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
  ...
  { CVT_95_addRegOperands, 1,
    CVT_95_addRegOperands, 2,
    CVT_Tied, Tie0_1_5,
    CVT_95_addRegOperands, 6, CVT_Done },
  ...


The Tie0_1_5 (and corresponding table) encodes that:
* Result operand 0 is the operand to copy (which is e.g. done when
  building up the operands to the MCInst in convertToMCInst())
* Asm operands 1 and 5 should be the same operands (which is checked
  in checkAsmTiedOperandConstraints()).

Reviewers: olista01, rengolin, fhahn, craig.topper, echristo, apazos, dsanders

Reviewed By: olista01

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42293

llvm-svn: 324196
2018-02-04 16:24:17 +00:00
Fangrui Song 3823fc46f5 Make utils/UpdateTestChecks/common.py Python 2/3 compatible and fix print statements.
Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42674

llvm-svn: 324104
2018-02-02 16:41:07 +00:00
Fangrui Song ee4e2e718d [utils] De-duplicate utils/update_{llc_,}test_checks.py
Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42654

llvm-svn: 323718
2018-01-30 00:40:05 +00:00
Rafael Espindola 93955d0d34 Fix some regular expressions in llvm-mode.el.
In some cases it was using "\" unnecessarily.  In another case it
needed an additional "\" to properly indicate a numbered sub-match.

Make comment-start buffer-local in llvm-mode.el

llvm-mode was setting comment-start globally.  However, it is better
to only set it locally in the current buffer.

Don't use purecopy in llvm-mode.el

There's no reason to use purecopy in llvm-mode.el.
purecopy is only needed for files that are dumped in emacs.

Add a version header to llvm-mode.el

Adding a version header to llvm-mode.el allows it to be installed by
the Emacs package manager.  There are not many requirements on the
version number; however it is useful to users to bump it when
something significant changes.  Here I've chosen just to start at 1.0.

Patch by Tom Tromey!

llvm-svn: 323705
2018-01-29 22:56:41 +00:00
Daniel Sanders 08464524c3 [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern
Summary:
Apparently, we missed on constraining register classes of VReg-operands of all the instructions
built from a destination pattern but the root (top-level) one. The issue exposed itself
while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped
into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained,
while nested VTOSIZS (or rather its destination virtual register to be exact) does not.

Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI.

https://bugs.llvm.org/show_bug.cgi?id=35965
rdar://problem/36886530

Patch by Roman Tereshin

Reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan

Reviewed By: dsanders, qcolombet, rovka

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42565

llvm-svn: 323692
2018-01-29 21:09:12 +00:00
Hiroshi Inoue c8e9245816 [NFC] fix trivial typos in comments and documents
"to to" -> "to"

llvm-svn: 323628
2018-01-29 05:17:03 +00:00
Justin Bogner 5db11e3181 update_mir_test_checks: Accept "." in function names
llvm-svn: 323573
2018-01-26 22:56:31 +00:00
Clement Courbet 3c299e1b71 [TableGen][NFC]Remove dead variable.
llvm-svn: 323525
2018-01-26 13:21:43 +00:00
Hans Wennborg f85c4960ef Update build_llvm_package.bat
I moved to a new machine and had to adjust a few things:

- Use %USERNAME% instead of %USER% (not sure why %USER% didn't work anymore)
- Update paths for using Python 3.6 instead of 3.5
- Skip building OpenMP which seems broken on Windows
- Work around new vsdevcmd.bat changing paths:
  https://developercommunity.visualstudio.com/content/problem/26780/vsdevcmdbat-changes-the-current-working-directory.html
- Build stage-0 compiler with MinSizeRel to work around VS 2017 bug:
  https://developercommunity.visualstudio.com/content/problem/139043/miscompile-in-trivial-c-program-with-155-preview-2.html

llvm-svn: 323427
2018-01-25 14:43:10 +00:00
Volkan Keles 4f3fa79842 [GlobalISel][TableGen] Fix the statistics for emitted patters
Collected statistics for the number of patterns emitted can be
incorrect because rules can be grouped if OptimizeMatchTable
is enabled. Increase the counter in RuleMatcher::emit(...)
to avoid that.

llvm-svn: 323391
2018-01-25 00:18:52 +00:00
Benjamin Kramer 4890a71f02 [TableGen] Add a way of getting the number of generic opcodes without including modular CodeGen headers.
This is a bit of a hack, but removes a cycle that broke modular builds
of LLVM. Of course the cycle is still there in form of a dependency
on the .def file.

llvm-svn: 323383
2018-01-24 22:35:11 +00:00
Malcolm Parsons 21e545d08d Fix typos of occurred and occurrence
llvm-svn: 323318
2018-01-24 10:33:39 +00:00
Hiroshi Inoue 501931b117 [NFC] fix trivial typos in comments
"the the" -> "the"

llvm-svn: 323302
2018-01-24 05:04:35 +00:00
Benjamin Kramer cbce2f02e9 [TableGen] Optimize the regex search.
llvm::Regex is still the slowest regex engine on earth, running it over
all instructions on X86 takes a while. Extract a prefix and use a binary
search to reduce the search space before we resort to regex matching.

There are a couple of caveats here:
- The generic opcodes are outside of the sorted enum. They're handled in an extra loop.
- If there's a top-level bar we can't use the prefix trick.
- We bail on top-level ?. This could be handled, but it's rare.

This brings the time to generate X86GenInstrInfo.inc from 21s to 4.7s on
my machine.

llvm-svn: 323277
2018-01-23 23:05:04 +00:00
Volkan Keles 1b55f1f804 Add a utility to reduce GlobalISel tests
Summary: This patch adds a script to reduce GlobalISel failures using bugpoint.

Reviewers: bogner

Reviewed By: bogner

Subscribers: MatzeB, qcolombet, rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41876

llvm-svn: 323248
2018-01-23 19:47:10 +00:00
Justin Bogner eaae305a09 update_mir_test_checks: Improve the check for LLVM IR in MIR files
The LLVM IR section of a MIR document can start with "--- |" rather
than just "---", because "|" is a sigil for a freeform document in
YAML. We need to handle this so that we don't try to add check lines
to the LLVM IR functions in a MIR file.

llvm-svn: 323178
2018-01-23 06:39:04 +00:00
Ilya Biryukov cc5e82b2f7 [Dockerfiles] Use a newer version of ninja when building inside debian8.
Summary:
The debian8 repos have an old version of ninja that seems to sometimes crash
when building llvm.

Reviewers: ioeric, mehdi_amini

Reviewed By: ioeric

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42304

llvm-svn: 323134
2018-01-22 17:19:41 +00:00
Dimitry Andric aad72b77c6 Follow-up to rL322875 by initializing the do_libcxxabi variable properly.
llvm-svn: 322879
2018-01-18 19:30:30 +00:00
Dimitry Andric d05541f7d6 Add a -no-libcxxabi option to the test-release.sh script.
On FreeBSD, it is currently not possible to build libcxxabi and link
against it, so we have been building releases with -no-libs for quite
some time.

However, libcxx and libunwind should build without problems, so provide
an option to skip just libcxxabi.

llvm-svn: 322875
2018-01-18 18:39:13 +00:00
Daniel Sanders 12e6e709e9 [globalisel][tablegen] Honour priority order within nested instructions.
It appears that we haven't been prioritizing rules that contain nested
instructions properly. InstructionOperandMatcher didn't override
isHigherPriorityThan so it never compared the instructions/operands/predicates
inside nested instructions.

Fixes PR35926. Thanks to Diana Picus for the bug report.

llvm-svn: 322754
2018-01-17 20:34:29 +00:00
Fangrui Song c4526fc5af [utils] Make .cfi_startproc optional for powerpc
Summary: llc sometimes may not emit .cfi_startproc which makes func_dict to have less entries.

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D42144

llvm-svn: 322725
2018-01-17 18:48:50 +00:00
Volkan Keles f7f2568613 [GlobalISel][TableGen] Add support for SDNodeXForm
Summary:
This patch adds CustomRenderer which renders the matched
operands to the specified instruction.

Targets can enable the matching of SDNodeXForm by adding
a definition that inherits from GICustomOperandRenderer and
GISDNodeXFormEquiv as follows.

def gi_imm8 : GICustomOperandRenderer<"renderImm8”>,
                       GISDNodeXFormEquiv<imm8_xform>;

Custom renderer functions should be of the form:
void render(MachineInstrBuilder &MIB, const MachineInstr &I);

Reviewers: dsanders, ab, rovka

Reviewed By: dsanders

Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet

Differential Revision: https://reviews.llvm.org/D42012

llvm-svn: 322582
2018-01-16 18:44:05 +00:00
George Rimar 83e63d96a9 [FileCheck] - Fix possible buffer out of bounds access when parsing --check-prefix.
FileCheck tool crashes when trying to parse --check-prefix argument if there is no any
data after it.

For example test like following would crash if there are no symbols and no EOL mark after `boom`:

# REQUIRES: x86
# RUN: <skipped few lines>
# RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom

Patch fixes the issue.

Differential revision: https://reviews.llvm.org/D42057

llvm-svn: 322536
2018-01-16 08:09:24 +00:00
Craig Topper 7a0c601f95 [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90.

This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class.

llvm-svn: 322532
2018-01-16 06:07:16 +00:00
Sander de Smalen 886510f350 [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands
Summary:
This extends TableGen's AsmMatcherEmitter with code that generates
a table with tied-operand constraints. The constraints are checked
when parsing the instruction. If an operand is not equal to its tied operand,
the assembler will give an error.

Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.

Reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo

Reviewed By: fhahn

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D41446

llvm-svn: 322166
2018-01-10 10:10:56 +00:00
Max Moroz 975eacada5 [lit] Implement "-r" option for builtin "diff" command + a test using that.
Summary:
That would allow to recursively compare directories in tests using
"diff -r" on Windows in a similar way as it can be done on Linux or Mac.

Reviewers: zturner, morehouse, vsk

Reviewed By: zturner

Subscribers: kcc, llvm-commits

Differential Revision: https://reviews.llvm.org/D41776

llvm-svn: 322102
2018-01-09 18:23:34 +00:00
Aleksandar Beserminji f02ad15ff1 [mips] Improve diagnostics for instruction mapping
This patch improves diagnostic for case when mapped instruction 
does not contain a field listed under RowFields.

Differential Revision: https://reviews.llvm.org/D41778

llvm-svn: 322004
2018-01-08 16:25:40 +00:00
Craig Topper 85657d59a9 [X86] Don't put any EVEX_B instructions in the tablegen generated load folding tables.
EVEX_B means different things for memory and register forms. The instructions should not be considered equivalent.

llvm-svn: 321954
2018-01-07 06:24:28 +00:00
Craig Topper ad89541ae9 [TableGen] Make the ambiguous match debug messages from the AsmMatcherEmitter slightly more useful.
Don't report ambiguous matches on different variants. Print the variant number in the output.

llvm-svn: 321938
2018-01-06 19:20:32 +00:00
Matt Arsenault 05d8f16aa4 Fix missing release metabug in merge-request.sh
llvm-svn: 321753
2018-01-03 18:51:22 +00:00
Tom Stellard d703b198f2 [lit] Bump version number
llvm-svn: 321735
2018-01-03 16:35:51 +00:00
Hans Wennborg 71525f706b The trunk version is now 7.0.0svn
llvm-svn: 321712
2018-01-03 14:52:54 +00:00
Hal Finkel 8b4bdfdbc4 [TableGen] Add support of Intrinsics with multiple returns
This change deals with intrinsics with multiple outputs, for example load
instrinsic with address updated.

DAG selection for Instrinsics could be done either through source code or
tablegen. Handling all intrinsics in source code would introduce a huge chunk
of repetitive code if we have a large number of intrinsic that return multiple
values (see NVPTX as an example). While intrinsic class in tablegen supports
multiple outputs, tablegen only supports Intrinsics with zero or one output on
TreePattern. This appears to be a simple bug in tablegen that is fixed by this
change.

For Intrinsics defined as:

  def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>;

Instruction will be defined as:

  def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>;

Patch by Wenbo Sun, thanks!

Differential Revision: https://reviews.llvm.org/D32888

llvm-svn: 321704
2018-01-03 11:35:09 +00:00
Benjamin Kramer 3a13ed60ba Avoid int to string conversion in Twine or raw_ostream contexts.
Some output changes from uppercase hex to lowercase hex, no other functionality change intended.

llvm-svn: 321526
2017-12-28 16:58:54 +00:00
Walter Lee b074f1428f [git-llvm] Handle files ignored by svn correctly
Summary: Correctly handle files ignored by svn (such as .o files,
which are ignored by default) by adding "--no-ignore" flag to "svn
status" and "svn add".

Differential Revision: https://reviews.llvm.org/D41404

llvm-svn: 321388
2017-12-22 21:19:13 +00:00
Krzysztof Parzyszek 2e0f7bd0fe [TableGen] Print more helpful information in case of type contradiction
Dump the failing TreePattern.

llvm-svn: 321282
2017-12-21 17:12:43 +00:00
Aaron Ballman 82e17f58f0 Do not generate an empty switch statement as it causes MSVC to issue diagnostics about switch statements without case or default labels.
llvm-svn: 321217
2017-12-20 20:09:30 +00:00
Matt Arsenault 303327d58b TableGen: Allow setting SDNodeProperties on intrinsics
Allows preserving MachineMemOperands on intrinsics
through selection. For reasons I don't understand, this
is a static property of the pattern and the selector
deliberately goes out of its way to drop if not present.

Intrinsics already inherit from SDPatternOperator allowing
them to be used directly in instruction patterns. SDPatternOperator
has a list of SDNodeProperty, but you currently can't set them on
the intrinsic. Without SDNPMemOperand, when the node is selected
any memory operands are always dropped. Allowing setting this
on the intrinsics avoids needing to introduce another equivalent
target node just to have SDNPMemOperand set.

llvm-svn: 321212
2017-12-20 19:36:28 +00:00
Daniel Sanders 32de8bbd30 [globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector members
NFC for currently supported targets. This resolves a problem encountered by
targets such as RISCV that reference `Subtarget` in ImmLeaf predicates.

llvm-svn: 321176
2017-12-20 14:41:51 +00:00
Ilya Biryukov 75db08124c Allow to apply cherry-picks when building Docker images.
Reviewers: mehdi_amini, ioeric, klimek

Reviewed By: ioeric

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41393

llvm-svn: 321175
2017-12-20 14:39:07 +00:00
Sander de Smalen cd6be960ce [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2
This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of
of r320992, r320986, r320973, and r320970 by reverting
https://reviews.llvm.org/rL321024.

The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158,
so this patch-series should be safe to resubmit.

llvm-svn: 321163
2017-12-20 11:02:42 +00:00
Adrian Prantl 0e6694d111 Silence a bunch of implicit fallthrough warnings
llvm-svn: 321114
2017-12-19 22:05:25 +00:00
Quentin Colombet 63a328c30c [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before the emission
Between the creation of the last InstructionMatcher and the first
emission of the related Rule, we need to clear the internal map of IDs.
We used to do that right after the creation of the main
InstructionMatcher when building the rule and although that worked, this
is fragile because if for some reason some later code decides to create
more InstructionMatcher before the final call to emit, then the IDs
would be completely messed up.

Move that to the beginning of "emit" so that the IDs are guarantee to be
consistent.

NFC.

llvm-svn: 321053
2017-12-19 02:57:23 +00:00
Justin Bogner 4314f3adc2 update_mir_test_checks: Accept IR as input as well as MIR
We need to handle IR for tests that want to do lowering (or just
-stop-after with IR as input). I've run this on one AArch64 test to
demonstrate what it looks like.

llvm-svn: 321048
2017-12-19 00:49:04 +00:00
Justin Bogner 930a95c269 update_mir_test_checks: Add "mir" to some states and regex names
For tests that do lowering we need to support IR as input, so here we
clarify some names to avoid ambiguity in upcoming commits.

llvm-svn: 321039
2017-12-18 23:31:55 +00:00
Quentin Colombet eba10cbc88 [TableGen][GlobalISel] Make the arguments of the Instruction and Operand Matchers consistent
Move InsnVarID and OpIdx at the beginning of the list of arguments
for all the constructors of the OperandMatcher subclasses.
This matches what we do for the InstructionMatcher.

NFC.

llvm-svn: 321031
2017-12-18 22:12:13 +00:00
Quentin Colombet 34688b9e38 [TableGen][GlobalISel] Refactor optimizeRules related bit to allow code reuse
In theory, reapplying optimizeRules on each group matchers should give
us a second nesting level on the matching table. In practice, we need
more work to make that happen because all the predicates are actually
not directly available through the predicate matchers list.

NFC.

llvm-svn: 321025
2017-12-18 21:25:53 +00:00
Reid Kleckner 37517a2ddd Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo
This reverts changes r320992, r320986, r320973, and r320970.

r320970 by itself breaks the test case, and the rest depend on it.

Test case will land soon.

llvm-svn: 321024
2017-12-18 20:58:25 +00:00
Quentin Colombet ec76d9c47f [TableGen][GlobalISel] Optimize MatchTable for faster instruction selection
*** Context ***

Prior to this patchw, the table generated for matching instruction was
straight forward but highly inefficient.

Basically, each pattern generates its own set of self contained checks
and actions.
E.g., TableGen generated:
// First pattern
CheckNumOperand 3
CheckOpcode G_ADD
...
Build ADDrr
// Second pattern
CheckNumOperand 3
CheckOpcode G_ADD
...
Build ADDri
// Third pattern
CheckNumOperand 3
CheckOpcode G_SUB
...
Build SUBrr

*** Problem ***

Because of that generation, a *lot* of check were redundant between each
pattern and were checked every single time until we reach the pattern
that matches.
E.g., Taking the previous table, let say we are matching a G_SUB, that
means we were going to check all the rules for G_ADD before looking at
the G_SUB rule. In particular we are going to do:
check 3 operands; PASS
check G_ADD; FAIL
; Next rule
check 3 operands; PASS (but we already knew that!)
check G_ADD; FAIL (well it is still not true)
; Next rule
check 3 operands; PASS (really!!)
check G_SUB; PASS (at last :P)

*** Proposed Solution ***

This patch introduces a concept of group of rules (GroupMatcher) that
share some predicates and only get checked once for the whole group.

This patch only creates groups with one nesting level. Conceptually
there is nothing preventing us for having deeper nest level. However,
the current implementation is not smart enough to share the recording
(aka capturing) of values. That limits its ability to do more sharing.

For the given example the current patch will generate:
// First group
CheckOpcode G_ADD

 // First pattern
 CheckNumOperand 3
 ...
 Build ADDrr
 // Second pattern
 CheckNumOperand 3
 ...
 Build ADDri

// Second group
CheckOpcode G_SUB

 // Third pattern
 CheckNumOperand 3
 ...
 Build SUBrr

But if we allowed several nesting level, it could create a sub group
for the checknumoperand 3.
(We would need to call optimizeRules on the rules within a group.)

*** Result ***

With only one level of nesting, the instruction selection pass is up
to 4x faster. For instance, one instruction now takes 500 checks,
instead of 24k! With more nesting we could get in the tens I believe.

Differential Revision: https://reviews.llvm.org/D39034

rdar://problem/34670699

llvm-svn: 321017
2017-12-18 19:47:41 +00:00
Sander de Smalen 09f56a54d0 [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified
Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified.

Reviewers: rengolin, fhahn, olista01, echristo, efriedma

Reviewed By: fhahn

Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40363

llvm-svn: 320992
2017-12-18 16:48:53 +00:00
Sander de Smalen 190979189a [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction
Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.

Patch [3/4] in a series to add parsing of predicates and properly parse SVE 
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.

Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund

Reviewed By: olista01, sdardis

Subscribers: fhahn, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40362

llvm-svn: 320986
2017-12-18 14:34:24 +00:00
Quentin Colombet 893e0f15e2 [TableGen][GlobalISel] Make the different Matcher comparable
This opens refactoring opportunities in the match table now that we can
check that two predicates are the same.

NFC.

llvm-svn: 320890
2017-12-15 23:24:39 +00:00
Quentin Colombet a646ef08e8 [TableGen][GlobalISel] Fix unused variable warning in release mode
Introduced in r320887.

NFC.

llvm-svn: 320889
2017-12-15 23:24:36 +00:00
Quentin Colombet aad20be6ca [TableGen][GlobalISel] Have the predicate directly know which data they are dealing with
Prior to this patch, a predicate wouldn't make sense outside of its
rule. Indeed, it was only during emitting a rule that a predicate would
be made aware of the IDs of the data it is checking. Because of that,
predicates could not be moved around or compared between each other.

NFC.

llvm-svn: 320887
2017-12-15 23:07:42 +00:00
Don Hinton 44298f26b6 [debuginfo] Remove obsolete test_debuginfo.pl that was moved to debuginfo-tests.
Summary:
Now that r320495, "[debuginfo-tests] Support moving
debuginfo-tests to llvm/projects," has landed, which includes a local
copy of test_debuginfo.pl, remove the obsolete copy.

Reviewers: zturner, aprantl

Reviewed By: aprantl

Subscribers: llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D41260

llvm-svn: 320771
2017-12-15 00:06:26 +00:00
Quentin Colombet 063d798acb [TableGen][GlobalISel] Add a common class for all PredicateMatcher
NFC.

llvm-svn: 320767
2017-12-14 23:44:07 +00:00
Krzysztof Parzyszek 2aaeeb40b3 Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.

llvm-svn: 320732
2017-12-14 19:05:21 +00:00
Sander de Smalen 14e36ee5c3 Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.

This is because the code will only update the diagnostic if it is more 
specific than the previous diagnostic. However, when having validated
operands and 'moved on' to a next operand (for some instruction/alias for
which all previous operands are valid), if the diagnostic is InvalidOperand,
than that should be set as the diagnostic, not the more specific message
about a previous operand for some other instruction/alias candidate.

(Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild 
of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win
builder does not seem to rebuild AArch64GenAsmMatcher.inc with the
newly built TableGen due to a missing dependency somewhere (see:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html))

Reviewers: craig.topper, olista01, rengolin, stoklund

Reviewed By: olista01

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40011

llvm-svn: 320711
2017-12-14 16:09:48 +00:00
Michael Zolotukhin 4d6b43ca94 Remove redundant includes from utils/TableGen.
llvm-svn: 320632
2017-12-13 21:31:13 +00:00
Craig Topper ac59db2efe [Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.

I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.

llvm-svn: 320552
2017-12-13 07:26:17 +00:00
Richard Smith 8a3adc3abb Avoid constructing an out-of-range value for an enumeration (which results in UB).
llvm-svn: 320206
2017-12-08 22:32:35 +00:00
Alex Bradbury d590c85753 [TableGen] Give the option of tolerating duplicate register names
A number of architectures re-use the same register names (e.g. for both 32-bit 
FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated 
MatchRegisterName and MatchRegisterAltName, as tablegen (when built with 
asserts enabled) will fail.

When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register 
names will be tolerated. A backend can then coerce registers to the desired 
register class by (for instance) implementing validateTargetOperandClass.

At least the in-tree Sparc backend could benefit from this, as does RISC-V 
(single and double precision floating point registers).

Differential Revision: https://reviews.llvm.org/D39845

llvm-svn: 320018
2017-12-07 09:51:55 +00:00
Shoaib Meenai d806af3499 [CMake] Use PRIVATE in target_link_libraries for executables
We currently use target_link_libraries without an explicit scope
specifier (INTERFACE, PRIVATE or PUBLIC) when linking executables.
Dependencies added in this way apply to both the target and its
dependencies, i.e. they become part of the executable's link interface
and are transitive.

Transitive dependencies generally don't make sense for executables,
since you wouldn't normally be linking against an executable. This also
causes issues for generating install export files when using
LLVM_DISTRIBUTION_COMPONENTS. For example, clang has a lot of LLVM
library dependencies, which are currently added as interface
dependencies. If clang is in the distribution components but the LLVM
libraries it depends on aren't (which is a perfectly legitimate use case
if the LLVM libraries are being built static and there are therefore no
run-time dependencies on them), CMake will complain about the LLVM
libraries not being in export set when attempting to generate the
install export file for clang. This is reasonable behavior on CMake's
part, and the right thing is for LLVM's build system to explicitly use
PRIVATE dependencies for executables.

Unfortunately, CMake doesn't allow you to mix and match the keyword and
non-keyword target_link_libraries signatures for a single target; i.e.,
if a single call to target_link_libraries for a particular target uses
one of the INTERFACE, PRIVATE, or PUBLIC keywords, all other calls must
also be updated to use those keywords. This means we must do this change
in a single shot. I also fully expect to have missed some instances; I
tested by enabling all the projects in the monorepo (except dragonegg),
and configuring both with and without shared libraries, on both Darwin
and Linux, but I'm planning to rely on the buildbots for other
configurations (since it should be pretty easy to fix those).

Even after this change, we still have a lot of target_link_libraries
calls that don't specify a scope keyword, mostly for shared libraries.
I'm thinking about addressing those in a follow-up, but that's a
separate change IMO.

Differential Revision: https://reviews.llvm.org/D40823

llvm-svn: 319840
2017-12-05 21:49:56 +00:00
Daniel Sanders 3c1c4c0ee0 Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
Some concerns were raised with the direction. Revert while we discuss it and look into an alternative

llvm-svn: 319739
2017-12-05 05:52:07 +00:00
Kuba Mracek 04013b704c Disable detect_leaks in the ASanified build of LLVM when using Apple LLVM. The released Apple LLVM versions don't support LSan.
llvm-svn: 319738
2017-12-05 05:22:02 +00:00
Daniel Sanders 04e4f47e93 [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
This patch splits atomics out of the generic G_LOAD/G_STORE and into their own
G_ATOMIC_LOAD/G_ATOMIC_STORE. This is a pragmatic decision rather than a
necessary one. Atomic load/store has little in implementation in common with
non-atomic load/store. They tend to be handled very differently throughout the
backend. It also has the nice side-effect of slightly improving the common-case
performance at ISel since there's no longer a need for an atomicity check in the
matcher table.

All targets have been updated to remove the atomic load/store check from the
G_LOAD/G_STORE path. AArch64 has also been updated to mark
G_ATOMIC_LOAD/G_ATOMIC_STORE legal.

There is one issue with this patch though which also affects the extending loads
and truncating stores. The rules only match when an appropriate G_ANYEXT is
present in the MIR. For example,
  (G_ATOMIC_STORE (G_TRUNC:s16 (G_ANYEXT:s32 (G_ATOMIC_LOAD:s16 X))))
will match but:
  (G_ATOMIC_STORE (G_ATOMIC_LOAD:s16 X))
will not. This shouldn't be a problem at the moment, but as we get better at
eliminating extends/truncates we'll likely start failing to match in some
cases. The current plan is to fix this in a patch that changes the
representation of extending-load/truncating-store to allow the MMO to describe
a different type to the operation.

llvm-svn: 319691
2017-12-04 20:39:32 +00:00
Jonas Devlieghere 64774bafff [NFC][lit] Use proper semantic versioning names for variables
The variable named `minor` was actually pointing to the patch part of
the version. While I was changing this I also made the check for Apple
clang more robust by checking both patch and minor rather than just
minor.

llvm-svn: 319656
2017-12-04 14:01:34 +00:00
Oliver Stannard 7ab60605f8 Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win
buildbot, and I can't reproduce it locally, so reverting until I can work out
what is wrong.

llvm-svn: 319654
2017-12-04 13:42:22 +00:00
Oliver Stannard 7cd4db94f8 [Asm, ARM] Add fallback diag for multiple invalid operands
This adds a "invalid operands for instruction" diagnostic for
instructions where there is an instruction encoding with the correct
mnemonic and which is available for this target, but where multiple
operands do not match those which were provided. This makes it clear
that there is some combination of operands that is valid for the current
target, which the default diagnostic of "invalid instruction" does not.

Since this is a very general error, we only emit it if we don't have a
more specific error.

Differential revision: https://reviews.llvm.org/D36747

llvm-svn: 319649
2017-12-04 12:02:32 +00:00
Matt Arsenault 2e8be9d126 Fix typo in emitted attribute name
Fixes build when using this attribute combination
on an intrinsic.

llvm-svn: 319625
2017-12-03 00:03:01 +00:00
Sam Parker f7fb49afc3 Add more triples to llc_test_checks.py
Added some commonly used Arm triples to the script, with and without
the -eabi suffix.

Differential Revision: https://reviews.llvm.org/D40708

llvm-svn: 319545
2017-12-01 14:27:11 +00:00
Jonas Devlieghere 42b9a603da [lit] Don't enable LSan on Darwin for Apple clang 9.0.0
The latest clang that ships with Xcode (clang 900 or 9.0.0) does not
support LSan. This fixes the lit configuration to reflect that.

Differential revision: https://reviews.llvm.org/D40672

llvm-svn: 319530
2017-12-01 10:49:47 +00:00
Ying Yi cfb08e9e6b [lit] Implement non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands internally
Summary:
The internal shell already supports 'cd', ‘export’ and ‘echo’ commands.
This patch adds implementation of non-pipelined ‘mkdir’, ‘diff’ and ‘rm’
commands as the internal shell builtins.

Reviewed by: Zachary Turner, Reid Kleckner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39567

llvm-svn: 319528
2017-12-01 09:54:27 +00:00
Daniel Sanders 0c43b3a023 [globalisel][tablegen] Add support for relative AtomicOrderings
No test yet because the relevant rules are blocked on the atomic_load,
and atomic_store nodes.

llvm-svn: 319475
2017-11-30 21:05:59 +00:00
Daniel Sanders f499b2bf1f [globalisel][tablegen] Add support for specific immediates in the match pattern
This enables a few rules such as ARM's uxtb instruction.

llvm-svn: 319457
2017-11-30 18:48:35 +00:00
Sam Clegg 51d90c8c6b Add libstd++-4.8 exceptions to ubsan_blacklist.txt
Differential Revision: https://reviews.llvm.org/D40589

llvm-svn: 319353
2017-11-29 20:10:14 +00:00
Greg Bedwell 34a83f0faf Make check-lit tests respect LLVM_LIT_TOOLS_DIR
Differential Revision: https://reviews.llvm.org/D40520

llvm-svn: 319329
2017-11-29 18:05:26 +00:00
Daniel Sanders 766646517f [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.
GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider
range of orderings. This has then been used to import patterns using nodes such
as atomic_cmp_swap, atomic_swap, and atomic_load_*.

llvm-svn: 319232
2017-11-28 22:07:05 +00:00
Matthias Braun adf7582d14 lit: Bring back -Dtool=xxx feature lost in r313928
llvm-svn: 319139
2017-11-28 03:23:07 +00:00
Simon Dardis 9d68565262 [utils][mips] Add support for mips for update_llc_checks.py
Add support for mips, particularly skipping the matching of .frame, .(f)mask
and LLVM's usage of the .set no(reorder|at|macro) directives.

Reviewers: spatel

Differential Revision: https://reviews.llvm.org/D40268

llvm-svn: 319001
2017-11-26 19:22:44 +00:00
Ying Yi a0903c6e5d Reverted rL318911 since it broke the sanitizer-windows.
llvm-svn: 318914
2017-11-23 13:23:21 +00:00
Ying Yi 989c9e75a6 [lit] Implement non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands internally
Summary:
The internal shell already supports 'cd', ‘export’ and ‘echo’ commands. 
This patch adds implementation of non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ 
commands as the internal shell builtins.

Reviewers: Zachary Turner, Reid Kleckner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39567

llvm-svn: 318911
2017-11-23 12:48:41 +00:00
George Rimar 33894b619b Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."
It reported to have problems with memory sanitizers and DBUILD_SHARED_LIBS=ON.

llvm-svn: 318899
2017-11-23 06:52:44 +00:00
George Rimar 860a7b7901 [llvm-tblgen] - Stop using std::string in RecordKeeper.
RecordKeeper::getDef() is a hot place, it shows up in profiling
and it creates std::string instance for each search in RecordMap
though RecordKeeper::RecordMap can use StringRef as a key
instead to avoid that. Patch do that change.

Differential revision: https://reviews.llvm.org/D40170

llvm-svn: 318822
2017-11-22 07:53:48 +00:00
Craig Topper fb0d4cd48c [SelectionDAG] Add a isel matcher op to check the type of node results other than result 0.
I plan to use this to check the type of the mask result of masked gathers in the X86 backend.

llvm-svn: 318820
2017-11-22 07:11:01 +00:00
Evandro Menezes 9dc54e25f0 [TableGen] Improve error reporting
When searching for a resource unit, use the reference location instead of
the definition location in case of an error.

Differential revision: https://reviews.llvm.org/D40263

llvm-svn: 318803
2017-11-21 21:33:52 +00:00
Oliver Stannard 1e73e95f3c [Asm] Improve "too few operands" errors
- We can still emit this error if the actual instruction has two or more
  operands missing compared to the expected one.
- We should only emit this error once per instruction.

Differential revision: https://reviews.llvm.org/D36746

llvm-svn: 318770
2017-11-21 15:16:50 +00:00
Oliver Stannard 6e94331259 [Asm] Finish matching once end of formal and actual lists reached (NFC)
This is NFC, as the matcher would continue looping up to the maximum
number of operands with no effect, but this should improve performance a
bit, and makes the debug trace clearer.

Differential revision: https://reviews.llvm.org/D36744

llvm-svn: 318769
2017-11-21 15:12:05 +00:00
Sander de Smalen 4acd57eb51 Revert r318759 due to make check-all failure on Windows
llvm-svn: 318768
2017-11-21 15:07:43 +00:00
Sander de Smalen f475eed48d [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.

This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate.

Reviewers: craig.topper, olista01, rengolin, stoklund

Reviewed By: olista01

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40011

llvm-svn: 318759
2017-11-21 12:26:06 +00:00
Zachary Turner 79708b54f2 Re-revert "Refactor debuginfo-tests."
This is still breaking greendragon.

At this point I give up until someone can fix the greendragon
bots, and I will probably abandon this effort in favor of using
a private github repository.

llvm-svn: 318722
2017-11-21 01:20:28 +00:00
Zachary Turner 8b6ef88e7e Resubmit "Refactor debuginfo-tests" again.
This was reverted due to the tests being run twice on some
build bots.  Each run had a slightly different configuration
due to the way in which it was being invoked.  This fixes
the problem (albeit in a somewhat hacky way).  Hopefully in
the future we can get rid of the workflow of running
debuginfo-tests as part of clang, and then this hack can
go away.

llvm-svn: 318697
2017-11-20 21:41:36 +00:00
Sander de Smalen 0c5a29b6be [AArch64][TableGen] Skip tied result operands for InstAlias
Summary:
This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias.

This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests.

Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch.


Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka

Reviewed By: rengolin, SjoerdMeijer

Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D40030

llvm-svn: 318650
2017-11-20 14:36:40 +00:00
Eric Fiselier c812560c14 [LIT] Fix testing out-of-tree Clang builds
Summary:
Currently, LIT configures the LLVM binary path before the Clang binary path. However this breaks testing out-of-tree Clang builds (where the LLVM binary path includes a copy of Clang).

This patch reverses the order of the paths when looking for Clang, putting the Clang binary directory first.

Reviewers: zturner, beanz, chapuni, modocache, EricWF

Reviewed By: EricWF

Subscribers: mgorny, cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D40217

llvm-svn: 318607
2017-11-19 00:00:49 +00:00
Daniel Sanders c54aa9c844 [globalisel][tablegen] Generalize pointer-type inference by introducing ptypeN. NFC
ptypeN is functionally the same as typeN except that it informs the
SelectionDAG importer that an operand should be treated as a pointer even
if it was written as iN. This is important for patterns that use iN instead
of iPTR to represent pointers. E.g.:
  (set GPR64:$dst, (load GPR64:$addr))

Previously, this was handled as a hardcoded special case for the appropriate
operands to G_LOAD and G_STORE.

llvm-svn: 318574
2017-11-18 00:16:44 +00:00
Reid Kleckner 6810c20c1b [lit] Try to improve Ctrl-C behavior on Windows
This functionality was broken during a refactor a while back because
'pool' is no longer in scope.

llvm-svn: 318572
2017-11-17 23:52:33 +00:00
Zachary Turner dfeb170011 Fix an issue with llvm lit tool substitutions.
When using an installed clang with an in-tree llvm, we were not
searching in the right paths for the tools.

llvm-svn: 318564
2017-11-17 22:51:43 +00:00
David Blaikie b3bde2ea50 Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

llvm-svn: 318490
2017-11-17 01:07:10 +00:00
Zachary Turner b5c237ec3d Re-revert "Refactor debuginfo-tests"
This is still broken because it causes certain tests to be
run twice with slightly different configurations, which is
wrong in some cases.

You can observe this by running:

  ninja -nv check-all | grep debuginfo-tests

And seeing that it passes clang/test and clang/test/debuginfo-tests
to lit, which causes it to run debuginfo-tests twice.  The fix is
going to involve either:

  a) figuring out that we're running in this "deprecated" configuration,
     and then deleting the clang/test/debuginfo-tests path, which should
     cause it to behave identically to before, or:
  b) make lit smart enough that it doesn't descend into a sub-suite if
     that sub-suite already has a lit.cfg file.

llvm-svn: 318486
2017-11-17 00:41:18 +00:00
Zachary Turner 5e420717a1 Resubmit "Refactor debuginfo-tests"
This was reverted due to some failures on specific darwin buildbots,
the issue being that the new lit configuration was not setting the
SDKROOT environment variable.  We've tested a fix locally and confirmed
that it works, so this patch resubmits everything with the fix
applied.

llvm-svn: 318435
2017-11-16 18:26:20 +00:00
Daniel Sanders f76f315436 [globalisel][tablegen] Generate rule coverage and use it to identify untested rules
Summary:
This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV,
causes TableGen to instrument the generated table to collect rule coverage
information. However, LLVM_ENABLE_GISEL_COV goes a bit further than
LLVM_ENABLE_DAGISEL_COV. The information is written to files
(${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be
concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will
read this information and use it to emit warnings about untested rules.

This technique could also be used by SelectionDAG and can be further
extended to detect hot rules and give them priority over colder rules.

Usage:
* Enable LLVM_ENABLE_GISEL_COV in CMake
* Build the compiler and run some tests
* cat gisel-coverage-[0-9]* > gisel-coverage-all
* Delete lib/Target/*/*GenGlobalISel.inc*
* Build the compiler

Known issues:
* ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual
  step due to a lack of a portable 'cat' command. It should be the
  concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files.
* There's no mechanism to discard coverage information when the ruleset
  changes

Depends on D39742

Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka

Reviewed By: rovka

Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D39747

llvm-svn: 318356
2017-11-16 00:46:35 +00:00
Oliver Stannard 174fdef458 [Docs] Add tablegen backend for target opcode documentation
This is a tablegen backend to generate documentation for the opcodes that exist
for each target. For each opcode, it lists the assembly string, the names and
types of all operands, and the flags and predicates that apply to the opcode.

Differential revision: https://reviews.llvm.org/D31025

llvm-svn: 318155
2017-11-14 15:35:15 +00:00
Zachary Turner faf04a09f6 Revert "Update test_debuginfo.pl script to point to new tree location."
This reverts the aforementioned patch and 2 subsequent follow-ups,
as some buildbots are still failing 2 tests because of it.
Investigation is ongoing into the cause of the failures.

llvm-svn: 318112
2017-11-13 23:33:29 +00:00
Daniel Sanders 6d9d30a917 [tablegen] Handle atomic predicates for ordering inside tablegen. NFC.
Similar to r315841, GlobalISel and SelectionDAG require different code for the
common atomic predicates due to differences in the representation.
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.

This patch moves the implementation of the common atomic predicates related to
ordering into tablegen so that it can handle these differences.

It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.

llvm-svn: 318102
2017-11-13 23:03:47 +00:00
Daniel Sanders 87d196ca48 [tablegen] Handle atomic predicates for memory type inside tablegen. NFC.
Similar to r315841, GlobalISel and SelectionDAG require different code for the
common atomic predicates due to differences in the representation.
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.

This patch moves the implementation of the common atomic predicates related to
memory type into tablegen so that it can handle these differences.

It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.

llvm-svn: 318095
2017-11-13 22:26:13 +00:00
Daniel Sanders b78ac6e322 [globalisel][tablegen] Add support for extload.
llvm-svn: 318068
2017-11-13 18:30:23 +00:00
Petar Jovanovic bd57b8bf3f fix printing of alias instructions by removing redundant spacing
Some alias instructions are printed with an extra space after the tab
character. Fix this by skipping that space when the tab character is printed
so that the instructions are aligned with the rest of the code.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D35946

llvm-svn: 318059
2017-11-13 18:00:24 +00:00
Daniel Sanders 7e52367398 [globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
  (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
  (sext:i32 (load:i16 $ptr)<<unindexedload>>)

I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.

Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.

llvm-svn: 317971
2017-11-11 03:23:44 +00:00
Zachary Turner c631ba5f52 Update test_debuginfo.pl script to point to new tree location.
llvm-svn: 317949
2017-11-10 23:13:14 +00:00
Zachary Turner 0f2ce11df7 [debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang.  This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.

The goal of this patch is to migrate towards a more standard
workflow.  To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.

Differential Revision: https://reviews.llvm.org/D39605

llvm-svn: 317925
2017-11-10 20:57:57 +00:00
Krzysztof Parzyszek b8c68c67dc Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.

Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:

  class FooDAGToDAGISel : public SelectionDAGISel {
    // Pull in declarations only.
    #define GET_DAGISEL_DECL
    #include "FooISelDAGToDAG.inc"
  };

  // Include the function bodies (with names qualified with the provided
  // class name).
  #define GET_DAGISEL_BODY FooDAGToDAGISel
  #include "FooISelDAGToDAG.inc"

When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).

Differential Revision: https://reviews.llvm.org/D39596

llvm-svn: 317903
2017-11-10 18:36:04 +00:00
Alex Bradbury 2af11919eb [utils] Fix RISC-V support in update_llc_test_checks.py
scrub_asm_riscv now takes two arguments rather than one.

llvm-svn: 317826
2017-11-09 20:01:25 +00:00
Alex Bradbury 86f971ccd6 [utils] Add RISC-V support to update_llc_test_checks.py
This should be a trivial change, and I've started using it for generating all 
tests at https://github.com/lowrisc/riscv-llvm (i.e. it's been tested in 
action quite a lot). Note that the regex does not attempt to match 
.cfi_startproc, as I want to ensure compatibility with functions that have the 
nounwind attribute.

Differential Revision: https://reviews.llvm.org/D39789

llvm-svn: 317693
2017-11-08 14:24:42 +00:00
Alexander Richardson 46e1fd6102 Add a -D flag to FileCheck to define variables
Summary:
This makes it very easy to test files that only differ in a constant
value somewhere in the test case.

Reviewers: jlebar, hfinkel, chandlerc, probinson

Reviewed By: probinson

Subscribers: probinson, llvm-commits

Differential Revision: https://reviews.llvm.org/D39629

llvm-svn: 317572
2017-11-07 13:24:44 +00:00
Florian Hahn 603c6455d2 [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39087

llvm-svn: 317564
2017-11-07 10:43:56 +00:00
Justin Bogner f7b1007345 update_mir_test_checks: Be careful about replacing entire vregs
Previously, this could end up replacing a vreg like %14 with
[[VREG1]]4, where VREG1 was the match for %1. That's obviously not
correct, though it hasn't actually come up in any tests I've converted
so far.

llvm-svn: 317509
2017-11-06 21:06:09 +00:00
Aaron Ballman cbaf5a4f50 Move the llvm-tblgen project into the Tablegenning folder on IDEs like Visual Studio rather than leave it in the root directory. NFC.
llvm-svn: 317420
2017-11-04 20:07:16 +00:00
Craig Topper e5d44cefea [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 into VPERM2F128/VPERM2I128.
This recovers some of the tests that were changed by r317403.

llvm-svn: 317410
2017-11-04 18:10:03 +00:00
Diana Picus d1b618177a [globalisel][tablegen] Skip src child predicates
The GlobalISel TableGen backend didn't check for predicates on the
source children. This caused it to generate code for ARM patterns such
as SMLABB or similar, but without properly checking for the sext_16_node
part of the operands. This in turn meant that we would select SMLABB
instead of MLA for simple sequences such as s32 + s32 * s32, which is
wrong (we want a MLA on the full operands, not just their bottom 16
bits).

This patch forces TableGen to skip patterns with predicates on the src
children, so it doesn't generate code for SMLABB and other similar ARM
instructions at all anymore. AArch64 and X86 are not affected.

Differential Revision: https://reviews.llvm.org/D39554

llvm-svn: 317313
2017-11-03 10:30:19 +00:00
Craig Topper 2fda36a18e [TableGen] Add an extra blank line to DAGISel output file to separate functions.
llvm-svn: 317298
2017-11-03 05:19:34 +00:00
Daniel Sanders 466fe399b8 [globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.
llvm-svn: 317132
2017-11-01 22:13:05 +00:00
Craig Topper 4e56ba271e [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit VPALIGND/Q into VPALIGNR if the extended registers aren't being used.
This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding.

Differential Revision: https://reviews.llvm.org/D39401

llvm-svn: 317122
2017-11-01 21:00:59 +00:00
Daniel Sanders 9cbe7c7f93 [globalisel][tablegen] Add support for multi-insn emission
The importer will now accept nested instructions in the result pattern such as
(ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction
def's a single vreg and the parent instruction consumes a single vreg where a
nested instruction is specified. The importer will automatically create a vreg
to connect the two using the type information from the pattern. This vreg will
be constrained to the register classes given in the instruction definitions*.

* REG_SEQUENCE is explicitly rejected because of this. The definition doesn't
  constrain to a register class and it therefore needs special handling.

llvm-svn: 317117
2017-11-01 19:57:57 +00:00
NAKAMURA Takumi 1657f2ad99 Fix warnings discovered by rL317076. [-Wunused-private-field]
llvm-svn: 317091
2017-11-01 13:47:55 +00:00
Daniel Sanders 198447a447 [globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC
The next commit will add support for multi-instruction emission so we need to
start allocating instruction ID's instead of hard-coding them to 0.

llvm-svn: 317057
2017-11-01 00:29:47 +00:00
Jake Ehrlich cde781015f Add system-linux to allow tests run with llvm-lit to restrict themselves to linux
I need a test that only runs in a reasonable amount of time on systems
that have sparse files. The broadest class of systems that support
sparse files are linux systems. So restricting my test to linux systems
should suffice. This change adds the system-linux feature to llvm-lit so
that it can be required.

Differential Revision: https://reviews.llvm.org/D39482

llvm-svn: 317055
2017-11-01 00:18:51 +00:00
Daniel Sanders 7438b26317 Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
(ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the
const_iterator forms of insert() and emplace() that were added in C++11. As a
result I've switched the const_iterators to iterators.

llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Daniel Sanders f69d1b018c Revert r317040: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The same bots fail but I believe I know what the issue is now. These bots are
missing the const_iterator versions of insert/emplace/etc. that were introduced
in C++11.

llvm-svn: 317042
2017-10-31 21:54:52 +00:00
Daniel Sanders 374f71ac90 Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
 (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't
like a call to emplace(). I've replaced it with insert() to see if it's a quirk
of the C++11 support.

llvm-svn: 317040
2017-10-31 21:34:53 +00:00
Daniel Sanders f87c142d9e Revert r317029: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it.

llvm-svn: 317033
2017-10-31 20:29:28 +00:00
Daniel Sanders e8a4f0d869 [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
  (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

llvm-svn: 317029
2017-10-31 19:54:05 +00:00
Daniel Sanders df258e328a [globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC
Multi-instruction emission will require that we have separate handling for
the defs between the implicitly created temporaries and the rule outputs.
The former require new temporary vregs while the latter should copy existing
operands. Factor out the implicit def/use renderers to minimize the code
duplication when we implement that.

llvm-svn: 317025
2017-10-31 19:09:29 +00:00
Daniel Sanders a7b7526416 [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to choose a mutatable instruction. NFC
Prepare for multiple instruction emission by allowing BuildMIAction to
search for a suitable matcher that will support mutation.

This patch deliberately neglects to add matchers aside from the root to
preserve NFC. That said, it should be noted that until we support mutations
other than just the opcode the chances of finding a non-root instruction
for which canMutate() is true, is essentially zero. Furthermore in the
presence of multi-instruction emission the chances of finding any
instruction for which canMutate() is true is also zero. Nevertheless, we
can't continue to require that all BuildMIAction's consider the root of the match
to be recyclable due to the risk of recycling it twice in the same rule.

llvm-svn: 317022
2017-10-31 18:50:24 +00:00
Daniel Sanders 6ea17edd80 [globalisel][tablegen] Allow any comment in DebugCommentAction. NFC
llvm-svn: 317017
2017-10-31 18:07:03 +00:00
Ayman Musa 25589e2a55 Adding a shufflevector and select LLVM IR instructions fuzz tool
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions.
This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets.
The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further.

Differential Revision: https://reviews.llvm.org/D38031

Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111
llvm-svn: 316989
2017-10-31 11:39:31 +00:00
Zachary Turner 94f5032aed Force #define GTEST_LANG_CXX11.
gtest depends on this #define to determine whether it can
use various classes like std::tuple, or whether it has to fall
back to experimental classes in the std::tr1 namespace.  The
check in the current version of gtest relies on the value of
the `__cplusplus` macro, but MSVC provides a non-conformant
value of this macro, making it effectively impossible to detect
C++11.  In short, LLVM compiled with MSVC has been silently
using the tr1 versions of several classes since the beginning of
time.

This would normally be pretty benign, except that in the latest
preview of MSVC they have marked all of the tr1 classes
deprecated, so it spews thousands of warnings.

llvm-svn: 316798
2017-10-27 21:12:28 +00:00
Craig Topper 01ebd9b7f7 [TableGen] Use Twine instead of std::string concatenation in two calls to PrintFatalError.
llvm-svn: 316697
2017-10-26 20:49:36 +00:00
Craig Topper 0551556ed2 [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell check function so it can use the correct table based on variant.
I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants.

llvm-svn: 316641
2017-10-26 06:46:41 +00:00
Craig Topper 2a06028c0a [AsmParser][TableGen] Make the generated mnemonic spell checker function a file local static function.
Also only emit in targets that specificially request it. This is required so we don't get an unused static function error.

llvm-svn: 316640
2017-10-26 06:46:40 +00:00
Daniel Sanders ab1d119154 [globalisel][tablegen] Fix future undefined behaviour in r316463.
I missed a dereference of `Matched` that preceeded the new check. Thanks to
Justin Bogner for spotting it.

llvm-svn: 316480
2017-10-24 18:11:54 +00:00
Daniel Sanders 64f745cf20 [globalisel][tablegen] Multi-insn emission requires that BuildMIAction support not being linked to an InstructionMatcher. NFC
When multi-instruction emission is supported, it will no longer be guaranteed
that every BuildMIAction has a corresponding matched instruction. BuildMIAction
should support not having one to cover the case where a rule produces more
instructions than it matched.

llvm-svn: 316463
2017-10-24 17:08:43 +00:00
Craig Topper 194cb74dec [TableGen] Fix some formatting quirks in the subtarget output file.
llvm-svn: 316450
2017-10-24 15:50:55 +00:00
Craig Topper df1285b8f4 [TableGen] Simplify some of the subtarget emission by removing code that avoids printing commas at the end of arrays and enums.
The C++ standard allows for trailing commas. We already do this in many other emitters.

llvm-svn: 316449
2017-10-24 15:50:53 +00:00
Sanjay Patel 9db5da2b63 [utils] make retq/retl regex an option that is off by default
Ideally, we should compare 32- and 64-bit versions to see if the 
ret line is the only difference and then insert the regex only
in that case. But this is a quick hack to avoid a bunch of noise
as existing tests are updated.

llvm-svn: 316443
2017-10-24 14:32:52 +00:00
Daniel Sanders bd83ad4a87 [globalisel][tablegen] Remove unused InstructionMatcher's. NFC
llvm-svn: 316407
2017-10-24 01:48:34 +00:00
Daniel Sanders d66e0901ae [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.
This patch enables the import of stores. Unfortunately, doing so by itself,
loses an optimization where storing 0 to memory makes use of WZR/XZR.

To mitigate this, this patch also introduces a new feature that allows register
operands to nominate a zero register. When this is done, GlobalISel will
substitute (G_CONSTANT 0) with the nominated register automatically. This
is currently configured to only apply to the stores.

Applying it to GPR32/GPR64 register classes in general will be done after
review see (https://reviews.llvm.org/D39150).

llvm-svn: 316360
2017-10-23 18:19:24 +00:00
Craig Topper e06cc6d9ba [X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
llvm-svn: 316345
2017-10-23 16:49:26 +00:00
Craig Topper 64cb997ce1 [X86] Update a doxygen comment in the disassembler tablegen code. NFC
llvm-svn: 316309
2017-10-23 03:42:35 +00:00
Craig Topper 326008c615 [X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.

llvm-svn: 316308
2017-10-23 02:26:24 +00:00
Fangrui Song dc168722da [utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.

Subscribers: nemanjai

Differential Revision: https://reviews.llvm.org/D39164

llvm-svn: 316297
2017-10-22 18:43:23 +00:00
Craig Topper dac20263a1 [X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.

More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).

llvm-svn: 316294
2017-10-22 17:22:29 +00:00
Craig Topper e975127db6 [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.

llvm-svn: 316285
2017-10-22 06:18:26 +00:00
Craig Topper ca2382d809 [X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.
This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB.

This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type.

This fixes PR32807.

llvm-svn: 316273
2017-10-21 20:03:20 +00:00
Sanjay Patel f1735a58ed [utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)
llvm-svn: 316242
2017-10-20 21:55:23 +00:00
Daniel Sanders 1e4569fdc1 [globalisel][tablegen] Fix small spelling nits. NFC
ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.

llvm-svn: 316237
2017-10-20 20:55:29 +00:00
Justin Bogner da9600e646 update_mir_test_checks: Support adding checks for vreg classes
This is a temporary hack to support adding checks for the "registers:"
block of mir functions. This is necessary to convert a number of tests
so that there's less churn when we change the MIR printer to put the
vreg classes on defs instead of in their own block.

llvm-svn: 316134
2017-10-18 22:39:55 +00:00
Justin Bogner 6b55f1f513 update_mir_test_checks: Improve message when updating fails
llvm-svn: 316133
2017-10-18 22:36:08 +00:00
Justin Bogner 3de36d6f11 update_mir_test_checks: Handle empty liveins
An empty livein block doesn't make much sense (why not just omit it?)
but they're legal and some tests have them, so its best to handle it.

llvm-svn: 316089
2017-10-18 15:38:56 +00:00
Justin Bogner 1a33cdb2e2 update_mir_test_checks: Do a better job of disambiguating names
Matching prefixes isn't good enough, because it leads to things like
calling the first constant C3 just because there were two copies
before it. Tighten up the check to match more precisely, but also be
careful about ambiguity when dealing with target opcodes that end in a
number.

llvm-svn: 316088
2017-10-18 15:37:09 +00:00
Justin Bogner 4b1ab94c7a update_mir_test_checks: Support '-' in function names
Some AArch64 and AMDGPU tests have functions with hyphens in the names

llvm-svn: 316063
2017-10-18 05:52:56 +00:00
Justin Bogner cf30db922e update_mir_test_checks: Fix a typo I made while preparing for commit
I accidentally added an extra arg here, so this didn't work at all.

llvm-svn: 316062
2017-10-18 05:39:22 +00:00
Justin Bogner 7c1bdaf7ca Add a utility to update MIR checks, similar to update_llc_test_checks
This adds update_mir_test_checks, which updates the check lines in mir
tests. This can only update tests that start and end with .mir
currently (ie, -run-pass) but it should be sufficient for updating at
least some of the GlobalISel tests.

llvm-svn: 316057
2017-10-18 02:20:31 +00:00
Peter Collingbourne c03ceb92ca lit: Improve %: normalization.
The new scheme should match the normalization of embedded paths in
linkrepro tar files.

Differential Revision: https://reviews.llvm.org/D39023

llvm-svn: 316044
2017-10-17 23:46:34 +00:00
Reid Kleckner cfdd4a2699 Revert MSVC 2017 build fix and fix it by moving the method that implicitly instantiates addPredicate out of line
llvm-svn: 315932
2017-10-16 20:31:16 +00:00
Reid Kleckner 46e0918f83 Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlier
MSVC doesn't seem to like implicitly instantiating addPredicate and then
explicitly specializing it later. It causes an internal compiler error.

llvm-svn: 315930
2017-10-16 20:23:16 +00:00
Javed Absar dfd8e2ffd1 [TableGen] Simplify CallingConvEmitter.cpp. NFC.
llvm-svn: 315911
2017-10-16 14:52:26 +00:00
Javed Absar 776bf1de01 [TableGen] Range loopify DAGISelMatcher. NFC.
llvm-svn: 315891
2017-10-16 06:43:54 +00:00
Daniel Sanders ea8711b88e Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
Summary:
iPTR is a pointer of subtarget-specific size to any address space. Therefore
type checks on this size derive the SizeInBits from a subtarget hook.

At this point, we can import the simplests G_LOAD rules and select load
instructions using them. Further patches will support for the predicates to
enable additional loads as well as the stores.

The previous commit failed on MSVC due to a failure to convert an
initializer_list to a std::vector. Hopefully, MSVC will accept this version.

Depends on D37457

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37458

llvm-svn: 315887
2017-10-16 03:36:29 +00:00
Daniel Sanders ce72d611af Revert r315885: [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
MSVC doesn't like one of the constructors.

llvm-svn: 315886
2017-10-16 02:15:39 +00:00
Daniel Sanders 6735ea86cd [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
Summary:
iPTR is a pointer of subtarget-specific size to any address space. Therefore
type checks on this size derive the SizeInBits from a subtarget hook.

At this point, we can import the simplests G_LOAD rules and select load
instructions using them. Further patches will support for the predicates to
enable additional loads as well as the stores.

Depends on D37457

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37458

llvm-svn: 315885
2017-10-16 01:16:35 +00:00
Daniel Sanders a71f454765 [globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks
Summary:
This includes some context-sensitivity in the MVT to LLT conversion so that
pointer types are tested correctly.
FIXME: I'm not happy with the way this is done since everything is a
       special-case. I've yet to find a reasonable way to implement it.

select-load.mir fails because <1 x s64> loads in tablegen get priority over s64
loads. This is fixed in the next patch and as such they should be committed
together, I've posted them separately to help with the review.

Depends on D37456

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37457

llvm-svn: 315884
2017-10-16 00:56:30 +00:00
Daniel Sanders adbf58dc0b [tablegen] Use hasPredCode()/hasImmCode() instead of getPredCode().empty()/getImmCode().empty(). NFC
These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty.

llvm-svn: 315872
2017-10-15 19:01:32 +00:00
Daniel Sanders df39cbae2f Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator
Summary:
It's possible for a ComplexPattern to be used as an operator in a match
pattern. This is used by the load/store patterns in AArch64 to name the
suboperands returned by ComplexPattern predicate so that they can be broken
apart and referenced independently in the result pattern.

This patch adds support for this in order to enable the import of load/store
patterns.

Depends on D37445

Hopefully fixed the ambiguous constructor that a large number of bots reported.

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D37456

llvm-svn: 315869
2017-10-15 18:22:54 +00:00
Daniel Sanders bb082a36d3 Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator
A large number of bots are failing on an ambiguous constructor call.

llvm-svn: 315866
2017-10-15 17:51:07 +00:00
Daniel Sanders b95b867dd8 [globalisel][tablegen] Import ComplexPattern when used as an operator
Summary:
It's possible for a ComplexPattern to be used as an operator in a match
pattern. This is used by the load/store patterns in AArch64 to name the
suboperands returned by ComplexPattern predicate so that they can be broken
apart and referenced independently in the result pattern.

This patch adds support for this in order to enable the import of load/store
patterns.

Depends on D37445

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D37456

llvm-svn: 315863
2017-10-15 17:03:36 +00:00
Krzysztof Parzyszek 4b3876f7a3 [TableGen] Remove error checks incorrectly failing on non-error conditions
In type inference, an empty type set for a specific hw mode is not an
error. In earlier stages of the design it was, but having to use non-
parameterized types with target intrinsics necessarily led to type
contradictions: since the intrinsics used specific types, they were
only valid for a specific hw mode, and the resulting type set for other
modes ended up empty. To accommodate the existence of such intrinsics
individual type sets were allowed to be empty as long as not all sets
were empty.

llvm-svn: 315858
2017-10-15 15:39:56 +00:00
Aaron Ballman 615eb47035 Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.
Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1

llvm-svn: 315854
2017-10-15 14:32:27 +00:00
Daniel Sanders 39690bdf42 [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC
Summary:
There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for
ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load
and atomic loads are handled by a separate node. However, this is not true of
GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity
of the operation. As a result, this mapping must also add a predicate that
checks for non-atomic MachineMemOperands.

This is NFC since these nodes always have predicates in practice and are
therefore always rejected at the moment.

Depends on D37443

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37445

llvm-svn: 315843
2017-10-15 02:41:12 +00:00
Daniel Sanders 3f267bf769 [tablegen] Handle common load/store predicates inside tablegen. NFC.
Summary:
GlobalISel and SelectionDAG require different code for the common
load/store predicates due to differences in the representation.
For example:
   SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG
   GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr))
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.

This patch moves the implementation of the common load/store predicates
into tablegen so that it can handle these differences.

It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.

Depends on D36618

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37443

Includes a partial revert of r315826 since this patch makes it necessary for
getPredCode() to return a std::string and getImmCode() should have the same
interface as getPredCode().

llvm-svn: 315841
2017-10-15 02:06:44 +00:00
Simon Pilgrim 6ecae9fc97 [TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters.

llvm-svn: 315826
2017-10-14 21:27:53 +00:00
Jordan Rose e55d9a1403 Revert "lit.py: Add new %{shared_output(LABEL)} substitution"
This reverts r315697 and my ill-fated attempts to fix it on Windows.
I'll try again when I get access to a Windows machine.

llvm-svn: 315793
2017-10-14 04:01:27 +00:00
Jordan Rose a33a17605d lit.py: Give up and disable the new shared-output.py test on Windows
"No such file or directory: C:\\...\\tests\\Output\\shared-output.py.tmp/Output/Shared/SHARED.tmp"

And yet other forward-slashes don't seem to be causing the same
problem. I'll see if I can get ahold of a Windows machine to poke at
this directly later.

llvm-svn: 315792
2017-10-14 03:33:46 +00:00
Jordan Rose fddfb5ad4c lit.py: Previous test fix was a red herring; backslashes are escapes
I don't have access to a Windows machine at the moment, so if this
doesn't fix it I'll just revert for now.

llvm-svn: 315782
2017-10-14 00:49:19 +00:00
Daniel Sanders bfa9e2cae7 [globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed.
Summary:
Operand variable lookups are now performed by the RuleMatcher rather than
searching the whole matcher hierarchy for a match. This revealed a wrong-code
bug that currently affects ARM and X86 where patterns that use a variable more
than once in the match pattern will be imported but won't check that the
operands are identical. This can cause the tablegen-erated matcher to
accept matches that should be rejected.

Depends on D36569

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Subscribers: aemerson, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36618

llvm-svn: 315780
2017-10-14 00:31:58 +00:00
Jordan Rose aafbc1c4db lit.py: Fix new test harder for systems that don't use / as os.path.sep
I didn't think about '%{inputs}' having the same problem. This one
should be a fully Windows path name.

llvm-svn: 315779
2017-10-14 00:26:48 +00:00
Jordan Rose f4fd5938e7 lit.py: Fix new test for systems that don't use / as os.path.sep
llvm-svn: 315773
2017-10-13 22:46:40 +00:00
Daniel Sanders 2fed4ffa9e [globalisel][tablegen] Fix a use-after free bug that manifests on non-macOS machines.
llvm-svn: 315765
2017-10-13 21:51:20 +00:00
Daniel Sanders 11300cead8 [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf.
Summary:
There's only a tablegen testcase for IntImmLeaf and not a CodeGen one
because the relevant rules are rejected for other reasons at the moment.
On AArch64, it's because there's an SDNodeXForm attached to the operand.
On X86, it's because the rule either emits multiple instructions or has
another predicate using PatFrag which cannot easily be supported at the
same time.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36569

llvm-svn: 315761
2017-10-13 21:28:03 +00:00
Daniel Sanders 649c585710 [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 use them.
Summary:
The purpose of this patch is to expose more information about ImmLeaf-like
PatLeaf's so that GlobalISel can learn to import them. Previously, ImmLeaf
could only be used to test int64_t's produced by sign-extending an APInt.
Other tests on immediates had to use the generic PatLeaf and extract the
constant using C++.

With this patch, tablegen will know how to generate predicates for APInt,
and APFloat. This will allow it to 'do the right thing' for both SelectionDAG
and GlobalISel which require different methods of extracting the immediate
from the IR.

This is NFC for SelectionDAG since the new code is equivalent to the
previous code. It's also NFC for FastISel because FastIselShouldIgnore is 1
for the ImmLeaf subclasses. Enabling FastIselShouldIgnore == 0 for these new
subclasses will require a significant re-factor of FastISel.

For GlobalISel, it's currently NFC because the relevant code to import the
affected rules is not yet present. This will be added in a later patch.

Depends on D36086

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: bjope, aemerson, rengolin, javed.absar, igorb, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D36534

llvm-svn: 315747
2017-10-13 20:42:18 +00:00
Daniel Sanders 9e0ae7bd8b Revert r315148 [TableGen] Avoid unnecessary std::string creations
I'm about to commit a patch that makes them necessary for getPredCode() and
it would be strange for getPredCode() and getImmCode() to require different
usage.

llvm-svn: 315733
2017-10-13 19:00:01 +00:00
Javed Absar 08fb414b21 [TableGen] : Simplify RegisterInfoEmitter
llvm-svn: 315700
2017-10-13 16:27:57 +00:00
Jordan Rose 53be3224b2 lit.py: Add new %{shared_output(LABEL)} substitution
This refers to a temporary path that can be shared across all tests,
identified by a particular label. This can be used for things like
caches.

At the moment, the character set for the LABEL is limited to C
identifier characters, plus '-', '+', '=', and '.'. This is the same
set of characters currently allowed in REQUIRES clause identifiers.

llvm-svn: 315697
2017-10-13 16:12:23 +00:00
Zachary Turner ad5997e87a [lit] Raise the logic for enabling clang & lld substitutions to llvm.
This paves the way for other projects which might /use/ clang or
lld but not necessarily need to the full set of functionality
available to clang and lld tests to be able to have a basic set
of substitutions that allow a project to run the clang or lld
executables.

llvm-svn: 315627
2017-10-12 21:56:05 +00:00
Artem Belevich 786ca6a166 [TableGen] Allow intrinsics to have up to 8 return values.
Differential Revision: https://reviews.llvm.org/D38633

llvm-svn: 315598
2017-10-12 17:40:00 +00:00
Don Hinton 3e0199f7eb [dump] Remove NDEBUG from test to enable dump methods [NFC]
Summary:
Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with
LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP.

Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods.

Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so
it'll be picked up by public headers.

Differential Revision: https://reviews.llvm.org/D38406

llvm-svn: 315590
2017-10-12 16:16:06 +00:00
Oliver Stannard dab5212884 [AsmParser] Suppress compile warning for targets with no register diags
This fixes the "switch statement contains 'default' but no 'case' labels"
warnings in table-generated code introduced in r315295.

llvm-svn: 315571
2017-10-12 09:28:23 +00:00
Zachary Turner 41a9ee98f9 Revert "[ADT] Make Twine's copy constructor private."
This reverts commit 4e4ee1c507e2707bb3c208e1e1b6551c3015cbf5.

This is failing due to some code that isn't built on MSVC
so I didn't catch.  Not immediately obvious how to fix this
at first glance, so I'm reverting for now.

llvm-svn: 315536
2017-10-11 23:54:34 +00:00
Zachary Turner 337462b365 [ADT] Make Twine's copy constructor private.
There's a lot of misuse of Twine scattered around LLVM.  This
ranges in severity from benign (returning a Twine from a function
by value that is just a string literal) to pretty sketchy (storing
a Twine by value in a class).  While there are some uses for
copying Twines, most of the very compelling ones are confined
to the Twine class implementation itself, and other uses are
either dubious or easily worked around.

This patch makes Twine's copy constructor private, and fixes up
all callsites.

Differential Revision: https://reviews.llvm.org/D38767

llvm-svn: 315530
2017-10-11 23:33:06 +00:00
Javed Absar 2c9570c096 [TableGen] Tidy up CodeGenSchedule.cpp
Use range_loop where it simplifies.

llvm-svn: 315446
2017-10-11 09:33:23 +00:00
Oliver Stannard 4191b9eaea [Asm] Add debug tracing in table-generated assembly matcher
This adds debug tracing to the table-generated assembly instruction matcher,
enabled by the -debug-only=asm-matcher option.

The changes in the target AsmParsers are to add an MCInstrInfo reference under
a consistent name, so that we can use it from table-generated code. This was
already being used this way for targets that use deprecation warnings, but 5
targets did not have it, and Hexagon had it under a different name to the other
backends.

llvm-svn: 315445
2017-10-11 09:17:43 +00:00
Francis Ricci 072eff0930 [lit] Only enable LSan on darwin when clang supports it
Summary:
LSan on darwin doesn't exist on older versions of clang,
causing non-boostrapped sanitized buildbots to fail

Reviewers: kubamracek, qcolombet, sqlbyme, zturner, modocache

Reviewed By: zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38703

llvm-svn: 315333
2017-10-10 17:21:32 +00:00
Javed Absar 9003dd7824 [TableGen] Convert VarDef to range_loop. NFC.
llvm-svn: 315321
2017-10-10 15:58:45 +00:00
Oliver Stannard 29ffd3f1d9 [AsmParser] Add DiagnosticString to register classes in tablegen
This allows a DiagnosticType and/or DiagnosticString to be associated
with a RegisterClass in tablegen, so that we can emit diagnostics in the
assembler when a register operand is incorrect.

DiagnosticType creates a predictable enum value, which gets returned as
the error code when an operand does not match, and can be used by the
assembly parser to map to a user-facing diagnostic. DiagnosticString
creates an anonymous enum value (currently based on the tablegen class
name), and a function to map from enum values to strings will be
generated. Both of these work the same was as they do for AsmOperand.

This isn't used by any targets yet, but has one (positive) side-effect.
It improves the diagnostic codes returned by validateOperandClass - we
always want to emit the diagnostic that relates to the expected operand
class, but this wasn't always being done when the expected and actual
classes were completely different (token/register/custom). This causes a
few AArch64 diagnostics to be improved, as Match_InvalidOperand was
being returned instead of a specific diagnostic type.

Differential revision: https://reviews.llvm.org/D36691

llvm-svn: 315295
2017-10-10 11:00:40 +00:00
Eugene Zemtsov eb4adc3daf Fix LLDB build for Android.
Currently libstdc++ on Android doesn't support std::to_string().

Differential Revision: https://reviews.llvm.org/D38701

llvm-svn: 315246
2017-10-09 22:43:35 +00:00
Daniel Sanders 4d4e7650dc [globalisel] Add support for ValueType operands in patterns.
It's rare but there are a small number of patterns like this:
    (set i64:$dst, (add i64:$src1, i64:$src2))
These should be equivalent to register classes except they shouldn't check for
a specific register bank.

This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other
in-tree targets such as BPF.

llvm-svn: 315226
2017-10-09 18:14:53 +00:00
Javed Absar 21c75912f5 [TableGen] remove make_range where not necessary
llvm-svn: 315209
2017-10-09 16:21:25 +00:00
Javed Absar f45d0b9849 [TableGen] Simplify, add range_loop in CodeGenSchedule
llvm-svn: 315183
2017-10-08 17:23:30 +00:00
Ayman Musa 993339b941 [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default.
After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'.
In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is:

 # Commit the tablegen backend disabled by default.

 # Proceed with an incremental updating of the manual tables - while checking the validity of each added entry.

 # Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead.

 # Schedule periodical (1 week/2 weeks/1 month) runs of the pass:

   - if changes appear (new entries):
      - make sure the entries are legal
      - If they are not, mark them as illegal to folding
   - Commit the changes (if there are any).

CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables.

Differential Revision: https://reviews.llvm.org/D38028

llvm-svn: 315173
2017-10-08 09:20:32 +00:00
Simon Pilgrim b021b13aac [TableGen] Avoid repeated find calls in CodeGenDAGPatterns getters. NFCI.
The assertion tests were using count() instead of testing the find result, resulting in double the number of searches in debug/assert builds.

Instead, call find once (like the release builds do) and assert the result against end().

llvm-svn: 315151
2017-10-07 14:34:24 +00:00
Simon Pilgrim 5e030f9cdc [TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters and in CodeGenDAGPatterns::getSDNodeNamed

Differential Revision: https://reviews.llvm.org/D38624

llvm-svn: 315148
2017-10-07 12:08:43 +00:00
Zachary Turner 96b04b68ed [lit] Improve tool substitution in lit.
This addresses two sources of inconsistency in test configuration
files.

1. Substitution boundaries.  Previously you would specify a
   substitution, such as 'lli', and then additionally a set
   of characters that should fail to match before and after
   the tool.  This was used, for example, so that matches that
   are parts of full paths would not be replaced.  But not all
   tools did this, and those that did would often re-invent
   the set of characters themselves, leading to inconsistency.
   Now, every tool substitution defaults to using a sane set
   of reasonable defaults and you have to explicitly opt out
   of it.  This actually fixed a few latent bugs that were
   never being surfaced, but only on accident.

2. There was no standard way for the system to decide how to
   locate a tool.  Sometimes you have an explicit path, sometimes
   we would search for it and build up a path ourselves, and
   sometimes we would build up a full command line.  Furthermore,
   there was no standardized way to handle missing tools.  Do we
   warn, fail, ignore, etc?  All of this is now encapsulated in
   the ToolSubst class.  You either specify an exact command to
   run, or an instance of FindTool('<tool-name>') and everything
   else just works.  Furthermore, you can specify an action to
   take if the tool cannot be resolved.

Differential Revision: https://reviews.llvm.org/D38565

llvm-svn: 315085
2017-10-06 17:54:46 +00:00
Zachary Turner c981448063 Run pyformat on lit code.
llvm-svn: 315084
2017-10-06 17:54:27 +00:00
Simon Pilgrim d0faf16d04 Strip trailing whitespace
llvm-svn: 315070
2017-10-06 15:33:55 +00:00
Javed Absar 32e3cb7bde [TableGen] Simplify SubtargetEmitter
Remove unnecessary duplicate if-condition.

llvm-svn: 315068
2017-10-06 15:25:04 +00:00
Javed Absar 41705e9e09 [TableGen] : CodeGenInsrtuction modify to range loop. NFC.
llvm-svn: 315050
2017-10-06 09:32:45 +00:00
Javed Absar fc500041bb [TablgeGen] : Tidy up CodeGenSchedule. NFC.
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38534

llvm-svn: 314982
2017-10-05 13:27:43 +00:00
Francis Ricci 954b94f5df [test] Fix append_path in the empty case
Summary:
normpath() was being called on an empty string and appended to
the environment variable in the case where the environment variable
was unset. This led to ":." being appended to the path, since
normpath() of an empty string is '.', presumably to represent cwd.

Reviewers: zturner, sqlbyme, modocache

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38542

llvm-svn: 314915
2017-10-04 17:30:28 +00:00
Oliver Stannard 41dfac3eb2 [AsmParser] Add DiagnosticString to AsmOperands in tablegen
This adds a DiagnosticString member to the AsmOperand tablegen class, so
that the diagnostic text to be used when an assembly operand is
incorrect can be stored in the tablegen description of the operand,
rather than in a separate switch statement in the AsmParser.

If DiagnosticString is used for any operands, tablegen will emit a
getMatchKindDiag function, to map from diagnostic enums to strings.

Differential revision: https://reviews.llvm.org/D31606

llvm-svn: 314803
2017-10-03 14:34:57 +00:00
Oliver Stannard 65f7bc5bf0 [Assembler] Report multiple near misses for invalid instructions
The current table-generated assembly instruction matcher returns a
64-bit error code when matching fails. Since multiple instruction
encodings with the same mnemonic can fail for different reasons, it uses
some heuristics to decide which message is important.

This heuristic does not work well for targets that have many encodings
with the same mnemonic but different operands, or which have different
versions of instructions controlled by subtarget features, as it is hard
to know which encoding the user was intending to use.

Instead of trying to improve the heuristic in the table-generated
matcher, this patch changes it to report a list of near-miss encodings.
This list contains an entry for each encoding with the correct mnemonic,
but with exactly one thing preventing it from being valid. This thing
could be a single invalid operand, a missing target feature or a failed
target-specific validation function.

The target-specific assembly parser can then report an error message
giving multiple options for instruction variants that the user may have
been trying to use. For example, I am working on a patch to use this for
ARM, which can give this error for an invalid instruction for ARMv6-M:

  <stdin>:8:3: error: invalid instruction, multiple near-miss encodings found
    adds r0, r1, #0x8
    ^
  <stdin>:8:3: note: for one encoding: instruction requires: thumb2
    adds r0, r1, #0x8
    ^
  <stdin>:8:16: note: for one encoding: expected an integer in range [0, 7]
    adds r0, r1, #0x8
                 ^
  <stdin>:8:16: note: for one encoding: expected a register in range [r0, r7]
    adds r0, r1, #0x8
                 ^

This also allows the target-specific assembly parser to apply its own
heuristics to suppress some errors. For example, the error "instruction
requires: arm-mode" is never going to be useful when targeting an
M-profile architecture (which does not have ARM mode).

This patch just adds the target-independent mechanism for doing this,
all targets still use the old mechanism. I've added a bit in the
AsmParser tablegen class to allow targets to switch to this new
mechanism. To use this, the target-specific assembly parser will have to
be modified for the change in signature of MatchInstructionImpl, and to
report errors based on the list of near-misses.

Differential revision: https://reviews.llvm.org/D27620

llvm-svn: 314774
2017-10-03 09:33:12 +00:00
Michal Gorny d6a4c79b14 [lit] Fix running lit tests in unconfigured source dir
Fix llvm_tools_dir attribute access not to fail when the variable is not
present. This directory is not really necessary to run lit tests,
and the code already accounts for it being None.

The reference was added in r313407, and it breaks the stand-alone lit
package in Gentoo.

Differential Revision: https://reviews.llvm.org/D38442

llvm-svn: 314620
2017-10-01 07:13:25 +00:00
Francis Ricci a7bf226529 [test] Enable LeakSanitizer on 64-bit Darwin ASan llvm builds
Summary:
Also disables leak checking on lto tests, due to many leaks reported
in the system's ld64.

Reviewers: kcc, pcc, bogner, kubamracek

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D37781

llvm-svn: 314535
2017-09-29 16:51:50 +00:00
Don Hinton 53eb637115 Cleanup some problems with LLVM_ENABLE_DUMP in release builds, and
always set LLVM_ENABLE_DUMP=ON for +Asserts builds.

Differential Revision: https://reviews.llvm.org/D38306

llvm-svn: 314346
2017-09-27 21:19:56 +00:00
Simon Pilgrim a932bfcc93 Use const where possible. NFCI.
llvm-svn: 314292
2017-09-27 10:03:17 +00:00
Simon Pilgrim 40687014ea Tidyup P->getComplexPatternInfo call by moving it inside if( != NULL) test. NFCI.
llvm-svn: 314202
2017-09-26 12:59:01 +00:00
Krzysztof Parzyszek 7725e497d1 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

Recommitting r313989 with the fix for unresolved references: explicitly
define the operator<< in namespace llvm.

llvm-svn: 314004
2017-09-22 18:29:37 +00:00
Simon Pilgrim 8c4d061562 Remove trailing whitespace. NFCI.
llvm-svn: 313996
2017-09-22 16:57:28 +00:00
Krzysztof Parzyszek 9b64c51739 Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"
This reverts commit r313989: it breaks Windows bots.

llvm-svn: 313990
2017-09-22 16:18:35 +00:00
Krzysztof Parzyszek d55727e873 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

llvm-svn: 313989
2017-09-22 16:06:35 +00:00
Simon Pilgrim 6f05a743f7 [TableGen] Return StringRef from ValueTypeByHwMode::getMVTName
Avoid unnecessary std::string creations during TypeSetByHwMode::writeToStream.

Found during investigations into PR28222

Differential Revision: https://reviews.llvm.org/D38174

llvm-svn: 313983
2017-09-22 13:32:26 +00:00
Zachary Turner 0aa02c08a7 Resubmit "[lit] Refactor out some more common lit configuration code."
There were two issues, one Python 3 specific related to Unicode,
and another which is that the tool substitution for lld no longer
rejected matches where a / preceded the tool name.

llvm-svn: 313928
2017-09-21 22:16:40 +00:00
Zachary Turner 5f2fd9b783 Revert "[lit] Refactor out some more common lit configuration code."
This is breaking several bots.  I have enough information to
investigate, so I'm reverting to green until I get it figured
out.

llvm-svn: 313922
2017-09-21 21:45:45 +00:00
Zachary Turner 0d36b657b9 [lit] Refactor out some more common lit configuration code.
debuginfo-tests has need to reuse a lot of common configuration
from clang and lld, and in general it seems like all of the
projects which are tightly coupled (e.g. lld, clang, llvm, lldb,
etc) can benefit from knowing about one other.  For example,
lldb needs to know various things about how to run clang in its
test suite.  Since there's a lot of common substitutions and
operations that need to be shared among projects, sinking this
up into LLVM makes sense.

In addition, this patch introduces a function add_tool_substitution
which handles all the dirty intricacies of matching tool names
which was previously copied around the various config files.  This
is now a simple straightforward interface which is hard to mess
up.

Differential Revision: https://reviews.llvm.org/D37944

llvm-svn: 313919
2017-09-21 21:27:31 +00:00
Zachary Turner 1ca789bdba [lit] Actually do normalize the case of files in the config map.
This has gone back and forth, but it seems this is necessary
after all.  realpath is not sufficient because if you have a
file named 'C:\foo.txt', then both realpath('c:\foo.txt') and
realpath(C:\foo.txt') return the string that was passed to them
exactly as is, meaning the case of the drive-letter won't match.

The problem before was not that we were normalizing the case of
items going into the config map, but rather that we were
normalizing the case of something we needed to print.  The value
that is used to key on the config map should never be printed.

llvm-svn: 313918
2017-09-21 21:27:11 +00:00
Zachary Turner 43bcf226c1 [lit] Don't norm case when inserting into the config map.
This makes all paths lowercase on Windows, which seemed like a
good idea at the time, but it means that tests can't properly
use FileCheck to match expected path names.

llvm-svn: 313889
2017-09-21 17:02:08 +00:00
Zachary Turner 71deeee593 [lit] Add a test for the builtin config map.
Config map is not exposed through the command line, so testing this
is somewhat tricky.  But basically we need a test that if a custom
driver builds a config map and passes it to main, it gets respected.

A config map allows config files in the source tree to be mapped
to alternate config files in the build tree.  This particular test
works by having two config files in separate directories, and
setting up a config map to have that redirects A/lit.site.cfg
to B/altconfig.  Then, we print a message in A/lit.site.cfg
and B/altconfig and check that we do see the output from B
but don't see the output from A.  Additionally we test that
the test suite specified by A's config map is properly discovered.

Differential Revision: https://reviews.llvm.org/D38105

llvm-svn: 313887
2017-09-21 16:18:28 +00:00
Javed Absar 4b13bfd965 [TableGen] Tidy up CodeGenRegisters
Replacing range loops.

Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38091

llvm-svn: 313874
2017-09-21 10:51:47 +00:00
Craig Topper d022d25eb3 [TableGen] Use CHAR_BIT instead of hardcoded 8 with sizeof. NFC
llvm-svn: 313860
2017-09-21 04:55:04 +00:00
Craig Topper ddfdd9413a [TableGen] Include StringMap.h instead of StringSet.h since that's the data structure we use.
llvm-svn: 313859
2017-09-21 04:55:03 +00:00
David L. Jones e85a0eca21 [lit/Win] Check if a path was found before attempting to use it.
Summary:
This appears to break some bots, when getToolsPath fails to find some or
all of the tools (for example, an incomplete GnuWin32 installation).

Reviewers: zturner, modocache

Subscribers: sanjoy, llvm-commits

Differential Revision: https://reviews.llvm.org/D38115

llvm-svn: 313854
2017-09-21 01:26:16 +00:00
Zachary Turner 957d611575 [lit] Make lit support config files with .py extension.
Many editors and Python-related diagnostics tools such as
debuggers break or fail in mysterious ways when python files
don't end in .py.  This is especially true on Windows, but
still exists on other platforms.  I don't want to be too heavy
handed in changing everything across the board, but I do want
to at least *allow* lit configs to have .py extensions.  This
patch makes the discovery process first look for a config file
with a .py extension, and if one is not found, then looks for
a config file using the old method.  So for existing users, there
should be no functional change.

Differential Revision: https://reviews.llvm.org/D37838

llvm-svn: 313849
2017-09-21 00:24:52 +00:00
Zachary Turner 08fe808b3d [lit] Undo the patch to stop writing pyc files.
The problems on the bots appear to be resolved and this was
determined to not be the culprit.  Removing this.

llvm-svn: 313807
2017-09-20 20:31:24 +00:00
Zachary Turner 249dc14979 [TableGen] Some optimizations to TableGen.
This changes some STL data types to corresponding LLVM
data types that have better performance characteristics.

Differential Revision: https://reviews.llvm.org/D37957

llvm-svn: 313783
2017-09-20 18:01:40 +00:00
Zachary Turner 8978363735 [lit] Reverse path list when updating environment vars.
Bug pointed out by EricWF.  This would construct a path where
items would be added in the wrong order, potentially leading
to using the wrong tools for testing.

llvm-svn: 313765
2017-09-20 17:08:20 +00:00
Zachary Turner d3bb80a1bc Make lit stop writing pyc files.
Many svn-based buildbots seem to be getting stuck continually
in tree conflicts due to the output of pyc files.  I'm disabling
these as a temporary measure in an attempt to get everything
stable again.

I'll try to remove this code once I understand the problem
better.

llvm-svn: 313698
2017-09-19 23:50:28 +00:00
Craig Topper 7c1ef6cbdc [TableGen] Generate formatted DAGISelEmitter without relying on formatted_raw_ostream.
The generated DAG isel file currently makes use of formatted_raw_ostream primarily for generating a hierarchical representation while also skipping over the initial comment that contains the current index.

It was reported in D37957 that this formatting might be slow due to the need to keep track of column numbers by monitoring all the written data for new lines.

This patch attempts to rewrite the emitter to make use of simpler formatting mechanisms to generate a fairly similar output. The main difference is that the number in the index comment is now right justified and padded with spaces inside the comment. Previously we appended the spaces after the comment.

Differential Revision: https://reviews.llvm.org/D37966

llvm-svn: 313674
2017-09-19 21:03:57 +00:00
Krzysztof Parzyszek affd201967 Recommit r313647 now that GCC seems to accept the offering
Add some member types to MachineValueTypeSet::const_iterator so that
iterator_traits can work with it.

Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)

The introduction of parameterized register classes in r313271 caused the
matcher generation code in TableGen to run much slower, particularly so
in the unoptimized (debug) build. This patch recovers some of the lost
performance.

Summary of changes:
- Cache the set of legal types in TypeInfer::getLegalTypes. The contents
  of this set do not change.
- Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally
  this would not be necessary, but in the debug build TableGen is not
  optimized, so this helps a little bit.
- Add an early exit from TypeSetByHwMode::operator== for the case when
  one or both arguments are "simple", i.e. only have one mode. This
  saves some time in GenerateVariants.
- Finally, replace the underlying storage type in TypeSetByHwMode::SetType
  with MachineValueTypeSet based on std::array instead of std::set.
  This significantly reduces the number of memory allocation calls.

I've done a number of experiments with the underlying type of InfoByHwMode.
The type is a map, and for targets that do not use the parameterization,
this map has only one entry. The best (unoptimized) performance, somewhat
surprisingly came from std::map, followed closely by std::unordered_map.
DenseMap was the slowest by a large margin.
Various hand-crafted solutions (emulating enough of the map interface
not to make sweeping changes to the users) did not yield any observable
improvements.

llvm-svn: 313660
2017-09-19 18:42:34 +00:00
Krzysztof Parzyszek 16441a9831 Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)"
It breaks a lot of bots due to missing "__iterator_category".

llvm-svn: 313651
2017-09-19 17:55:07 +00:00
Krzysztof Parzyszek 1e166766c3 Move "(void)variable" closer to the assertion that uses it, NFC
llvm-svn: 313649
2017-09-19 17:47:53 +00:00
Krzysztof Parzyszek 02fa88e748 Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)
The introduction of parameterized register classes in r313271 caused the
matcher generation code in TableGen to run much slower, particularly so
in the unoptimized (debug) build. This patch recovers some of the lost
performance.

Summary of changes:
- Cache the set of legal types in TypeInfer::getLegalTypes. The contents
  of this set do not change.
- Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally
  this would not be necessary, but in the debug build TableGen is not
  optimized, so this helps a little bit.
- Add an early exit from TypeSetByHwMode::operator== for the case when
  one or both arguments are "simple", i.e. only have one mode. This
  saves some time in GenerateVariants.
- Finally, replace the underlying storage type in TypeSetByHwMode::SetType
  with MachineValueTypeSet based on std::array instead of std::set.
  This significantly reduces the number of memory allocation calls.

I've done a number of experiments with the underlying type of InfoByHwMode.
The type is a map, and for targets that do not use the parameterization,
this map has only one entry. The best (unoptimized) performance, somewhat
surprisingly came from std::map, followed closely by std::unordered_map.
DenseMap was the slowest by a large margin.
Various hand-crafted solutions (emulating enough of the map interface
not to make sweeping changes to the users) did not yield any observable
improvements.

llvm-svn: 313647
2017-09-19 17:32:35 +00:00
Daniel Sanders 28887fe548 [globalisel] Add support for intrinsic_w_chain.
This maps directly to G_INTRINSIC_W_SIDE_EFFECTS.

llvm-svn: 313627
2017-09-19 12:56:36 +00:00
Zachary Turner d1e5e35660 [lit] Use realpath when adding to the config map.
Since the path a user specifies to the llvm-lit script might be
different than the source tree they built from (since they could
be behind different symlinks), we need to use realpath to make
sure that path comparisons work as expected.

Even better would be to use a custom dictionary comparison with
actual file equivalence comparison semantics, but this is the
least friction to unbreak things for now.

llvm-svn: 313594
2017-09-18 23:36:35 +00:00
Zachary Turner bbf8f23ed9 Fix inverted regex search.
I was using the pattern as the source string and vice versa
causing strange regular expression errors.

llvm-svn: 313590
2017-09-18 23:14:15 +00:00
Zachary Turner fca1a34a11 [lit] Fix a Python 3 compatibility issue.
llvm-svn: 313580
2017-09-18 22:30:45 +00:00
Zachary Turner d4401d354a [lit] Update clang and lld to use new config helpers.
NFC intended here, this only updates clang and lld's lit configs
to use some helper functionality in the lit.llvm submodule.

llvm-svn: 313579
2017-09-18 22:26:48 +00:00
Benjamin Kramer e57308ecf0 Remove uses of deprecated std::not1.
Lambdas are slightly more verbose, but also more readable. No
functionality change intended.

llvm-svn: 313482
2017-09-17 11:19:53 +00:00
Zachary Turner b9fad9fd12 Try to fix some failing bots.
It doesn't make sense to me why these bots are failing as the
traceback does not agree with the source code.  It's possible
something is stale or there is some other mysterious error,
but in any case hopefully this fixes it.

llvm-svn: 313469
2017-09-16 19:20:53 +00:00
Zachary Turner c3023d1bd1 Resubmit "Add a shared llvm.lit module that all test suites can use."
There were some issues surrounding Py2 / Py3 compatibility, but
I've now tested with both Py2 and Py3 and everything seems to
work.

llvm-svn: 313467
2017-09-16 18:46:21 +00:00
Zachary Turner d6bca1c549 [lit] Fix some Python 3 compatibility issues.
llvm-svn: 313466
2017-09-16 18:45:44 +00:00
Zachary Turner f734daf36d [lit] Fix the lit unit tests.
A few tests were manually constructing a LitConfig object, since
I added a new argument to it this was triggering some failures
I didn't detect.  `ninja check-lit` passes now.

llvm-svn: 313461
2017-09-16 15:48:30 +00:00
Zachary Turner 42b6dcbcef [lit] Add a single process mode.
This is helpful for debugging test failures since it removes
the multiprocessing pool from the picture.  This will obviously
slow down the test suite by a few orders of magnitude, so it
should only be used for debugging specific failures.

llvm-svn: 313460
2017-09-16 15:31:34 +00:00
Chandler Carruth 309f360240 [git] Update the llvm git helper script to work correctly with the
latest Python versions.

llvm-svn: 313435
2017-09-16 02:13:35 +00:00
Zachary Turner 525b09d347 Revert lit changes related to lit.llvm module.
It looks like this is going to be non-trivial to get working
in both Py2 and Py3, so for now I'm reverting until I have time
to fully test it under Python 3.

llvm-svn: 313429
2017-09-16 00:52:49 +00:00
Zachary Turner 245a0beb3b [lit] Fix another Python 3 error.
Apparently we have a buildbot running Python 3.  This is going
to be fun :-/

llvm-svn: 313428
2017-09-16 00:43:16 +00:00
Zachary Turner 712ffde369 [lit] Better check for integral value.
Some versions of python don't have 'long'.  Use numbers.Number
instead.

llvm-svn: 313427
2017-09-16 00:38:20 +00:00
Zachary Turner 2aa5a92bdb Resubmit "[lit] Add a lit.llvm module that all llvm projects can use"
This was reverted alongside the revert of the lit/llvm-lit refactor,
but now that that has re-landed, I'm relanding this as well.

llvm-svn: 313426
2017-09-16 00:25:58 +00:00
Zachary Turner ce92db13ea Resubmit "[lit] Force site configs to run before source-tree configs"
This is a resubmission of r313270.  It broke standalone builds of
compiler-rt because we were not correctly generating the llvm-lit
script in the standalone build directory.

The fixes incorporated here attempt to find llvm/utils/llvm-lit
from the source tree returned by llvm-config.  If present, it
will generate llvm-lit into the output directory.  Regardless,
the user can specify -DLLVM_EXTERNAL_LIT to point to a specific
lit.py on their file system.  This supports the use case of
someone installing lit via a package manager.  If it cannot find
a source tree, and -DLLVM_EXTERNAL_LIT is either unspecified or
invalid, then we print a warning that tests will not be able
to run.

Differential Revision: https://reviews.llvm.org/D37756

llvm-svn: 313407
2017-09-15 22:10:46 +00:00
Krzysztof Parzyszek 89291f2ac8 Fix selecting legal types in TypeInfer::getLegalTypes
Collect all legal types for all modes.

llvm-svn: 313380
2017-09-15 18:58:07 +00:00
Ilya Biryukov 8b62e0887d Added optional validation of svn sources to Dockerfiles.
Summary: This commit also adds a script to compute sha256 hashes of llvm checkouts.

Reviewers: klimek, mehdi_amini

Reviewed By: klimek

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37099

llvm-svn: 313359
2017-09-15 13:35:54 +00:00
Zachary Turner 83dcb68468 Revert "[lit] Force site configs to run before source-tree configs"
This patch is still breaking several multi-stage compiler-rt bots.
I already know what the fix is, but I want to get the bots green
for now and then try re-applying in the morning.

llvm-svn: 313335
2017-09-15 02:56:40 +00:00
Tom Stellard a9191b55bb merge-request.sh: Update to use new "Fixed by Commit(s)" field
Summary:
This will be used instead of the url field to track which commits need
to be merged.

This patch also drops support for version 1.x of the bugzilla CLI tool.

Reviewers: hansw, hans

Reviewed By: hans

Subscribers: hans, llvm-commits

Differential Revision: https://reviews.llvm.org/D37786

llvm-svn: 313334
2017-09-15 02:25:22 +00:00
Zachary Turner 7f9c0ce1bb [lit] Revert "Add a lit.llvm module that all llvm projects can use"
This is breaking due to some changes I forgot to merge in, so I'm
temporarily reverting them until I can re-test that this works.

llvm-svn: 313328
2017-09-15 00:56:08 +00:00
Zachary Turner 247b3c1f48 [lit] Remove some code that I forgot to remove.
llvm-svn: 313326
2017-09-15 00:43:38 +00:00
Zachary Turner e5412b882a [lit] Add a lit.llvm module that all test suites can use.
To further reduce duplicate code, this patch introduces a module
that configs can simply import and get access to a lot of useful
functionality such as setting up paths, adding features that are
useful across all projects, and other utility-type functions.

For now this only updates llvm's suite to use this new library,
but subsequent patches will update other projects.

Differential Revision: https://reviews.llvm.org/D37778

llvm-svn: 313325
2017-09-15 00:34:00 +00:00
Zachary Turner d8f68bb598 [lit] Fix some windows line endings that snuck in.
llvm-svn: 313301
2017-09-14 21:32:13 +00:00
Krzysztof Parzyszek 788e768ffd Subtarget support for parameterized register class information
Implement "checkFeatures" and emitting HW mode check code.

Differential Revision: https://reviews.llvm.org/D31959

llvm-svn: 313295
2017-09-14 20:44:20 +00:00
Benjamin Kramer 591aac7cdf Remove usages of deprecated std::unary_function and std::binary_function.
These are removed in C++17. We still have some users of
unary_function::argument_type, so just spell that typedef out. No
functionality change intended.

Note that many of the argument types are actually wrong :)

llvm-svn: 313287
2017-09-14 18:33:25 +00:00
Krzysztof Parzyszek a8daf1747c Silence warning about unused variable in release build
llvm-svn: 313273
2017-09-14 17:08:26 +00:00
Krzysztof Parzyszek 779d98e1c0 TableGen support for parameterized register class information
This replaces TableGen's type inference to operate on parameterized
types instead of MVTs, and as a consequence, some interfaces have
changed:
- Uses of MVTs are replaced by ValueTypeByHwMode.
- EEVT::TypeSet is replaced by TypeSetByHwMode.

This affects the way that types and type sets are printed, and the
tests relying on that have been updated.

There are certain users of the inferred types outside of TableGen
itself, namely FastISel and GlobalISel. For those users, the way
that the types are accessed have changed. For typical scenarios,
these replacements can be used:
- TreePatternNode::getType(ResNo) -> getSimpleType(ResNo)
- TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo)
- TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false)

For more information, please refer to the review page.

Differential Revision: https://reviews.llvm.org/D31951

llvm-svn: 313271
2017-09-14 16:56:21 +00:00