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5 Commits

Author SHA1 Message Date
Dinar Temirbulatov aead31a36f [X86] SET0 to use XMM registers where possible PR26018 PR32862 
Differential Revision: https://reviews.llvm.org/D35839

llvm-svn: 309298
 2017-07-27 17:47:01 +00:00
Simon Pilgrim 106307aa13 [X86][AVX] Regenerated and cleaned up AVX1 intrinsic tests. 
Cleaned up triple settings, added 32-bit/64-bit targets where useful, added broadcast comments

llvm-svn: 309100
 2017-07-26 10:54:51 +00:00
Craig Topper d788498411 [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1. 
llvm-svn: 268871
 2016-05-08 07:10:47 +00:00
Simon Pilgrim 726622394f [X86][AVX] Regenerated AVX tests 
Updated i1 select, vector truncation and subvector extraction tests

llvm-svn: 257995
 2016-01-16 15:25:02 +00:00
Bruno Cardoso Lopes 72323966c8 Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556 
llvm-svn: 137179
 2011-08-09 23:27:13 +00:00