Commit Graph

8 Commits

Author SHA1 Message Date
Erich Keane 521ed960ed Correct Vectorcall Register passing and HVA Behavior
Front end component (back end changes are D27392).  The vectorcall 
calling convention was broken subtly in two cases.  First, 
it didn't properly handle homogeneous vector aggregates (HVAs). 
Second, the vectorcall specification requires that only the 
first 6 parameters be eligible for register assignment. 
This patch fixes both issues.

Differential Revision: https://reviews.llvm.org/D27529

llvm-svn: 291041
2017-01-05 00:20:51 +00:00
Vedant Kumar f8e09c3bb6 [test] Fix typos in a few tests (NFC)
Patch by Kai Zhao!

llvm-svn: 245817
2015-08-23 18:53:59 +00:00
David Blaikie a953f2825b Update Clang tests to handle explicitly typed load changes in LLVM.
llvm-svn: 230795
2015-02-27 21:19:58 +00:00
Eric Christopher 560cc4fb44 Make sure that arm-linux-gnu is still the apcs-gnu ABI when we
use clang -cc1 matching the front end and backend. Fix up a couple
of tests that were testing aapcs for arm-linux-gnu.

The test that removes the aapcs abi calling convention removes
them because the default triple matches what the backend uses
for the calling convention there and so it doesn't need to be
explicitly stated - see the code in TargetInfo.cpp.

llvm-svn: 224491
2014-12-18 02:08:55 +00:00
Tim Northover b047bfae32 AArch64: simplify PCS mapping.
Now that LLVM can count the registers needed to implement AAPCS rules, we don't
need to duplicate that logic here. This means we can drop the explicit padding
and also use more natural types in many cases (e.g. "struct { float arr[3]; }"
used to end up as "[2 x double]" to avoid holes on the stack.

The one wrinkle is that AAPCS va_arg was also using the register counting
machinery. But the local replacement isn't too bad.

llvm-svn: 222904
2014-11-27 21:02:49 +00:00
Tim Northover 5a1558ec31 ARM ABI: simplify decisions on whether args can be expanded.
Homogeneous aggregates on AAPCS_VFP ARM need to be passed *without* being
flattened (e.g. [2 x float] rather than "float, float") for various weird ABI
reasons. However, this isn't the case for anything else; further, we know at
the ABIArgInfo::getDirect callsites whether this flattening is allowed.

So, we can get more unified ARM code, with a simpler Clang, by just using that
knowledge directly.

llvm-svn: 221559
2014-11-07 22:30:50 +00:00
Reid Kleckner 80944df6f4 Implement IRGen for the x86 vectorcall convention
The most complex aspect of the convention is the handling of homogeneous
vector and floating point aggregates.  Reuse the homogeneous aggregate
classification code that we use on PPC64 and ARM for this.

This convention also has a C mangling, and we apparently implement that
in both Clang and LLVM.

Reviewed By: majnemer

Differential Revision: http://reviews.llvm.org/D6063

llvm-svn: 221006
2014-10-31 22:00:51 +00:00
Reid Kleckner e9f6a717dd Fix ARM HVA classification of classes with non-virtual bases
Reuse the PPC64 HVA detection algorithm for ARM and AArch64. This is a
nice code deduplication, since they are roughly identical. A few virtual
method extension points are needed to understand how big an HVA can be
and what element types it can have for a given architecture.

Also make the record expansion code work in the presence of non-virtual
bases.

Reviewed By: uweigand, asl

Differential Revision: http://reviews.llvm.org/D6045

llvm-svn: 220972
2014-10-31 17:10:41 +00:00