fbd67be50e
Don't prepend a space character for constants in Value::print.
...
llvm-svn: 56920
2008-10-01 15:09:37 +00:00
3a293e7404
Fix typos in comments.
...
llvm-svn: 56919
2008-10-01 15:07:49 +00:00
96740aad86
revert the addition of Preverves(CallGraph), per Duncan's comments
...
llvm-svn: 56917
2008-10-01 09:13:40 +00:00
bb3c5019f8
Mark CALL instructions as having a Use of ESP/RSP.
...
llvm-svn: 56911
2008-10-01 04:14:30 +00:00
67d90de2b0
Call ScalarEvolution's deleteValueFromRecords before deleting an
...
instruction, not after. This fixes some uses of free'd memory.
llvm-svn: 56908
2008-10-01 02:02:03 +00:00
68f12ee567
Implement the -fno-builtin option in the front-end, not in the back-end.
...
llvm-svn: 56900
2008-10-01 00:59:58 +00:00
15e6be8cc5
Mark merged-in VNInfo's as being PHIKilled.
...
llvm-svn: 56893
2008-09-30 23:58:47 +00:00
f4a36407c7
Fix a simple error in renumbering kill markaers, that took an inordinant amount of time to track down.
...
llvm-svn: 56889
2008-09-30 22:51:54 +00:00
1782584f56
Just don't transform this memset into "bzero" if no-builtin is specified.
...
llvm-svn: 56888
2008-09-30 22:05:33 +00:00
5093ab4c76
add preserversCFG() + preservers(CallGraph)
...
llvm-svn: 56887
2008-09-30 22:04:30 +00:00
e818bc159f
- Initialize "--no-builtin" to "false".
...
- Testcase for r56885.
llvm-svn: 56886
2008-09-30 21:40:30 +00:00
bd09262e97
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
...
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
llvm-svn: 56885
2008-09-30 21:22:07 +00:00
b486350b15
Move the primary fast-isel top-level comments to FastISel.cpp, where
...
they'll be a little more visible. Also, update and reword them a bit.
llvm-svn: 56877
2008-09-30 20:48:29 +00:00
2bd7b24f1a
add AU.setPreservesCFG() since this pass only adds and removes function attributes
...
llvm-svn: 56868
2008-09-30 18:34:38 +00:00
86aa16a69a
Optimize SelectionDAG's AssignTopologicalOrder even further.
...
Completely eliminate the TopOrder std::vector. Instead, sort
the AllNodes list in place. This also eliminates the need to
call AllNodes.size(), a linear-time operation, before
performing the sort.
Also, eliminate the Sources temporary std::vector, since it
essentially duplicates the sorted result as it is being
built.
This also changes the direction of the topological sort
from bottom-up to top-down. The AllNodes list starts out in
roughly top-down order, so this reduces the amount of
reordering needed. Top-down is also more convenient for
Legalize, and ISel needed only minor adjustments.
llvm-svn: 56867
2008-09-30 18:30:35 +00:00
1a9a0b7b4e
Add runStaticConstructorsDestructors which runs ctors / dtors of a single module. Patch by David Chisnall.
...
llvm-svn: 56849
2008-09-30 15:51:21 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
...
llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
...
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
...
llvm-svn: 56835
2008-09-30 06:36:58 +00:00
e8ced3ec19
Fix misoptimization of: xor i1 (icmp eq (X, C1), icmp s[lg]t (X, C2))
...
llvm-svn: 56834
2008-09-30 06:08:34 +00:00
8392f0c75d
Fix X86FastISel's output for x86-32 PIC constant pool addresses.
...
llvm-svn: 56829
2008-09-30 01:21:32 +00:00
6ebe734ca6
Move the GlobalBaseReg field out of X86ISelDAGToDAG.cpp
...
and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.
llvm-svn: 56825
2008-09-30 00:58:23 +00:00
5033136825
Disable all x87 usage, including f32 and f64 when the subtarget
...
doesn't have SSE(2), with X86FastISel.
llvm-svn: 56823
2008-09-30 00:48:39 +00:00
f61a84ec43
Remove misuse of ReplaceNodeResults for atomics with
...
valid types. No functional change.
llvm-svn: 56808
2008-09-29 22:25:26 +00:00
4aa9095398
Fix FastISel to not initialize the PIC-base register multiple times
...
in functions with PIC references from more than one basic block.
llvm-svn: 56807
2008-09-29 21:55:50 +00:00
c02dbf451e
Fix an over-pessimization about GlobalVariable addresses in X86FastISel.
...
llvm-svn: 56802
2008-09-29 21:13:15 +00:00
221fe42006
Support inreg, zext and sext as return value attributes.
...
llvm-svn: 56801
2008-09-29 20:49:50 +00:00
82237f2f42
Fix PR2835. Do not change the width of a volatile load.
...
llvm-svn: 56792
2008-09-29 17:26:18 +00:00
57512a1be4
Speed up these passes when the callgraph has
...
huge simply connected components. Suggested
by Chris.
llvm-svn: 56787
2008-09-29 14:59:04 +00:00
ffc9da6772
remove redundant test (mayBeOverriden() includes hasLinkOnceLinkage)
...
llvm-svn: 56786
2008-09-29 14:40:32 +00:00
e340e18783
Tweak some comments.
...
llvm-svn: 56784
2008-09-29 13:35:31 +00:00
08d91178e9
Rename isWeakForLinker to mayBeOverridden. Use it
...
instead of hasWeakLinkage in a bunch of optimization
passes.
llvm-svn: 56782
2008-09-29 11:25:42 +00:00
3774b2f292
Re-apply 56683 with fixes.
...
llvm-svn: 56748
2008-09-27 01:56:22 +00:00
1d5e766016
Unbreak build.
...
llvm-svn: 56727
2008-09-27 00:22:09 +00:00
9eb525d4f9
Implement function notes as function attributes.
...
llvm-svn: 56716
2008-09-26 23:51:19 +00:00
c4b02eb4e5
Generated files for warning fix.
...
llvm-svn: 56715
2008-09-26 23:46:20 +00:00
e2ea91e7cb
Fix a compiler warning.
...
llvm-svn: 56714
2008-09-26 23:45:53 +00:00
7d6fa97567
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
...
llvm-svn: 56711
2008-09-26 23:41:32 +00:00
a05633e105
Now Attributes are divided in three groups
...
- return attributes - inreg, zext and sext
- parameter attributes
- function attributes - nounwind, readonly, readnone, noreturn
Return attributes use 0 as the index.
Function attributes use ~0U as the index.
This patch requires corresponding changes in llvm-gcc and clang.
llvm-svn: 56704
2008-09-26 22:53:05 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
5628f642ad
Fix missing whitespace in the printing of function notes.
...
llvm-svn: 56702
2008-09-26 22:02:59 +00:00
6e0548336a
Rename ConstantSDNode's getSignExtended to getSExtValue, for
...
consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.
llvm-svn: 56700
2008-09-26 21:54:37 +00:00
7e922aa35d
Mark lea fi# as being really rematerializable.
...
llvm-svn: 56698
2008-09-26 21:30:20 +00:00
30f5494efb
unpckhps requires sse1, punpckhdq requires sse2.
...
llvm-svn: 56697
2008-09-26 21:26:30 +00:00
2564b900ce
Fix X86FastISel's address folding to check displacement
...
values for overflow.
llvm-svn: 56686
2008-09-26 20:04:15 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
...
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
9e3f7dbeda
CMake: Builds all examples. Corrected name of CBackend target.
...
llvm-svn: 56682
2008-09-26 19:48:03 +00:00
c0f4d00d67
Generated files for previous patch.
...
llvm-svn: 56679
2008-09-26 19:32:34 +00:00
a7dd8bfaa5
Another file I forgot.
...
llvm-svn: 56678
2008-09-26 19:31:53 +00:00
0e32a2c935
Add "inreg" field to CallSDNode (doesn't increase
...
its size). Adjust various lowering functions to
pass this info through from CallInst. Use it to
implement sseregparm returns on X86. Remove
X86_ssecall calling convention.
llvm-svn: 56677
2008-09-26 19:31:26 +00:00
007a6bb9b9
Factor out the code for determining when symblic addresses
...
require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.
llvm-svn: 56676
2008-09-26 19:15:30 +00:00
994dd0bbec
Avoid spilling EBP / RBP twice in the prologue.
...
llvm-svn: 56675
2008-09-26 19:14:21 +00:00
a381313d98
We don't need to insert copies for implicit_def's.
...
llvm-svn: 56674
2008-09-26 18:50:46 +00:00
001ffdd36b
X86 address displacement field must be interpreted as a 32-bit value.
...
llvm-svn: 56665
2008-09-26 16:58:16 +00:00
cdc95498f5
CMake: Builds all targets.
...
llvm-svn: 56641
2008-09-26 04:40:32 +00:00
839105d254
Disable support for x86_f80 in X86FastISel. Supporting it would
...
require more work.
llvm-svn: 56637
2008-09-26 01:39:32 +00:00
374d7f2b16
If we have a function with an unreachable statement such that the ending debug
...
information is in an unreachable block, then it's possible that the high/low pc
values won't be set for the dwarf information. E.g., this function:
void abort(void) __attribute__((__noreturn__));
void dead_beef(void) __attribute__ ((noreturn));
int *b;
void dead_beef(void) {
*b=0xdeadbeef;
abort();
}
has a call to "@llvm.dbg.region.end" only in the unreachable block:
define void @dead_beef() noreturn nounwind {
entry:
call void @llvm.dbg.func.start(...)
call void @llvm.dbg.stoppoint(...)
...
call void @abort( ) noreturn nounwind
unreachable
return: ; No predecessors!
call void @llvm.dbg.stoppoint(...)
call void @llvm.dbg.region.end(...)
ret void
}
The dwarf information emitted is something like:
0x00000084: TAG_subprogram [5]
AT_name( "dead_beef" )
AT_external( 0x01 )
AT_prototyped( 0x01 )
AT_decl_file( 0x01 )
AT_decl_line( 0x08 )
Note that this is *not* the best fix for this problem, but a band-aid for an
gaping wound. This code needs to be changed when we revamp our debugging
information.
llvm-svn: 56628
2008-09-26 00:28:12 +00:00
9dbe45c000
Prefer movlhps over punpcklqdq, etc. in more cases.
...
llvm-svn: 56627
2008-09-25 23:35:16 +00:00
0c1b884df1
Fix a bug in which address displacements were being added to the
...
load from the stub, instead of the result of the load from the stub.
llvm-svn: 56626
2008-09-25 23:34:02 +00:00
0c37421623
Make pointer parameter const for isUsedInBasicBlock.
...
llvm-svn: 56625
2008-09-25 22:42:01 +00:00
4c758ea3e0
Large mechanical patch.
...
s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g
This sets the stage
- to implement function notes as function attributes and
- to distinguish between function attributes and return value attributes.
This requires corresponding changes in llvm-gcc and clang.
llvm-svn: 56622
2008-09-25 21:00:45 +00:00
87001fd6fd
Reapply 56585:56589 with proper fix for some gcc versions
...
llvm-svn: 56621
2008-09-25 21:00:33 +00:00
74c9ed91b0
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
...
llvm-svn: 56620
2008-09-25 20:50:48 +00:00
c50ada2f56
Accept 'inreg' attribute on x86 functions as
...
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0). Update documentation
to reflect reality.
llvm-svn: 56619
2008-09-25 20:47:45 +00:00
bb9a211530
Avoid a spurious extra space character when printing empty structs.
...
llvm-svn: 56616
2008-09-25 17:37:20 +00:00
5e490a7567
Support for i1 XOR in FastISel. It is actually safe because
...
i1 operands are assumed to already by zero-extended.
llvm-svn: 56615
2008-09-25 17:22:52 +00:00
6975c36c43
Don't print fast-isel debug messages by default. Thanks Chris!
...
llvm-svn: 56614
2008-09-25 17:21:42 +00:00
dd920bf3f0
Don't forget the newline in debug output.
...
llvm-svn: 56613
2008-09-25 17:17:27 +00:00
32a733e2c7
FastISel support for debug info.
...
llvm-svn: 56610
2008-09-25 17:05:24 +00:00
4b35e64504
bug 2812: Segmentation fault on a big emdiam processor.
...
llvm-svn: 56609
2008-09-25 16:15:10 +00:00
3691d507c4
PIC support in X86FastISel.
...
llvm-svn: 56608
2008-09-25 15:24:26 +00:00
84301390ae
Temporarily backing out 56585:56589 to unbreak the build.
...
llvm-svn: 56607
2008-09-25 07:38:08 +00:00
3663f156f7
Fix a recent fast-isel coverage regression - don't bail out before
...
giving the target a chance to materialize constants.
llvm-svn: 56605
2008-09-25 01:28:51 +00:00
b8e69f1755
Enable DeadMachineInstructionElim when Fast-ISel is enabled.
...
llvm-svn: 56604
2008-09-25 01:14:49 +00:00
b873aa632c
Add debug output to this pass.
...
llvm-svn: 56602
2008-09-25 01:06:50 +00:00
7b5a6afb44
pmovsxbq etc. requires sse4.1.
...
llvm-svn: 56600
2008-09-25 00:49:51 +00:00
acb0554842
Refactor the code that adds standard LLVM codegen passes into
...
a separate function, eliminating duplication between the
add-passes-for-file and add-passes-for-machine-code code.
llvm-svn: 56599
2008-09-25 00:37:07 +00:00
2e7450716a
<rdar://problem/6234798> Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")
...
llvm-svn: 56597
2008-09-25 00:14:04 +00:00
382e2ec6b7
Give LowerSubregs.cpp a top-level description.
...
llvm-svn: 56596
2008-09-24 23:44:12 +00:00
f8ead16b50
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
...
llvm-svn: 56594
2008-09-24 23:27:55 +00:00
4751549f9b
X86ISD::VZEXT_LOAD should produce and fold a chain.
...
llvm-svn: 56593
2008-09-24 23:26:36 +00:00
86d421df23
Remove SelectionDag early allocation of registers
...
for earlyclobbers. Teach Local RA about earlyclobber,
and add some tests for it.
llvm-svn: 56592
2008-09-24 23:13:09 +00:00
3097c10347
Minor cleanup
...
llvm-svn: 56588
2008-09-24 22:22:54 +00:00
a9163feefe
Get rid of virtual inheritance for ARM TAI
...
llvm-svn: 56587
2008-09-24 22:22:27 +00:00
237f087eb9
Get rid of virtual inheritance for PPC TAI
...
llvm-svn: 56586
2008-09-24 22:22:03 +00:00
77aa975bdd
Use crazy template-based inheritance instead of virtual one.
...
llvm-svn: 56585
2008-09-24 22:21:39 +00:00
fd7faecfc2
Use helper
...
llvm-svn: 56584
2008-09-24 22:21:04 +00:00
d19e91e5a8
SmallPtrSet will be better
...
llvm-svn: 56583
2008-09-24 22:20:46 +00:00
8e7b93938d
Get rid of ReadOnlySection duplicate
...
llvm-svn: 56582
2008-09-24 22:20:27 +00:00
91a6705839
Use named sections, where they should be
...
llvm-svn: 56581
2008-09-24 22:19:13 +00:00
5906234c1d
Get rid of now unused {Four,Eight,Sixteen}ByteConstantSection
...
llvm-svn: 56580
2008-09-24 22:18:54 +00:00
123afb88c4
Use generic section-handling stuff to emit constant pool entries
...
llvm-svn: 56579
2008-09-24 22:17:59 +00:00
41573b2131
Cleanup
...
llvm-svn: 56578
2008-09-24 22:17:27 +00:00
22db30548d
Get rid of duplicate char*/Section* stuff for TLS sections
...
llvm-svn: 56577
2008-09-24 22:17:06 +00:00
1f365bbf55
Cleanup, no functionality change
...
llvm-svn: 56576
2008-09-24 22:16:33 +00:00
7497762606
Get rid of duplicate char*/Section* DataSection
...
llvm-svn: 56575
2008-09-24 22:16:16 +00:00
f8dc8aac3c
Get rid of duplicate char*/Section* TextSection
...
llvm-svn: 56574
2008-09-24 22:15:21 +00:00
076e905b94
Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.
...
llvm-svn: 56573
2008-09-24 22:14:23 +00:00
69ff51baa0
Drop obsolete hook and change all usage to new interface
...
llvm-svn: 56572
2008-09-24 22:13:07 +00:00
7d002fa77b
Provide direct function to switch to Section
...
llvm-svn: 56571
2008-09-24 22:12:10 +00:00
8ac1127ed6
SPU section handling is really huge mess. Replace remaining TAI calls for sections with explicit names in order not to block existing backends during section handling migration. SPU folks! Please consider using new section handling facility someday.
...
llvm-svn: 56570
2008-09-24 22:11:42 +00:00
69721aa85c
Remove dead code for PIC16 (preparation to switch to new section handling stuff)
...
llvm-svn: 56569
2008-09-24 22:11:26 +00:00
ffecb087a3
XMM6-XMM15 are callee-saved on Win64. Patch by Nicolas Capens!
...
llvm-svn: 56568
2008-09-24 22:03:04 +00:00
4ef4b1a7c1
Fix off-by-one error when updating live intervals.
...
llvm-svn: 56567
2008-09-24 21:30:38 +00:00
cdc0060e27
Add DisableGVCompilation which forces the JIT to assert when it tries to allocate space for a GlobalVariable.
...
llvm-svn: 56557
2008-09-24 16:25:55 +00:00
dea91308ae
Reapplying r56550
...
llvm-svn: 56553
2008-09-24 10:25:02 +00:00
162c26dee3
Forgot this part with my last patch. Sorry about the breakage.
...
llvm-svn: 56552
2008-09-24 10:16:24 +00:00
4e26a81371
Temporarily revert r56550 until missing commit can be added.
...
llvm-svn: 56551
2008-09-24 08:30:44 +00:00
7c31464a0b
Refactor the constant folding code into it's own function. And call it from both
...
the SelectionDAG and DAGCombiner code. The only functionality change is that now
the DAG combiner is performing the constant folding for these operations instead
of being a no-op.
This is *not* in response to a bug, so there isn't a testcase.
llvm-svn: 56550
2008-09-24 07:11:26 +00:00
25dd4a2daf
Commit CodeGenPrepare.cpp changes which was accidentially left out of 56526.
...
llvm-svn: 56549
2008-09-24 06:48:55 +00:00
c1ea149dcd
Fix fallout in CodeGenPrepare from 56526. Will likely need more work.
...
llvm-svn: 56546
2008-09-24 05:32:41 +00:00
a867337344
Fix fallout from revision r56535.
...
llvm-svn: 56545
2008-09-24 04:55:49 +00:00
ace327af3e
CMake: Lists of source files updated. Removed bogus dependency from
...
lib/VMCore/CMakeLists.txt
llvm-svn: 56541
2008-09-24 01:58:12 +00:00
c36660d756
Next round of earlyclobber handling. Approach the
...
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.
llvm-svn: 56539
2008-09-24 01:07:17 +00:00
6402c7236f
s/ParamAttrsWithIndex/FnAttributeWithIndex/g
...
llvm-svn: 56535
2008-09-24 00:55:02 +00:00
0009505a25
s/ParamAttributeListImpl/AttributeListImpl/g
...
llvm-svn: 56532
2008-09-24 00:29:49 +00:00
6b33aa4d96
Refactor the logic for testing if an instruction is dead into a
...
separate method.
llvm-svn: 56531
2008-09-24 00:27:38 +00:00
1e2b282be3
Set SetStore to false, to allow this pass to delete
...
dead loads.
llvm-svn: 56529
2008-09-24 00:07:08 +00:00
7c59ed6ff8
Add a method to MachineInstr for testing whether it makes
...
any volatile memory references.
llvm-svn: 56528
2008-09-24 00:06:15 +00:00
e15607b7bb
Put FN_NOTE_AlwaysInline and others in FnAttr namespace.
...
llvm-svn: 56527
2008-09-24 00:06:15 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
e87abd26ba
Move FN_NOTE_AlwaysInline and other out of ParamAttrs namespace.
...
Do not check isDeclaration() in hasNote(). It is clients' responsibility.
llvm-svn: 56524
2008-09-23 23:52:03 +00:00
f405b5e532
80 cols
...
llvm-svn: 56521
2008-09-23 23:32:15 +00:00
a987d3e3fb
s/ParameterAttributes/Attributes/g
...
llvm-svn: 56520
2008-09-23 23:25:44 +00:00
ba3fa6c6e1
s/ParameterAttributes/Attributes/g
...
llvm-svn: 56513
2008-09-23 23:03:40 +00:00
82fed6702b
Use parameter attribute store (soon to be renamed) for
...
Function Notes also. Function notes are stored at index ~0.
llvm-svn: 56511
2008-09-23 22:35:17 +00:00
676145f02d
Now that DeadMachineInstructionElim is basically working
...
correctly, it's not necessary to explicitly remove registers
from their use-def lists.
llvm-svn: 56509
2008-09-23 22:04:18 +00:00
918fe08a56
Arrange for FastISel code to have access to the MachineModuleInfo
...
object. This will be needed to support debug info.
llvm-svn: 56508
2008-09-23 21:53:34 +00:00
269999cb03
Track local physical register liveness. This is not the most
...
efficient implementation possible, but it's pretty simple and
good enough for the time being.
llvm-svn: 56504
2008-09-23 21:40:44 +00:00
4f6646780e
regenerate
...
llvm-svn: 56502
2008-09-23 21:18:31 +00:00
7f0a77f11d
allow inreg on the result of a function
...
llvm-svn: 56501
2008-09-23 21:18:08 +00:00
c07f686665
Replace the LiveRegs SmallSet with a simple counter that keeps
...
track of the number of live registers, which is all the set was
being used for.
llvm-svn: 56498
2008-09-23 18:50:48 +00:00
ed1cf1a8f1
Fix these enums' starting values to reflect the way that
...
instruction opcodes are now numbered. No functionality change.
llvm-svn: 56497
2008-09-23 18:42:32 +00:00
e64c9944f6
Delete an unused function.
...
llvm-svn: 56495
2008-09-23 18:26:47 +00:00
2430073657
Move the code for initializing the global base reg out of
...
X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow
it to be reused by FastISel.
llvm-svn: 56494
2008-09-23 18:22:58 +00:00
9c40c28926
Rationalize the names of passes that print information:
...
-callgraph => print-callgraph
-callscc => print-callgraph-sccs
-cfgscc => print-cfg-sccs
-externalfnconstants => print-externalfnconstants
-print => print-function
-print-alias-sets (no change)
-print-callgraph => dot-callgraph
-print-cfg => dot-cfg
-print-cfg-only => dot-cfg-only
-print-dom-info (no change)
-printm => print-module
-printusedtypes => print-used-types
llvm-svn: 56487
2008-09-23 12:47:39 +00:00
bdb215d338
Fix indendation.
...
llvm-svn: 56486
2008-09-23 08:54:41 +00:00
4cdc18ad80
Add initial support for inserting last minute copies.
...
llvm-svn: 56485
2008-09-23 04:37:10 +00:00
9e9426cb82
Support x86 specific inline asm modifier 'J'.
...
llvm-svn: 56483
2008-09-22 23:57:37 +00:00
e2947e1e07
Fix the alignment of loads from constant pool entries when the
...
load address has an offset from the base of the constant pool
entry.
llvm-svn: 56479
2008-09-22 22:40:08 +00:00
329fe728b5
Add hasNote() to check note associated with a function.
...
llvm-svn: 56477
2008-09-22 22:32:29 +00:00
bab5988017
Livestacks really does preserve everything.
...
llvm-svn: 56476
2008-09-22 22:26:15 +00:00
962c2cf17a
Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
...
llvm-svn: 56475
2008-09-22 22:21:38 +00:00
97364655dc
Significant improvements to the logic for merging live intervals. This code can't
...
just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.
llvm-svn: 56472
2008-09-22 21:58:58 +00:00
7a74e71489
Make log, log2, log10, exp, exp2 use Expand by
...
default.
llvm-svn: 56471
2008-09-22 21:57:32 +00:00
168f8f3916
Mark several codegen passes as preserving all analysis.
...
llvm-svn: 56469
2008-09-22 20:58:04 +00:00
f1acc4d610
More refactoring. Yawn.
...
llvm-svn: 56468
2008-09-22 20:51:30 +00:00
7beddb8680
Refactor FP intrinisic setup. Per review feedback.
...
llvm-svn: 56456
2008-09-22 19:51:58 +00:00
8807bddf08
CMake build system: support for parallel builds.
...
llvm-svn: 56453
2008-09-22 18:21:51 +00:00
13beeeb128
Per review feedback: Only perform
...
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.
llvm-svn: 56452
2008-09-22 18:19:24 +00:00
796a271c5f
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
...
llvm-svn: 56436
2008-09-22 14:50:07 +00:00
a229b3c9a7
Initial support for the CMake build system.
...
llvm-svn: 56419
2008-09-22 01:08:49 +00:00
91ef8fcd29
Add helper function to get a 32-bit floating point constant. No functionality change.
...
llvm-svn: 56418
2008-09-22 00:44:35 +00:00
f1280cf744
Fold immediates into X86 shifts with fast isel. This generates:
...
sarl $3, %ecx
instead of:
movl $3, %ecx
sarl %cl, %edx
This shrinks fast isel 176.gcc by about 2000 instructions (.3%)
llvm-svn: 56413
2008-09-21 21:44:29 +00:00
ae9d9f4d3f
Factor out code into HandleVirtRegDef, for consistency with
...
Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.
llvm-svn: 56412
2008-09-21 21:11:41 +00:00
dfc19e6c01
Instead of building a list and sorting it just to find a maximum element,
...
compute the maximum element directly.
llvm-svn: 56411
2008-09-21 21:01:49 +00:00
df8f1cb995
Fetch the starting index of the block when assigning intervals. This gets live-in indices
...
correct in the presence of things like EH labels.
llvm-svn: 56410
2008-09-21 20:43:24 +00:00
43f5449c48
don't print GlobalAddressSDNode's with an offset of zero as "foo0".
...
llvm-svn: 56399
2008-09-21 18:38:31 +00:00
9a8eb0d534
add a note
...
llvm-svn: 56391
2008-09-20 19:17:53 +00:00
e1dc84be64
Implement review feedback from Devang: make use
...
of mayReadFromMemory and mayWriteToMemory.
llvm-svn: 56387
2008-09-20 16:45:58 +00:00
9af7b3daec
Teach coalescer about earlyclobber bits.
...
Check bits for preferred register.
llvm-svn: 56384
2008-09-20 02:03:04 +00:00
c042000649
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
...
llvm-svn: 56381
2008-09-20 01:28:05 +00:00
4730522235
No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
...
llvm-svn: 56378
2008-09-20 00:13:45 +00:00
9d917beba6
80 column violation.
...
llvm-svn: 56377
2008-09-20 00:13:08 +00:00
098786e9f7
Fix a FastISel GlobalVariable CSE bug.
...
llvm-svn: 56376
2008-09-19 23:42:04 +00:00
29e4c9192d
Continue after removing the current MI.
...
llvm-svn: 56372
2008-09-19 22:49:39 +00:00
9801ba451a
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
...
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
llvm-svn: 56371
2008-09-19 22:16:54 +00:00
436aae627d
Make earlyclobber stuff work when virtual regs
...
have previously been assigned conflicting physreg.
llvm-svn: 56364
2008-09-19 18:52:31 +00:00
4c0197043c
Re-materalized definition instructions may be dead. Whack them.
...
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
715b9d2403
backing out my last commit, it was not intended to go on the trunk
...
llvm-svn: 56349
2008-09-19 15:13:20 +00:00
92f17070e7
first shot at removing Use::Val
...
untested, Use::swap() is definitely not done yet
llvm-svn: 56348
2008-09-19 15:03:57 +00:00
310077034a
Remove the MarkModRef pass (use AddReadAttrs instead).
...
Unfortunately this means removing one regression test
of GlobalsModRef because I couldn't work out how to
perform it without MarkModRef.
llvm-svn: 56342
2008-09-19 08:23:44 +00:00
af25ee7ffc
Add a new pass AddReadAttrs which works out which functions
...
can get the readnone/readonly attributes, and gives them it.
The plan is to remove markmodref (which did the same thing
by querying GlobalsModRef) and delete the analogous
functionality from GlobalsModRef.
llvm-svn: 56341
2008-09-19 08:17:05 +00:00
e519bd4183
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
...
and redo as linked list walk. Logic moved into RA.
Per review feedback.
llvm-svn: 56326
2008-09-19 01:02:35 +00:00
c25be3b2de
splitLoop does not handle split condition EQ.
...
Fixes PR 2805
llvm-svn: 56321
2008-09-18 23:45:14 +00:00
6e005fdc8d
Address-mode folding for X86FastISel. It's pretty basic, but it
...
catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.
llvm-svn: 56320
2008-09-18 23:23:44 +00:00
a00fa322b1
Decrementing the iterator here could be wrong if the worklist is empty after the "erase".
...
Thanks to Ji Young Park for the patch!
llvm-svn: 56316
2008-09-18 23:04:18 +00:00
76b22c1420
Try to place hoisted instructions befoe icmp instruction.
...
llvm-svn: 56315
2008-09-18 22:50:42 +00:00
3d9416cf24
Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
...
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
e91edeb61c
Simplify this code. The FastISel class has its own TD member.
...
llvm-svn: 56311
2008-09-18 18:26:43 +00:00
f3d647e00b
Don't consider instructions with implicit physical register
...
defs to be necessarily live.
llvm-svn: 56310
2008-09-18 18:22:32 +00:00
95be7d7b85
Add a new "fast" scheduler. This is currently basically just a
...
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.
This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.
llvm-svn: 56307
2008-09-18 16:26:26 +00:00
5cc53c34c3
Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable.
...
llvm-svn: 56303
2008-09-18 07:54:21 +00:00
933b392f65
Duh. Default to ARMCC::AL (always).
...
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
5e3ac187d9
Clean up.
...
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
bc0d0eccf3
Cosmetic.
...
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
af13bf1ebd
FastISel: For calls, prefer using the callee's address as a constant
...
over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.
This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.
llvm-svn: 56292
2008-09-17 21:18:49 +00:00
f8610ebebc
Add a bit to mark operands of asm's that conflict
...
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
llvm-svn: 56290
2008-09-17 21:13:11 +00:00
f3fcd7a464
Unallocatable registers do not have live intervals.
...
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
7f9671ba37
Do not hoist instruction above branch condition. The instruction may use branch condition.
...
llvm-svn: 56286
2008-09-17 18:21:49 +00:00
dca8d3b183
Do not ignore iv uses outside the loop.
...
This one slipped through cracks very well.
llvm-svn: 56284
2008-09-17 17:53:47 +00:00
6ab52a8018
Don't worry about clobbering physical register defs that aren't used.
...
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
7848cfcd77
Fix addrmode1 instruction encodings; fix bx_ret encoding.
...
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
937569afe3
Specify instruction encoding using range list to avoid endianess issues.
...
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
173aa8602d
Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
...
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.
llvm-svn: 56270
2008-09-17 01:39:10 +00:00
c24cd015a7
Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
...
be used with fast-isel.
llvm-svn: 56268
2008-09-17 00:43:24 +00:00
95e1af217f
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
...
function with appropriate parameters. This allows us to support blocks on PPC.
llvm-svn: 56267
2008-09-17 00:30:57 +00:00
a904f466e8
When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
...
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
64d6c6fe30
Change SelectionDAG::getConstantPool to always set the alignment of the
...
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.
In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.
This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)
Patch by Paul Redmond!
llvm-svn: 56253
2008-09-16 22:05:41 +00:00
24c79f28b1
Reverting r56249. On further investigation, this functionality isn't needed.
...
Apologies for the thrashing.
llvm-svn: 56251
2008-09-16 21:48:12 +00:00
ab26f20d44
Include the alignment value when displaying ConstantPoolSDNodes.
...
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
8bc392fb1d
- Change "ExternalSymbolSDNode" to "SymbolSDNode".
...
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol
These changes pave the way to allowing SymbolSDNodes with non-external linkage.
llvm-svn: 56249
2008-09-16 21:12:30 +00:00
5cf6120a7c
Fix these comments to reflect current reality. Surprisingly,
...
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.
llvm-svn: 56248
2008-09-16 20:45:53 +00:00
dc5f5cbe59
Finally re-apply r46959. This is made feasible by the combination
...
of r56230, r56232, and r56246.
llvm-svn: 56247
2008-09-16 18:52:57 +00:00
dafa9c6e85
Improve instcombine's handling of integer min and max in two ways:
...
- Recognize expressions like "x > -1 ? x : 0" as min/max and turn them
into expressions like "x < 0 ? 0 : x", which is easily recognizable
as a min/max operation.
- Refrain from folding expression like "y/2 < 1" to "y < 2" when the
comparison is being used as part of a min or max idiom, like
"y/2 < 1 ? 1 : y/2". In that case, the division has another use, so
folding doesn't eliminate it, and obfuscates the min/max, making it
harder to recognize as a min/max operation.
These benefit ScalarEvolution, CodeGen, and anything else that wants to
recognize integer min and max.
llvm-svn: 56246
2008-09-16 18:46:06 +00:00
7c5dbd95e2
AllocateRWXMemory -> AllocateRWX.
...
llvm-svn: 56244
2008-09-16 17:28:18 +00:00
050d7835c6
Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
...
are not enabled. Instead just omit the tail call flag when calls are
created.
llvm-svn: 56235
2008-09-16 01:42:28 +00:00
c5d2892e62
Re-enables the new vector select in the bitcode reader, by modifying the
...
bitcode reader/writer as follows:
- add and use new bitcode FUNC_CODE_INST_VSELECT to handle the llvm
select opcode using either i1 or [N x i1] as the selector.
- retain old BITCODE FUNC_CODE_INST_SELECT in the bitcode reader to
handle select on i1 for backwards compatibility with existing bitcode
files.
- re-enable the vector-select.ll test program.
Also, rename the recently added bitcode opcode FUNC_CODE_INST_VCMP to
FUNC_CODE_INST_CMP2 and make the bitcode writer use it to handle
fcmp/icmp on scalars or vectors. In the bitcode writer, use
FUNC_CODE_INST_CMP for vfcmp/vicmp only. In the bitcode reader, have
FUNC_CODE_INST_CMP handle icmp/fcmp returning bool, for backwards
compatibility with existing bitcode files.
Patch by Preston Gurd!
llvm-svn: 56233
2008-09-16 01:01:33 +00:00
f9081a2cd5
Teach ScalarEvolution to consider loop preheaders in the search for
...
an if statement that guards a loop, to allow indvars to avoid smax
operations in more situations.
llvm-svn: 56232
2008-09-15 22:18:04 +00:00
82ab1e7280
Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
...
instruction. Also, their valno's should have an unknown def. This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.
llvm-svn: 56231
2008-09-15 22:00:38 +00:00
68e7735a38
Teach LSR to optimize away SMAX operations for tripcounts in common
...
cases. See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.
llvm-svn: 56230
2008-09-15 21:22:06 +00:00
233785daae
Fixed Bug 2751
...
http://llvm.org/bugs/show_bug.cgi?id=2751
Abicall was enabled even when static code model was provided
in the command line.
The correct behavior is to disable abicall when static is
specified.
llvm-svn: 56228
2008-09-15 21:06:55 +00:00
3c7b9ba547
Re-enable SelectionDAG CSE for calls. It matters in the case of
...
libcalls, as in this testcase on ARM.
llvm-svn: 56226
2008-09-15 19:46:03 +00:00
02acc35abd
Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
...
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
81313fd8d1
Fix WriteAsOperand to not emit a leading space character. Adjust
...
its callers to emit a space character before calling it when a
space is needed.
This fixes several spurious whitespace issues in
ScalarEvolution's debug dumps. See the test changes for
examples.
This also fixes odd space-after-tab indentation in the output
for switch statements, and changes calls from being printed like
this:
call void @foo( i32 %x )
to this:
call void @foo(i32 %x)
llvm-svn: 56196
2008-09-14 17:21:12 +00:00
c0d712d9ed
adjust last patch per review feedback
...
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
38453eebdc
Remove isImm(), isReg(), and friends, in favor of
...
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.
llvm-svn: 56189
2008-09-13 17:58:21 +00:00
9ddb3145ae
Fix PR2792: treat volatile loads as writing memory somewhere.
...
Treat stores as reading memory, just to play safe.
llvm-svn: 56188
2008-09-13 12:45:50 +00:00
a5804effed
Fix random abort.
...
llvm-svn: 56184
2008-09-13 01:55:59 +00:00
d3fe174c53
Define CallSDNode, an SDNode subclass for use with ISD::CALL.
...
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.
And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.
CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.
llvm-svn: 56183
2008-09-13 01:54:27 +00:00
380482ac46
Typo.
...
llvm-svn: 56182
2008-09-13 01:44:01 +00:00
ba28161103
Rely on instruction format to determine so_reg operand for now.
...
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
...
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
db6571a2c7
Accidentially flipped the condition.
...
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
25a39094f8
Add debug dumps.
...
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
...
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
d1424c4eca
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
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llvm-svn: 56172
2008-09-12 22:45:55 +00:00
33fa89c6fb
Rewrite address mode 1 code emission routines.
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llvm-svn: 56171
2008-09-12 22:01:15 +00:00
3c12fc4342
On some targets, non-move instructions can become move instructions because of coalescing. e.g.
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vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1 // after coalescing vr0 with vr1
Update the value# of the destination register with the copy instruction if that happens.
llvm-svn: 56165
2008-09-12 18:13:14 +00:00
ec270fb640
Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
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ConstantFP* instead of APInt and APFloat directly.
This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.
It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.
It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.
llvm-svn: 56162
2008-09-12 18:08:03 +00:00
1f3ab86804
Pass "earlyclobber" bit through to machine
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representation; coalescer and RA need to know
about it. No functional change.
llvm-svn: 56161
2008-09-12 17:49:03 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
06dbb126e6
Rather than marking all internal globals "Ref"
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when a readonly declaration is called, set a
flag. This is faster and uses less memory.
In theory it is less accurate, because before
only those internal globals that were read
by someone were being marked "Ref", but now
all are. But in practice, thanks to other
passes, all internal globals of the kind
considered here will be both read and stored
to: those only read will have been turned
into constants, and those only stored to will
have been deleted.
llvm-svn: 56143
2008-09-12 07:29:58 +00:00
baf6762e26
The sequence for ppcf128 compares was not IEEE
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safe in the presence of NaNs.
llvm-svn: 56136
2008-09-12 00:30:56 +00:00
eff71f2953
On 64-bit targets, change 32-bit getelementptr indices to be 64-bit
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getelementptr indices, inserting an explicit cast if necessary.
This helps expose the sign-extension operation to other optimizations.
llvm-svn: 56133
2008-09-11 23:06:38 +00:00
7d01c0654c
Fix a vectorshuffle instcombine bug introduced by r55995.
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Patch by Nicolas Capens!
llvm-svn: 56129
2008-09-11 22:47:57 +00:00
a7cd7bc353
udpate header comment: s/VP/VFP/
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llvm-svn: 56126
2008-09-11 21:41:29 +00:00
dd45bc25ac
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
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llvm-svn: 56119
2008-09-11 20:28:43 +00:00
5456a37280
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
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vr1024 = extract_subreg vr1025, 1
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vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
llvm-svn: 56118
2008-09-11 20:07:10 +00:00
453564bfba
Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel.
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llvm-svn: 56117
2008-09-11 19:44:55 +00:00
0a6d01770f
Fix comment typo.
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llvm-svn: 56116
2008-09-11 19:41:10 +00:00
d4133ac315
Intrinsics don't touch internal global variables
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(unless passed one via a parameter), even if they
are IntrWriteMem.
llvm-svn: 56115
2008-09-11 19:35:55 +00:00
9b9d547a5c
Fix a copy+paste bug that Duncan spotted. For several
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cases it was still getting lucky and detecting overflow
but it was clearly incorrect.
llvm-svn: 56113
2008-09-11 18:53:02 +00:00
4c9fbbb511
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
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llvm-svn: 56112
2008-09-11 18:40:32 +00:00
e30b36fe37
Intrinsics don't read these kinds of global
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variables.
llvm-svn: 56105
2008-09-11 15:43:12 +00:00
783ed9ead1
Fix a 80 column violation.
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llvm-svn: 56097
2008-09-11 05:58:06 +00:00
58d084c05b
The version of AtomicSDNode::AtomicSDNode used (only) for
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cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional. Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.
From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out. I
cannot test on that platform.
llvm-svn: 56091
2008-09-11 03:12:59 +00:00
41baf8b22a
If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on
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X86-64 in fast isel.
llvm-svn: 56088
2008-09-11 02:41:37 +00:00
e5ca04e70d
Succumb utterly to compatibility and implement
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__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
llvm-svn: 56087
2008-09-11 02:15:03 +00:00
b401449ceb
Propagate subreg index when promoting a load to a copy.
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llvm-svn: 56085
2008-09-11 01:02:12 +00:00
Dan Gohman