maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
50,991 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

174 Commits

Author SHA1 Message Date
Evan Cheng 30f6f8fdad Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings. 
llvm-svn: 59314
 2008-11-14 20:09:11 +00:00
Evan Cheng 2666f59322 Fix pre- and post-indexed load / store encoding bugs. 
llvm-svn: 59230
 2008-11-13 07:34:59 +00:00
Evan Cheng af644b50b4 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng 7095cd2af2 Jump table JIT support. Work in progress. 
llvm-svn: 58836
 2008-11-07 09:06:08 +00:00
Evan Cheng 98dc53e926 Encode misc arithmetic instructions. 
llvm-svn: 58828
 2008-11-07 01:41:35 +00:00
Evan Cheng 49d665218c Encode extend instructions; more clean up. 
llvm-svn: 58818
 2008-11-06 22:15:19 +00:00
Evan Cheng aa03cd3336 - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
 2008-11-06 17:48:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Evan Cheng 36ae40342f Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>. 
llvm-svn: 58793
 2008-11-06 03:35:07 +00:00
Evan Cheng b870fd8874 Fix so_imm encoding bug; add support for MOVi2pieces. 
llvm-svn: 58790
 2008-11-06 02:25:39 +00:00
Evan Cheng 2686c8fb34 Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. 
llvm-svn: 58789
 2008-11-06 01:21:28 +00:00
Evan Cheng fd2adbfa28 Encode pic load / store instructions; fix some encoding bugs. 
llvm-svn: 58780
 2008-11-05 23:22:34 +00:00
Evan Cheng 81889d010c Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions. 
llvm-svn: 58764
 2008-11-05 18:35:52 +00:00
Jim Grosbach 4d0549e3be Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there. 
llvm-svn: 58626
 2008-11-03 18:38:31 +00:00
Evan Cheng 8fce66a47c Forgot this in last commit. 
llvm-svn: 58527
 2008-10-31 19:11:09 +00:00
Jim Grosbach b7c01f5f48 Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) 
llvm-svn: 57524
 2008-10-14 20:36:24 +00:00
Chris Lattner 2753955fc0 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
 2008-10-11 22:08:30 +00:00
Jim Grosbach f311fe142c Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits. 
llvm-svn: 57262
 2008-10-07 21:08:09 +00:00
Jim Grosbach 1d54d4f375 Fix Opcode values of CMP and CMN 
llvm-svn: 57251
 2008-10-07 17:40:46 +00:00
Evan Cheng 7848cfcd77 Fix addrmode1 instruction encodings; fix bx_ret encoding. 
llvm-svn: 56277
 2008-09-17 07:53:38 +00:00
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed. 
llvm-svn: 56180
 2008-09-13 01:35:33 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats. 
llvm-svn: 56176
 2008-09-12 23:15:39 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
 2008-09-12 16:56:44 +00:00
Evan Cheng fa558788e7 Control flow instruction encodings. 
llvm-svn: 55601
 2008-09-01 08:25:56 +00:00
Evan Cheng c288cc0572 ldm / stm instruction encodings. 
llvm-svn: 55599
 2008-09-01 07:48:18 +00:00
Evan Cheng c37532b24a AXI2 and AXI3 instruction encodings. 
llvm-svn: 55598
 2008-09-01 07:34:13 +00:00
Evan Cheng 169eccc24e addrmode3 instruction encodings. 
llvm-svn: 55596
 2008-09-01 07:00:14 +00:00
Evan Cheng cccca875b1 Rest of addrmode2 instruction encodings. 
llvm-svn: 55593
 2008-09-01 01:27:33 +00:00
Evan Cheng 01fd3f129a Addr2 word / byte load encodings. 
llvm-svn: 55591
 2008-08-31 19:02:21 +00:00
Evan Cheng 9f717afd68 MVN is addrmode1. 
llvm-svn: 55530
 2008-08-29 07:36:24 +00:00
Evan Cheng 2d37f19ef2 Refactor ARM instruction format definitions into a separate file. No functionality changes. 
llvm-svn: 55518
 2008-08-28 23:39:26 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue. 
llvm-svn: 54128
 2008-07-27 21:46:04 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Bill Wendling 97925ec704 Final de-tabification. 
llvm-svn: 47663
 2008-02-27 06:33:05 +00:00
Chris Lattner 1ea55cf816 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
 2008-01-17 19:59:44 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 94de7bc3aa get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Evan Cheng 7250120177 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
llvm-svn: 45727
 2008-01-07 23:56:57 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner f4d55ec4e8 remove explicit isStore flags that are now inferrable. 
llvm-svn: 45653
 2008-01-06 05:55:01 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Bill Wendling f359fed9f9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng f948772f9e 80 col. 
llvm-svn: 41812
 2007-09-10 22:22:23 +00:00
Raul Herbster 73489273ae ARM instruction table was modified by adding information to generate multiply instruction of V5TE. 
llvm-svn: 41626
 2007-08-30 23:25:47 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00