d08fbd19f5
Move callee-saved regs spills / reloads to TFI
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llvm-svn: 120228
2010-11-27 23:05:03 +00:00
d2466687bf
Formatting.
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llvm-svn: 116635
2010-10-15 22:49:28 +00:00
0961c55161
RISC architectures get their memory operand folding for free.
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The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
llvm-svn: 108099
2010-07-11 19:19:13 +00:00
d7b33002dd
Replace copyRegToReg with copyPhysReg for ARM.
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llvm-svn: 108078
2010-07-11 06:33:54 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
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llvm-svn: 104421
2010-05-22 01:47:14 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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llvm-svn: 103193
2010-05-06 19:06:44 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
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MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
fe864425cb
Refactor code.
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llvm-svn: 86423
2009-11-08 00:15:23 +00:00
4e9f379554
80-column cleanup of file header comments
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llvm-svn: 86408
2009-11-07 22:00:39 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
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llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
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llvm-svn: 77173
2009-07-27 00:05:15 +00:00
95fc6ee51a
Remove unused member functions.
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llvm-svn: 76960
2009-07-24 07:43:59 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
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llvm-svn: 76883
2009-07-23 17:06:46 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
ade05a37f1
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
Anton Korobeynikov