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Author SHA1 Message Date
Bob Wilson 59f75bba24 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson 3968c6a252 Fix bad indentation, 80-column violations, and trailing whitespace. 
llvm-svn: 99295
 2010-03-23 17:23:59 +00:00
Johnny Chen ac5024bbeb Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288
 2010-03-23 16:43:47 +00:00
Bob Wilson 9b680e21c0 Rename some instructions to match the corresponding NEON opcode. 
llvm-svn: 99266
 2010-03-23 06:26:18 +00:00
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Bob Wilson e60e3ab624 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson c286c88db0 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson 98bf5189d7 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson debe0bdb13 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Jeffrey Yasskin 7d116ce2e3 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
llvm-svn: 99182
 2010-03-22 16:13:21 +00:00
Daniel Dunbar fed917e078 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
llvm-svn: 99097
 2010-03-20 22:36:22 +00:00
Bob Wilson 162242b63b pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!

llvm-svn: 99096
 2010-03-20 22:20:40 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson 59e5141d44 Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.

llvm-svn: 99094
 2010-03-20 21:57:36 +00:00
Bob Wilson b18adef4ad Add variants of VST2, VST3 and VST4 with address register writeback, and 
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093
 2010-03-20 21:45:18 +00:00
Bob Wilson 89ba42c4ce Add instructions for double-spaced VST3 and VST4 without address register 
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090
 2010-03-20 21:15:48 +00:00
Bob Wilson 322cbff3d3 Add VST1 instructions with address register writeback. 
llvm-svn: 99083
 2010-03-20 20:54:36 +00:00
Bob Wilson 9152d96dfb Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with 
address register writeback.

llvm-svn: 99082
 2010-03-20 20:47:18 +00:00
Bob Wilson 9b1584245a Tidy some more comments and whitespace. 
llvm-svn: 99081
 2010-03-20 20:39:53 +00:00
Bob Wilson cf324658f6 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and 
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080
 2010-03-20 20:10:51 +00:00
Bob Wilson 7ee900da22 Tidy some comments and whitespace for consistency. 
llvm-svn: 99078
 2010-03-20 19:57:03 +00:00
Bob Wilson c0795f8b87 Rename some instructions for consistency and sanity: use "_UPD" suffix for 
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066
 2010-03-20 18:35:24 +00:00
Bob Wilson d092669b48 Add instructions for double-spaced VLD3 and VLD4 without address register 
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065
 2010-03-20 18:14:26 +00:00
Bob Wilson 496766cb56 Add VLD1 instructions with address register writeback. 
llvm-svn: 99062
 2010-03-20 17:59:03 +00:00
Bob Wilson 2497d85c9e Revert the rest of 98679. 
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049
 2010-03-20 06:34:02 +00:00
Bob Wilson 614d1fdfc3 Fix a very bad typo. Since the register number was off by one, the ARM 
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043
 2010-03-20 06:05:13 +00:00
Johnny Chen f833fad813 Add NLdStFrm Format. 
llvm-svn: 99014
 2010-03-20 00:17:00 +00:00
Johnny Chen 053e3510a3 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

llvm-svn: 99013
 2010-03-19 23:50:27 +00:00
Bob Wilson e4191e719b Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Johnny Chen 0dab68f3d0 Renumber LdStExFrm from 28 to 11 and shift the existing format values to make 
room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

llvm-svn: 98967
 2010-03-19 17:39:00 +00:00
Chris Lattner 0433699ef0 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.

llvm-svn: 98937
 2010-03-19 05:33:51 +00:00
Jeffrey Yasskin 4822dfcc9a Remove a memory leak from ThumbTargetMachine. 
llvm-svn: 98936
 2010-03-19 05:25:28 +00:00
Daniel Dunbar 857955243e Fix -Asserts warnings. 
llvm-svn: 98928
 2010-03-19 03:18:23 +00:00
Bob Wilson a4d86b63c7 Update comment to refer to the right filename. 
llvm-svn: 98902
 2010-03-18 23:57:57 +00:00
Anton Korobeynikov f11aa9e7b4 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov 64578d5599 Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Anton Korobeynikov 422dd6608a Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support. 
llvm-svn: 98887
 2010-03-18 22:35:02 +00:00
Chris Lattner fb2ceede8f fix some buggy ops concatentation 
llvm-svn: 98869
 2010-03-18 21:06:54 +00:00
Bob Wilson a7f236ae3a Refactor NEON ld/st instructions to hardcode class arguments that are constants. 
No functional changes.

llvm-svn: 98860
 2010-03-18 20:18:39 +00:00
Johnny Chen 274a0d3794 Revert 98745 with respect to the addition of NEONFrm subformats for disassembly. 
There is a better way coming up.

llvm-svn: 98777
 2010-03-17 23:26:50 +00:00
Johnny Chen 0910b5afac Fixed a bug in the IT mask printing where T means the cond bit in the mask 
matches that of Firstcond[0] and E means otherwise.  The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing.  The disassembler also depends
on this arrangement.  This is similar to what's described in A2.5.2 ITSTATE.

Ran:

utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2

successfully.

llvm-svn: 98775
 2010-03-17 23:14:23 +00:00
Johnny Chen 8609782366 Refines 98745 so that it only contains the patch related to the output of the 
addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.

This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp.  It is used by disassembler as of now.

llvm-svn: 98774
 2010-03-17 23:01:59 +00:00
Bob Wilson a6fe21a79a Clean up whitespace. 
llvm-svn: 98769
 2010-03-17 21:16:45 +00:00
Bob Wilson 69ba1bcd05 Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f 
in svn r74988 but the format field was never widened.

llvm-svn: 98768
 2010-03-17 21:13:43 +00:00
Johnny Chen 6e81f67b09 98745 contains something unrelated to the patch. 
Remove it from ARMAddressingModes.h.

llvm-svn: 98751
 2010-03-17 18:32:39 +00:00
Johnny Chen 8f3004cff2 Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm 
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98745
 2010-03-17 17:52:21 +00:00
Bob Wilson c7ba918b84 Revert 98683. It is breaking something in the disassembler. 
llvm-svn: 98692
 2010-03-16 23:01:13 +00:00
Bob Wilson c953bca10b Remove redundant writeback flag from ARM address mode 6. Also remove the 
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683
 2010-03-16 21:44:40 +00:00