Commit Graph

671 Commits

Author SHA1 Message Date
Richard Smith b87c465391 Store a TypeArgument on an attribute as a TypeSourceInfo*, rather than as a
QualType with a SourceLocation stashed alongside.

llvm-svn: 193803
2013-10-31 21:23:20 +00:00
Chad Rosier bdca387884 [AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193791
2013-10-31 19:29:05 +00:00
Chad Rosier 4d55e6e0a4 [AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193692
2013-10-30 15:20:07 +00:00
Richard Smith 66e7168f8d PR17666: Instead of allowing an initial identifier argument in any attribute
which we don't think can't have one, only allow it in the tiny number of
attributes which opts into this weird parse rule.

I've manually checked that the handlers for all these attributes can in fact
cope with an identifier as the argument. This is still somewhat terrible; we
should move more fully towards picking the parsing rules based on the
attribute, and make the Parse -> Sema interface more type-safe.

llvm-svn: 193295
2013-10-24 01:07:54 +00:00
Chad Rosier 3c03dee1d1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192971
2013-10-18 14:03:36 +00:00
Kevin Qin f22bf50443 Implemented aarch64 SIMD copy related ACLE intrinsic :
vget_lane, vset_lane, vcopy_lane, vcreate, vdup_n, vdup_lane, vmov_n.

llvm-svn: 192411
2013-10-11 02:34:30 +00:00
Chad Rosier 0babda4b9c [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192232
2013-10-08 20:43:46 +00:00
Jiangning Liu b96ebac02b Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192029
2013-10-05 08:22:55 +00:00
DeLesley Hutchins 210791a021 Consumed Analysis: Change callable_when so that it can take a list of states
that a function can be called in.  This reduced the total number of annotations
needed and makes writing more complicated behaviour less burdensome.
Patch by chriswails@gmail.com.

llvm-svn: 191983
2013-10-04 21:28:06 +00:00
Jiangning Liu 4617e9dc85 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191945
2013-10-04 09:21:17 +00:00
Aaron Ballman 682ee42550 Tablegen now generates a StringSwitch for attributes containing enumeration arguments to map strings to the proper enumeration value. This makes error checking more consistent and reduces the amount of hand-written code required.
llvm-svn: 190545
2013-09-11 19:47:58 +00:00
Aaron Ballman c12aaff2cb The cleanup attribute no longer uses an unresolved, simple identifier as its argument. Instead, it takes an expression that is fully resolved.
llvm-svn: 190476
2013-09-11 01:37:41 +00:00
Aaron Ballman 8ee40b7264 Attribute tablegen now understands that attribute arguments can be optional. This allows for automated checking of the number of arguments expected vs number of arguments given for attributes. Greatly reduces the amount of manual checking required.
llvm-svn: 190368
2013-09-09 23:33:17 +00:00
Benjamin Kramer 60509af49a Fix constructor-related typos.
Noticed by Roman Divacky.

llvm-svn: 190311
2013-09-09 14:48:42 +00:00
Jiangning Liu 1bda93a252 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190289
2013-09-09 02:21:08 +00:00
Jordan Rose 7bd9186cdd [analyzer] SATestBuild: strip trailing newlines from command file.
When running a make-based command, SATestBuild tries to append a -jN flag
with an appropriate N to run the build in parallel. However, it failed
to take into account that each line read includes a trailing newline
(unless it is the last line of a file without a trailing newline), which
resulted in the "-jN" appearing on a line on its own.

llvm-svn: 190164
2013-09-06 16:12:41 +00:00
Hao Liu b1852eed38 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189926
2013-09-04 09:29:13 +00:00
Aaron Ballman f58070baed Switched FormatAttr to using an IdentifierArgument instead of a StringArgument since that is a more accurate modeling.
llvm-svn: 189851
2013-09-03 21:02:22 +00:00
Kevin Qin c076d0682b mangle aarch64 Neon ACLE scalar instrinsic name with BHSD suffix.
llvm-svn: 189574
2013-08-29 07:55:15 +00:00
Craig Topper da7cf8ab2b Move individual group name strings from the OptionTable into one big char array. Then only store offsets into it in the OptionTable. Saves about 4K from the clang binary and removes 400 relocation entries from DiagnosticIDs.o.
llvm-svn: 189568
2013-08-29 05:18:04 +00:00
Craig Topper a3891a7568 Reorder and shrink size of NameLen field in diagnostic group table. Shaves ~4K from clang binary.
llvm-svn: 189445
2013-08-28 06:01:10 +00:00
Craig Topper d80c17e060 Merge diagnostic group tables to reduce data size and relocation entries.
The individual group and subgroups tables are now two large tables. The option table stores an index into these two tables instead of pointers. This reduces the size of the options tabe since it doesn't need to store pointers. It also reduces the number of relocations needed.

My build shows this reducing DiagnosticsIDs.o and the clang binary by ~20.5K. It also removes ~400 relocation entries from DiagnosticIDs.o.

llvm-svn: 189438
2013-08-28 04:02:50 +00:00
Rafael Espindola d3f8b1f2b1 clang-format utils/TableGen/TableGen.cpp.
I have a patch that edits the file. Running clang-format first makes the patch
a lot easier to review.

llvm-svn: 188562
2013-08-16 16:46:27 +00:00
Hao Liu 4efa1402fe Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
llvm-svn: 188452
2013-08-15 08:26:30 +00:00
Tim Northover 2fe823a6c3 AArch64: initial NEON support
Patch by Ana Pazos

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187568
2013-08-01 09:23:19 +00:00
Aaron Ballman 080cad730a Fixing an unused variable warning.
llvm-svn: 187474
2013-07-31 02:20:22 +00:00
Aaron Ballman 0979e9e130 Added the notion of Type and TargetSpecific attributes to the clang tablegen. In turn, this fixes a mistake with Ptr32, Ptr64, UPtr and SPtr attribtues generating AST nodes that are never actually used.
llvm-svn: 187401
2013-07-30 01:44:15 +00:00
Craig Topper a9bcac5825 Const-correct some iterators. No functional change.
llvm-svn: 186797
2013-07-21 22:20:10 +00:00
Craig Topper f3932e3355 Remove trailing whitespace
llvm-svn: 186722
2013-07-19 21:43:59 +00:00
Michael Gottesman 1169a52c83 [NeonIntrinsicTestEmitter] vld1/vst1 do not require the :64 hint.
llvm-svn: 184786
2013-06-24 21:25:39 +00:00
Michael Gottesman c6b5e56c19 [NeonIntrinsicTestEmitter] Fix incorrect FileCheck pattern where we were expecting a ',' prefix to alignment hints.
llvm-svn: 184785
2013-06-24 21:25:37 +00:00
Michael Gottesman d95c49a91c [NeonIntrinsicTestEmitter] Add requirement to arm neon intrinsic tests for the feature long_tests.
This will prevent the tests from running on normal make check. You will need to
actually pass in --param run_long_tests=true to LIT in order to run these.

llvm-svn: 184784
2013-06-24 21:25:34 +00:00
Reid Kleckner 5d0708893d Remove option emitter from clang-tblgen
The CMake build was still using it because I forgot to s/CLANG/LLVM/ in
the tablegen() call.  The Makefile build is already using llvm-tblgen.

llvm-svn: 184192
2013-06-18 15:25:00 +00:00
Jordan Rose c7b992edcf [analyzer] SATestBuild: Don't require reference results to have logs.
The Logs directory isn't used for testing, so it's filtered out ahead of
time. However, there's then no reason to include it in version control at
all. Don't error if it's not present.

llvm-svn: 183689
2013-06-10 19:34:30 +00:00
Anna Zaks 7b4f8a4181 [analyzer] Always use ccc-analyzer when running scan-build on buildbot
llvm-svn: 182982
2013-05-31 02:31:09 +00:00
Richard Smith 82f3fc06d3 Increase the portability of this script a bit: use /usr/bin/env to find bash,
rather than assuming it lives in the path. Patch by Eitan Adler!

llvm-svn: 182696
2013-05-24 23:54:21 +00:00
Jim Grosbach d10f1c04aa ARM: Improve codegen for vget_low_* and vget_high_ intrinsics.
These intrinsics use the __builtin_shuffle() function to extract the
low and high half, respectively, of a 128-bit NEON vector. Currently,
they're defined to use bitcasts to simplify the emitter, so we get code
like:
uint16x4_t vget_low_u32(uint16x8_t __a) {
  return (uint32x2_t) __builtin_shufflevector((int64x2_t) __a,
                                              (int64x2_t) __a,
                                              0);
}

While this works, it results in those bitcasts going all the way through
to the IR, resulting in code like:
  %1 = bitcast <8 x i16> %in to <2 x i64>
  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32>
  %zeroinitializer
  %3 = bitcast <1 x i64> %2 to <4 x i16>

We can instead easily perform the operation directly on the input vector
like:

uint16x4_t vget_low_u16(uint16x8_t __a) {
  return __builtin_shufflevector(__a, __a, 0, 1, 2, 3);
}

Not only is that much easier to read on its own, it also results in
cleaner IR like:

  %1 = shufflevector <8 x i16> %in, <8 x i16> undef,
                     <4 x i32> <i32 0, i32 1, i32 2, i32 3>

This is both easier to read and easier for the back end to reason
about effectively since the operation is obfuscating the source with
bitcasts.

rdar://13894163

llvm-svn: 181865
2013-05-15 02:40:04 +00:00
Reid Kleckner 4290361b99 Fix copy-pasto in naming of LAST_MS_INHERITANCE[_ATTR]
Richard Smith pointed this out over a month ago.

llvm-svn: 181830
2013-05-14 20:55:49 +00:00
Dmitri Gribenko 010316ce34 ArrayRef<T>() -> None cleanup
llvm-svn: 181140
2013-05-05 01:03:47 +00:00
Douglas Gregor 231ca1c929 Restore Richard's belief in me.
llvm-svn: 181042
2013-05-03 18:51:59 +00:00
Douglas Gregor d2472d4cdb Use attribute argument information to determine when to parse attribute arguments as expressions.
This change partly addresses a heinous problem we have with the
parsing of attribute arguments that are a lone identifier. Previously,
we would end up parsing the 'align' attribute of this as an expression
"(Align)":

 template<unsigned Size, unsigned Align>
 class my_aligned_storage
 {
   __attribute__((align((Align)))) char storage[Size];
 };

while this would parse as a "parameter name" 'Align':

 template<unsigned Size, unsigned Align>
 class my_aligned_storage
 {
   __attribute__((align(Align))) char storage[Size];
 };

The code that handles the alignment attribute would completely ignore
the parameter name, so the while the first of these would do what's
expected, the second would silently be equivalent to

 template<unsigned Size, unsigned Align>
 class my_aligned_storage
 {
   __attribute__((align)) char storage[Size];
 };

i.e., use the maximal alignment rather than the specified alignment.

Address this by sniffing the "Args" provided in the TableGen
description of attributes. If the first argument is "obviously"
something that should be treated as an expression (rather than an
identifier to be matched later), parse it as an expression.

Fixes <rdar://problem/13700933>.

llvm-svn: 180973
2013-05-02 23:25:32 +00:00
Douglas Gregor 33ebfe36e5 Revert r180970; it's causing breakage.
llvm-svn: 180972
2013-05-02 23:15:45 +00:00
Douglas Gregor 44dff3f2dc Use attribute argument information to determine when to parse attribute arguments as expressions.
This change partly addresses a heinous problem we have with the
parsing of attribute arguments that are a lone identifier. Previously,
we would end up parsing the 'align' attribute of this as an expression
"(Align)":

  template<unsigned Size, unsigned Align>
  class my_aligned_storage
  {
    __attribute__((align((Align)))) char storage[Size];
  };

while this would parse as a "parameter name" 'Align':

  template<unsigned Size, unsigned Align>
  class my_aligned_storage
  {
    __attribute__((align(Align))) char storage[Size];
  };

The code that handles the alignment attribute would completely ignore
the parameter name, so the while the first of these would do what's
expected, the second would silently be equivalent to

  template<unsigned Size, unsigned Align>
  class my_aligned_storage
  {
    __attribute__((align)) char storage[Size];
  };

i.e., use the maximal alignment rather than the specified alignment.

Address this by sniffing the "Args" provided in the TableGen
description of attributes. If the first argument is "obviously"
something that should be treated as an expression (rather than an
identifier to be matched later), parse it as an expression.

Fixes <rdar://problem/13700933>.

llvm-svn: 180970
2013-05-02 23:08:12 +00:00
Michael Gottesman 3508389233 [neonemitter tests] Change triple of emitted tests to thumbv7s to match the target cpu being swift. Also specify the target-abi to apcs-gnu.
llvm-svn: 180233
2013-04-25 00:10:14 +00:00
Michael Gottesman 6cd3e560fd [6/6] ARM Neon Intrinsic Tablegen Test Generator.
Added GenerateChecksForIntrinsic method to generate FileCheck patterns
for generated arm neon tests.

Reviewed by Bob Wilson.

llvm-svn: 179644
2013-04-16 23:00:26 +00:00
Michael Gottesman 1d712fe52d [5/6] ARM Neon Intrinsic Tablegen Test Generator.
Changed the test generation target cpu type from cortex-a9 to swift.

Reviewed by Bob Wilson.

llvm-svn: 179642
2013-04-16 22:55:01 +00:00
Michael Gottesman d44c8f7d20 [4/6] ARM Neon Intrinsic Tablegen Test Generator.
Added code to NeonEmitter::runTests so that GenTest gets all of the needed
arguments to invoke the neon test generation methods.

Reviewed by Bob Wilson.

llvm-svn: 179640
2013-04-16 22:48:52 +00:00
Michael Gottesman 095c58f1c4 [3/6] ARM Neon Intrinsic Tablegen Test Generator.
Refactored out the method InstructionTypeCode from MangleName for use in
further patches which perform neon tablegen test generation.

Reviewed by Bob Wilson.

llvm-svn: 179636
2013-04-16 22:07:30 +00:00
Michael Gottesman fc89cc2a91 [2/6] ARM Neon Intrinsic Tablegen Test Generator.
This patch causes OpInst records to be silently identified with their Non-Op
inst counterparts so that the same test generation infrastructure can be used to
generate tests.

Reviewed by Bob Wilson.

llvm-svn: 179628
2013-04-16 21:18:42 +00:00
Bob Wilson 2b59395d0e Define Neon intrinsics as "static inline" to avoid warning. rdar://13108414
We had been defining Neon intrinsics as "static" with always_inline attributes.
If you use them from an extern inline function, you get a warning, e.g.:

static function 'vadd_u8' is used in an inline function with external linkage

This change simply adds the inline keyword to avoid that warning.

llvm-svn: 179406
2013-04-12 20:17:20 +00:00