Commit Graph

424328 Commits

Author SHA1 Message Date
Yaxun (Sam) Liu 559b8fc17e [AMDGPU] emit macro __GFX9__ etc
Emit predefined macros for GPU family. e.g.
for GPU gfx9xx emit __GFX9__, etc.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D125909
2022-05-19 12:06:56 -04:00
Florian Hahn 32d6ef36d6
[SimpleLoopUnswitch] Skip trivial selects during trivial unswitching.
Update the remaining places in unswitchTrivialBranch to properly skip
trivial selects.

Fixes #55526.
2022-05-19 17:01:13 +01:00
Jay Foad d14f2a6359 [AMDGPU] Allow multiple uses of the same literal in SOP2/SOPC
AMDGPUAsmParser::validateSOPLiteral already knew about this but
SIInstrInfo::verifyInstruction did not.

Differential Revision: https://reviews.llvm.org/D125976
2022-05-19 16:42:20 +01:00
David Spickett a136a00eae [lldb] Add non-address bit improvements to release notes
This summarises the changes made by d9398a91e2.
Which forms the bulk of the fixes needed for non-address bit handling.

Note that in the previous releases we noted memory tagging support,
which is a subset of non-address bits. The recent changes enable
debugging of programs using memory tagging, pointer authentication
and top byte ignore (all at once) on AArch64.
2022-05-19 15:39:32 +00:00
Yaxun (Sam) Liu cefe472c51 [clang] Fix __has_builtin
Fix __has_builtin to return 1 only if the requested target features
of a builtin are enabled by refactoring the code for checking
required target features of a builtin and use it in evaluation
of __has_builtin.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D125829
2022-05-19 11:34:42 -04:00
Tiehu Zhang 3ed9f603fd [LoopVectorize] Don't interleave when the number of runtime checks exceeds the threshold
The runtime check threshold should also restrict interleave count.
Otherwise, too many runtime checks will be generated for some cases.

Reviewed By: fhahn, dmgreen

Differential Revision: https://reviews.llvm.org/D122126
2022-05-19 23:29:00 +08:00
Tiehu Zhang 94a2bd5a27 [LoopVectorize] Precommit a test for D122126 2022-05-19 23:28:39 +08:00
Florian Hahn df56fb44f5
[VPlan] Update VPWidenMemoryInstruction to not inherit from VPValue.
VPWidenMemoryInstruction also models stores which may not produce a value.
This can trip over analyses. Improve the modeling by only adding
VPValues for VPWidenMemoryInstructionRecipes modeling loads.
2022-05-19 16:24:58 +01:00
Louis Dionne 4431e8c84e [libc++] Override the value of LIBCXX_CXX_ABI in the cache
This will allow us to remove this entirely once the commit has propagated
through all CI and hence changed the value in the cache.
2022-05-19 11:21:09 -04:00
Sotiris Apostolakis a094ad03f3 [NFC] Fix typos in X86CmovConversion 2022-05-19 15:13:11 +00:00
Louis Dionne a5f36259a2 [libunwind] Remove unused _LIBUNWIND_HAS_NO_THREADS macro in tests
The _LIBUNWIND_HAS_NO_THREADS macro is only picked up by libunwind
inside its sources, so it is only required when it builds. It doesn't
need to be defined when running the tests.
2022-05-19 10:58:13 -04:00
Joe Nash ac2ff258d6 [AMDGPU] gfx11 scalar memory instructions
Contributors:
Mirko Brkusanin <Mirko.Brkusanin@amd.com>

Patch 9/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125820

Reviewed By: kosarev, #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125822
2022-05-19 10:27:47 -04:00
Louis Dionne fa7ce8e685 [runtimes] Fix the build of merged ABI/unwinder libraries
Also, add a CI job that tests this configuration. The exact configuration
is that we build a shared libc++ and merge objects for the ABI library
and the unwinder library into it.

Differential Revision: https://reviews.llvm.org/D125903
2022-05-19 10:49:36 -04:00
Andrzej Warzynski e601b2a154 [flang][driver] Add support for generating executables on MacOSX/Darwin
This patch basically extends https://reviews.llvm.org/D122008 with
support for MacOSX/Darwin.

To facilitate this, I've added `MacOSX` to the list of supported OSes in
Target.cpp. Flang already supports `Darwin` and it doesn't really do
anything OS-specific there (it could probably safely skip checking the
OS for now).

Note that generating executables remains hidden behind the
`-flang-experimental-exec` flag. Also, we don't need to add `-lm` on
MacOSX as `libm` is effectively included in `libSystem` (which is linked
in unconditionally).

Differential Revision: https://reviews.llvm.org/D125628
2022-05-19 15:47:59 +01:00
Mats Petersson 3b390a1682 [flang][OpenMP] Support for Collapse
Convert Fortran parse-tree into MLIR for collapse-clause.

Includes simple Fortran to LLVM-IR test, with auto-generated
check-lines (some of which have been edited by hand).

Reviewed By: kiranchandramohan, shraiysh, peixin

Differential Revision: https://reviews.llvm.org/D125302
2022-05-19 15:39:48 +01:00
Joe Nash 729467acef [AMDGPU] gfx11 LDSDIR instructions MC support
Contributors:
Carl Ritson <carl.ritson@amd.com>

Patch 8/N for upstreaming of AMDGPU gfx11 architecture.

Depends on D125498

Reviewed By: critson, rampitec, #amdgpu

Differential Revision: https://reviews.llvm.org/D125820
2022-05-19 10:08:47 -04:00
Nikolas Klauser f94a447679 [libc++] Granularize algorithm benchmarks
Reviewed By: ldionne, #libc

Spies: libcxx-commits, mgorny, mgrang

Differential Revision: https://reviews.llvm.org/D124740
2022-05-19 16:13:52 +02:00
Daniil Dudkin b2f9bde2e0 [flang][NFC] Allow whitespaces before `ERROR`
This change allows to write whitespaces before the `ERROR` keyword
in semantic tests for consistency with other testing infrastructure.

Also, one test is changed in order to test if the change works
correctly.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D125884
2022-05-19 17:13:02 +03:00
Nikolas Klauser 06cf0ce90a [libc++] Enable move semantics for vector in C++03
We require move semantics in C++03 anyways, so let's enable them for the containers.

Reviewed By: ldionne, #libc

Spies: libcxx-commits

Differential Revision: https://reviews.llvm.org/D123802
2022-05-19 16:11:56 +02:00
Bradley Smith 5f4541fefb [AArch64][SVE] Convert SRSHL to LSL when the fed from an ABS intrinsic
Differential Revision: https://reviews.llvm.org/D125233
2022-05-19 14:07:59 +00:00
Utkarsh Saxena 5bbf6ad5b6 Add an option to fill container for ref
This allows index implementations to fill container details when required specially when computing containerID is expensive.

Differential Revision: https://reviews.llvm.org/D125925
2022-05-19 16:05:38 +02:00
William Schmidt d633dbd195 [SLP][NFC] Pre-commit test showing vectorization preventing FMA
When we generate a horizontal reduction of floating adds fed by a vectorized
tree rooted at floating multiplies, we should account for the cost of no
longer being able to generate scalar FMAs.  Similarly, if we vectorize a
list of floating multiplies that each feeds a single floating add, we should
again account for this cost.

The first test was reduced from a case where the vectorizable tree looked
barely profitable (cost -1) with a horizontal reduction, but produced
substantially worse code than allowing the FMAs to be generated.  The second
test was derived from the first: we again generate a horizontal reduction
here, but even if the horizontal reduction is forced to be unprofitable, we
try to vectorize the multiplies.  I have follow-up patches to address these
issues.

Differential Revision: https://reviews.llvm.org/D124867
2022-05-19 06:57:24 -07:00
David Spickett 068f14f1e4 [lldb] Add --show-tags option to "memory find"
This is off by default. If you get a result and that
memory has memory tags, when --show-tags is given you'll
see the tags inline with the memory content.

```
(lldb) memory read mte_buf mte_buf+64 --show-tags
<...>
0xfffff7ff8020: 00 00 00 00 00 00 00 00 0d f0 fe ca 00 00 00 00 ................ (tag: 0x2)
<...>
(lldb) memory find -e 0xcafef00d mte_buf mte_buf+64 --show-tags
data found at location: 0xfffff7ff8028
0xfffff7ff8028: 0d f0 fe ca 00 00 00 00 00 00 00 00 00 00 00 00 ................ (tags: 0x2 0x3)
0xfffff7ff8038: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ (tags: 0x3 0x4)
```

The logic for handling alignments is the same as for memory read
so in the above example because the line starts misaligned to the
granule it covers 2 granules.

Depends on D125089

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D125090
2022-05-19 14:40:01 +01:00
Sheng df25f0d520 [M68k] Fix a bug in disassembler
Sorry for my reckless patch. In some cases `RoundUp` is less than
the bit width of APInt. We need to check this before we do zext.
2022-05-19 21:19:44 +08:00
David Green 602f81ec33 [AArch64] Fix zero element TBL indices
A TBL instruction will fill out-of-range values with 0's, something used
in D121139 to turn tbl2 with a zero input into tbl1s. This works OK for
v16i8, but for v8i8 the input is still treated as a v16i8, so
out-of-range values (like a lane index of 8) would end up loading values
from the top half of the input register. Clean this up by detecting the
out of range values and making sure they really use out of range values.
There is a fix for swapped indices of 64bit input vectors too, which
could be incorrectly adjusted if the zerovector was the first operand.

Fixes #55545

Differential Revision: https://reviews.llvm.org/D125865
2022-05-19 13:54:35 +01:00
Sheng 017c98276b [NFC][M68k] Replace `APInt::zextOrSelf` with `APInt::zext`
This is a follow up to D125558
2022-05-19 20:43:56 +08:00
David Spickett 13e1cf8065 Reland "[lldb] Add --all option to "memory region""
This reverts commit 3e928c4b9d.

This fixes an issue seen on Windows where we did not properly
get the section names of regions if they overlapped. Windows
has regions like:
[0x00007fff928db000-0x00007fff949a0000) ---
[0x00007fff949a0000-0x00007fff949a1000) r-- PECOFF header
[0x00007fff949a0000-0x00007fff94a3d000) r-x .hexpthk
[0x00007fff949a0000-0x00007fff94a85000) r-- .rdata
[0x00007fff949a0000-0x00007fff94a88000) rw- .data
[0x00007fff949a0000-0x00007fff94a94000) r-- .pdata
[0x00007fff94a94000-0x00007fff95250000) ---

I assumed that you could just resolve the address and get the section
name using the start of the region but here you'd always get
"PECOFF header" because they all have the same start point.

The usual command repeating loop used the end address of the previous
region when requesting the next, or getting the section name.
So I've matched this in the --all scenario.

In the example above, somehow asking for the region at
0x00007fff949a1000 would get you a region that starts at
0x00007fff949a0000 but has a different end point. Using the load
address you get (what I assume is) the correct section name.
2022-05-19 13:16:36 +01:00
David Green dd644ddf85 [AArch64] Extend zero vector TBL codegen tests. NFC 2022-05-19 13:01:55 +01:00
Andrzej Warzynski f820625503 [flang][driver] Make driver accept `-module-dir<value>`
`-module-dir` is Flang's equivalent for `-J` from GFortran (in fact,
`-J` is an alias for `-module-dir` in Flang). Currently, only
`-module-dir <value>` is accepted. However, `-J` (and other options for
specifying various paths) accepts `-J<value>` as well as `-J <value>`.
This patch makes sure that `-module-dir` behaves consistently with other
such flags.

Differential Revision: https://reviews.llvm.org/D125957
2022-05-19 11:13:35 +00:00
Dmitry Preobrazhensky 44673278e0 [AMDGPU][MC][GFX940] Add SMFMAC aliases
Differential Revision: https://reviews.llvm.org/D125888
2022-05-19 13:40:48 +03:00
Jay Foad 4e432f1b7c [APInt] Deprecate truncOrSelf, zextOrSelf and sextOrSelf
Differential Revision: https://reviews.llvm.org/D125558
2022-05-19 11:23:13 +01:00
Jay Foad 6bec3e9303 [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf
Most clients only used these methods because they wanted to be able to
extend or truncate to the same bit width (which is a no-op). Now that
the standard zext, sext and trunc allow this, there is no reason to use
the OrSelf versions.

The OrSelf versions additionally have the strange behaviour of allowing
extending to a *smaller* width, or truncating to a *larger* width, which
are also treated as no-ops. A small amount of client code relied on this
(ConstantRange::castOp and MicrosoftCXXNameMangler::mangleNumber) and
needed rewriting.

Differential Revision: https://reviews.llvm.org/D125557
2022-05-19 11:23:13 +01:00
Ivan Kosarev 70ace420c1 [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir.
Discovered with D125604.

Reviewed By: #amdgpu, arsenm

Differential Revision: https://reviews.llvm.org/D125900
2022-05-19 11:20:08 +01:00
Kirill Bobyrev 4f5a4215bf
[clangd] Update the test after diagnostic message change 2022-05-19 12:03:31 +02:00
Kirill Bobyrev 43c0f90dd6
[clangd] NFC: Clarify the Include Cleaner warning 2022-05-19 11:59:00 +02:00
Lian Wang 530bab1f93 [RISCV][SelectionDAG] Support VECREDUCE_ADD mask operation
Re-landed D125206

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125206
2022-05-19 09:53:33 +00:00
Konrad Kleine c0f5beef2f [release] Add cmake as an extra tarball and not bundle it
Revert "Add cmake/ to release tarballs via concatenation"

This reverts commit 3a33664e88.

Revert "Add cmake to source release tarballs"

This reverts commit 32a0482a65.

Reviewed By: tstellar, aaronpuchert

Differential Revision: https://reviews.llvm.org/D125798
2022-05-19 11:12:54 +02:00
Alex Bradbury 2f8c067bef [WebAssembly][NFC] Fix errant tabs in test case in last commit
[4e8b2ac](https://reviews.llvm.org/rG4e8b2ac7c019) contained unintended
tabs. This commit fixes that.
2022-05-19 10:10:20 +01:00
Guillaume Chatelet 94d6dd9057 [libc] Apply no-builtin everywhere, remove unnecessary flags
Some functions like `stpncpy` are implemented in terms of `memset` but are not
currently using `-fno-builtin-memset`. This is somewhat hidden by the fact that
we use `-ffreestanding` globally and that `-ffreestanding` implies
`-fno-builtin` for Clang.

This patch also removes `-mllvm -combiner-global-alias-analysis` that is Clang
specific and that does not bring substantial gains on modern processors.

Also we keep `-mllvm --tail-merge-threshold=0` for aarch64 in CMakeLists.txt
but we omit it in the Bazel config. This is because Bazel consumes the source
files directly and so it can use PGO to take optimal decisions locally.

Differential Revision: https://reviews.llvm.org/D125894
2022-05-19 09:08:42 +00:00
Alex Bradbury 4e8b2ac7c0 [WebAssembly] Fix bug where -no-type-check failed to completely disable the typechecker
Related to <https://github.com/llvm/llvm-project/issues/55566>.
Committing directly (per LLVM's code review policy) as this is a trivial
fix.
2022-05-19 10:06:02 +01:00
LLVM GN Syncbot 3948962b45 [gn build] Port 4df795bff7 2022-05-19 08:04:45 +00:00
Sam McCall 481691572d [Serialization] Add missing includes for CHAR_BIT 2022-05-19 10:04:25 +02:00
Lian Wang f035068bb3 [LegalizeVectorTypes][VP] Add widen and split support for VP_SETCC
Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D125446
2022-05-19 07:42:39 +00:00
Daniel Kiss d3a6f57391 [libunwind] Remove -Wsign-conversion warning
Reland after dependent change reland.
2022-05-19 09:41:42 +02:00
Sam McCall 4df795bff7 [Serialization] Delta-encode consecutive SourceLocations in TypeLoc
Much of the size of PCH/PCM files comes from stored SourceLocations.
These are encoded using (almost) their raw value, VBR-encoded. Absolute
SourceLocations can be relatively large numbers, so this commonly takes
20-30 bits per location.

We can reduce this by exploiting redundancy: many "nearby" SourceLocations are
stored differing only slightly and can be delta-encoded.
Randam-access loading of AST nodes constrains how long these sequences
can be, but we can do it at least within a node that always gets
deserialized as an atomic unit.

TypeLoc is implemented in this patch as it's a relatively small change
that shows most of the API.
This saves ~3.5% of PCH size, I have local changes applying this technique
further that save another 3%, I think it's possible to get to 10% total.

Differential Revision: https://reviews.llvm.org/D125403
2022-05-19 09:40:44 +02:00
Lian Wang bbc6834e26 [LegalizeTypes][VP] Add integer promotions support for VP_TRUNCATE
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125739
2022-05-19 07:36:10 +00:00
Lian Wang 993070d11f [LegalizeTypes][VP][NFC] Use an if and two returns instead of ?: operator
Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125858
2022-05-19 07:18:24 +00:00
Sam McCall 4f35ca59d0 [clangd] Suppress warning: control reaches end of function 2022-05-19 08:26:13 +02:00
Sam McCall cd387e43bf [pseudo] Squash some warnings. NFC
Explicitly sizing Kind enum suggests that too-large values are allowed,
and that putting it in a bitfield is dangerous.

GCC doesn't like condition ? integer : enum.
2022-05-19 08:20:12 +02:00
LLVM GN Syncbot dfd3a385d6 [gn build] Port 03ea140b3a 2022-05-19 06:13:53 +00:00