babdcc8c2c
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
...
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 12:24:57 +00:00
8002a3f6d8
[mips] Rename HIRegs and LORegs.
...
llvm-svn: 188341
2013-08-14 00:47:08 +00:00
3a2c2d42b8
[Mips][msa] Added initial MSA support.
...
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
llvm-svn: 188313
2013-08-13 20:54:07 +00:00
9770097727
[Mips] Support for unaligned load/store microMips instructions
...
This includes instructions lwl, lwr, swl and swr.
Patch by Zoran Jovnovic
llvm-svn: 188312
2013-08-13 20:19:16 +00:00
939877ee14
This patch implements ei and di instructions for mips. Test cases are added.
...
llvm-svn: 188176
2013-08-12 13:07:23 +00:00
00fcf2e169
[mips] Rename accumulator register classes and FP register operands.
...
llvm-svn: 188020
2013-08-08 21:54:26 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
...
llvm-svn: 187832
2013-08-06 23:08:38 +00:00
e2a39e7532
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'
...
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.
llvm-svn: 187824
2013-08-06 22:35:29 +00:00
34a32c0b87
[mips] Replace usages of register classes with register operands. Also, remove
...
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
llvm-svn: 187821
2013-08-06 22:20:40 +00:00
21f334372e
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,
...
remove lines that are setting DecoderNamespace for pseudo atomic instructions.
No intended functionality change.
llvm-svn: 187632
2013-08-01 23:14:16 +00:00
f8fff213d5
[mips] Define instruction itineraries IIArith and IILogic.
...
No functionality change.
llvm-svn: 187468
2013-07-31 00:55:34 +00:00
5973e8371a
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
...
turns "bal" into "bgezal".
llvm-svn: 187440
2013-07-30 20:24:24 +00:00
a3d9ab90dc
[mips] Implement llvm.trap intrinsic.
...
Patch by Sasa Stankovic.
llvm-svn: 187244
2013-07-26 20:58:55 +00:00
44ff81d4e3
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
...
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.
llvm-svn: 186855
2013-07-22 18:52:22 +00:00
29410f9c91
Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
...
llvm-svn: 186507
2013-07-17 14:05:19 +00:00
1baf2ea2d1
[mips] Add instruction itinerary classes for mult, seb and slt instructions.
...
llvm-svn: 186222
2013-07-12 22:43:20 +00:00
bcf1ca08e0
Add support for Mips break and syscall insructions. The corresponding test cases are added.
...
llvm-svn: 186151
2013-07-12 09:25:35 +00:00
524ad0e46e
Reverting commit r185999 due to buildboot failure.
...
llvm-svn: 186000
2013-07-10 12:26:26 +00:00
e84de1e101
Add support for Mips break and syscall insructions. The corresponding test cases are added.
...
llvm-svn: 185999
2013-07-10 10:18:10 +00:00
b34ad7860f
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
...
floating point loads and stores.
No changes in functionality.
llvm-svn: 185399
2013-07-02 00:00:02 +00:00
1af66c9b8a
[mips] Reverse the order of source operands of shift and rotate instructions that
...
have three register operands.
No intended functionality changes.
llvm-svn: 185376
2013-07-01 20:39:53 +00:00
da4496c860
[mips] brcond + setgt/setugt instruction selection patterns.
...
llvm-svn: 183334
2013-06-05 19:49:55 +00:00
6871031be9
[mips] Add instruction selection patterns for blez and bgez.
...
llvm-svn: 182396
2013-05-21 17:13:47 +00:00
5de4416962
[mips] Add (setne $lhs, 0) instruction selection pattern.
...
llvm-svn: 182307
2013-05-20 18:18:07 +00:00
1cb024207f
[mips] Trap on integer division by zero.
...
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.
llvm-svn: 182306
2013-05-20 18:07:43 +00:00
03f0fd37a9
Mips assembler: Add TwoOperandConstraint definitions
...
This patch removes alias definition for addiu $rs,$imm
and instead uses the TwoOperandAliasConstraint field in
the ArithLogicI instruction class.
This way all instructions that inherit ArithLogicI class
have the same macro defined.
The usage examples are added to test files.
Patch by Vladimir Medic
llvm-svn: 182048
2013-05-16 20:24:27 +00:00
59817110ff
Mips td file formatting: white space and long lines
...
llvm-svn: 182047
2013-05-16 20:08:49 +00:00
51785c4715
Mips assembler: Add branch macro definitions
...
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm
The corresponding test cases are added.
Patch by Vladimir Medic
llvm-svn: 182040
2013-05-16 19:40:19 +00:00
f5f48d8ff7
Mips assembler: Assembler macro ADDIU $rs,imm
...
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
llvm-svn: 181729
2013-05-13 20:26:46 +00:00
b4526ea132
[mips] Add instruction selection pattern for (seteq $LHS, 0).
...
llvm-svn: 181459
2013-05-08 19:38:04 +00:00
4254319ef9
[mips] Fix handling of instructions which copy to/from accumulator registers.
...
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
llvm-svn: 180827
2013-04-30 23:22:09 +00:00
f0aa6c9101
[mips] Add definitions of micromips load and store instructions.
...
Patch by Zoran Jovanovic.
llvm-svn: 180241
2013-04-25 01:21:25 +00:00
cd9b74a599
[mips] Add definitions of micromips shift instructions.
...
Patch by Zoran Jovanovic.
llvm-svn: 180238
2013-04-25 01:11:15 +00:00
be6a818fd4
[mips] First patch which adds support for micromips.
...
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.
Patch by Zoran Jovanovic.
llvm-svn: 179873
2013-04-19 19:03:11 +00:00
c68fd9f4f1
[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
...
operand type to uimm16.
Patch by Vladimir Medic.
llvm-svn: 179872
2013-04-19 18:47:40 +00:00
2f08822f9d
[mips] Reapply r179420 and r179421.
...
llvm-svn: 179434
2013-04-13 00:55:41 +00:00
8ed2892c1c
Revert r179420 and r179421.
...
llvm-svn: 179422
2013-04-12 22:40:07 +00:00
931ad87f6a
[mips] Instruction selection patterns for carry-setting and using add
...
instructions.
llvm-svn: 179421
2013-04-12 22:24:52 +00:00
b3c1847b30
[mips] Add patterns for DSP indexed load instructions.
...
llvm-svn: 178408
2013-03-30 02:14:45 +00:00
b1457304cc
[mips] Define reg+imm load/store pattern templates.
...
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
be8612f6f4
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
...
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.
Mips16's instructions are unaffected by this change.
llvm-svn: 178403
2013-03-30 01:36:35 +00:00
c8d85025a0
[mips] Define pseudo instructions for spilling and copying accumulator
...
registers.
llvm-svn: 178390
2013-03-30 00:54:52 +00:00
311246c6d5
[Mips Assembler] Add support for OR macro with imediate opperand
...
Mips assembler supports macros that allows the OR instruction
to have an immediate parameter. This patch adds an instruction
alias that converts this macro into a Mips ORI instruction.
Contributer: Vladimir Medic
llvm-svn: 178316
2013-03-28 23:45:13 +00:00
e1d85d55e6
[Mips Assembler] Add alias definitions for jal
...
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs
This patch provides alias definitions in td files and test cases to show the usage.
Contributer: Vladimir Medic
llvm-svn: 178304
2013-03-28 23:02:21 +00:00
9e65aa35a0
This patch that enables the Mips assembler to use symbols for offset for instructions
...
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
llvm-svn: 177685
2013-03-22 00:05:30 +00:00
c7828356aa
[mips] Print move instructions.
...
"move $4, $5" is printed instead of "or $4, $5, $zero".
llvm-svn: 176455
2013-03-04 22:25:01 +00:00
ece459bb66
[mips] Fix inefficient code generation.
...
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:
(select (setgt a, Constant), T, F)
The pattern above effectively turns into this:
(conditional-move (setlt a, Constant + 1), F, T)
llvm-svn: 176384
2013-03-01 21:52:08 +00:00
a35bc832a0
[mips] Remove SDNPWantParent from the list of SDNodeProperties.
...
No functionality change intended.
llvm-svn: 175325
2013-02-16 00:14:37 +00:00
69fb3d11ec
[mips] Split SelectAddr, which was used to match address patterns, into two
...
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
llvm-svn: 175300
2013-02-15 21:20:45 +00:00
b9bf8dca47
Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
...
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is
important as well as for other passes which need an accurate count of
program size. There will be other similar putbacks to this for various
instructions.
llvm-svn: 174747
2013-02-08 21:42:56 +00:00
061d1ea5da
[mips] Add definition of JALR instruction which has two register operands. Change the
...
original JALR instruction with one register operand to be a pseudo-instruction.
llvm-svn: 174657
2013-02-07 19:48:00 +00:00
556135d813
[mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".
...
llvm-svn: 174546
2013-02-06 21:50:15 +00:00
a206050ccb
Move MRI liveouts to Mips return instructions.
...
llvm-svn: 174410
2013-02-05 18:12:03 +00:00
9c1a027fe8
This patch that sets the EmitAlias flag in td files
...
and enables the instruction printer to print aliased
instructions.
Due to usage of RegisterOperands a change in common
code (utils/TableGen/AsmWriterEmitter.cpp) is required
to get the correct register value if it is a RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 174358
2013-02-05 08:32:10 +00:00
f8933f83f0
Start static relocation implementation for mips16.
...
This checkin makes hello world work.
llvm-svn: 174264
2013-02-02 04:07:35 +00:00
c0b020690b
[mips] Lower EH_RETURN.
...
Patch by Sasa Stankovic.
llvm-svn: 173862
2013-01-30 00:26:49 +00:00
7ab15fafe3
This is a resubmittal. For some reason it broke the bots yesterday
...
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and
blank spaces at end of lines.
Contributer: Jack Carter
llvm-svn: 172882
2013-01-19 02:00:40 +00:00
86c2c564ff
This is a resubmittal. For some reason it broke the bots yesterday
...
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Removal of redundant code and formatting fixes.
Contributers: Jack Carter/Vladimir Medic
llvm-svn: 172842
2013-01-18 20:15:06 +00:00
873c724b4a
This patch tackles the problem of parsing Mips
...
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
a8c5ec09c7
Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
...
llvm-svn: 171697
2013-01-07 05:45:56 +00:00
f412e7501a
[mips] Reorder template parameters. Remove class shift_rotate_imm32 and
...
shift_rotate_imm64.
llvm-svn: 171513
2013-01-04 19:25:46 +00:00
e36e2f6876
[mips] Refactor instructions which move data from or to coprocessors.
...
llvm-svn: 171510
2013-01-04 19:13:49 +00:00
6ac2fc4976
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
...
instructions.
llvm-svn: 170956
2012-12-21 23:21:32 +00:00
beea8a34c3
[mips] Refactor SYNC and multiply/divide instructions.
...
llvm-svn: 170955
2012-12-21 23:17:36 +00:00
31ddec5887
[mips] Refactor BAL instructions.
...
llvm-svn: 170954
2012-12-21 23:15:59 +00:00
d6b694f036
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
...
was not catching the error.
llvm-svn: 170953
2012-12-21 23:13:59 +00:00
a158042a56
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
...
llvm-svn: 170952
2012-12-21 23:03:50 +00:00
e1826d7464
[mips] Refactor load/store left/right and load-link and store-conditional
...
instructions.
llvm-svn: 170950
2012-12-21 23:01:24 +00:00
d9bf8424e5
[mips] Refactor load/store instructions.
...
llvm-svn: 170948
2012-12-21 22:58:55 +00:00
b59b047fbe
[mips] Remove unnecessary isPseudo parameter.
...
llvm-svn: 170947
2012-12-21 22:57:26 +00:00
e738efc95b
[mips] Refactor LUI instruction.
...
llvm-svn: 170944
2012-12-21 22:46:07 +00:00
895e1cb2aa
[mips] Refactor count leading zero or one instructions.
...
llvm-svn: 170942
2012-12-21 22:43:58 +00:00
4f4c4aa05e
[mips] Refactor sign-extension-in-register instructions.
...
llvm-svn: 170940
2012-12-21 22:41:52 +00:00
b14c6e4e5f
[mips] Refactor instructions which copy from and to HI/LO registers.
...
llvm-svn: 170939
2012-12-21 22:39:17 +00:00
9e89195dce
[mips] Refactor logical NOR instructions.
...
llvm-svn: 170937
2012-12-21 22:35:47 +00:00
ac10697207
[mips] Move instruction definitions in MipsInstrInfo.td.
...
llvm-svn: 170936
2012-12-21 22:33:43 +00:00
8965d24a2a
There is one more patch to finish large frames. Make sure we assert
...
on code that has large frames which will not yet compile correctly.
llvm-svn: 170673
2012-12-20 06:57:00 +00:00
e7f1acc7c0
[mips] Refactor SLT (set on less than) instructions. Separate encoding
...
information from the rest.
llvm-svn: 170664
2012-12-20 04:27:52 +00:00
bbd197e9c4
[mips] Refactor unconditional branch instruction. Separate encoding information
...
from the rest.
llvm-svn: 170663
2012-12-20 04:22:39 +00:00
b1527b7505
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
...
parameter.
llvm-svn: 170661
2012-12-20 04:20:09 +00:00
14f9ce0f83
[mips] Delete definition of CPRESTORE instruction.
...
llvm-svn: 170660
2012-12-20 04:15:30 +00:00
c0ea0bb99b
[mips] Refactor conditional branch instructions with one register operand.
...
Separate encoding information from the rest.
llvm-svn: 170659
2012-12-20 04:13:23 +00:00
f71ffd29d9
[mips] Refactor conditional branch instructions with two register operands.
...
Separate encoding information from the rest.
llvm-svn: 170657
2012-12-20 04:10:13 +00:00
7d75f9e3d3
[mips] Change the order of template parameters. Move the default parameters to
...
the end.
llvm-svn: 170651
2012-12-20 03:52:08 +00:00
244f9e874c
[mips] Refactor shift instructions with register operands. Separate encoding
...
information from the rest.
llvm-svn: 170650
2012-12-20 03:48:24 +00:00
7f96ad325f
[mips] Refactor shift immediate instructions. Separate encoding information
...
from the rest.
llvm-svn: 170649
2012-12-20 03:44:41 +00:00
ab1b715bf2
[mips] Refactor arithmetic and logic instructions with immediate operands.
...
Separate encoding information from the rest.
llvm-svn: 170648
2012-12-20 03:40:03 +00:00
1b37c4af01
[mips] Refactor arithmetic and logic instructions. Separate encoding
...
information from the rest.
llvm-svn: 170647
2012-12-20 03:34:05 +00:00
73495897b1
[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
...
ArithLogicI as the instruction base classes.
llvm-svn: 170642
2012-12-20 03:00:16 +00:00
02ec5516f8
[mips] Move class IsCommutable into MipsInstrInfo.td.
...
llvm-svn: 170054
2012-12-13 00:32:01 +00:00
efdce0fb09
[mips] Delete nodes and instructions for dynamic alloca that are no longer in
...
use.
llvm-svn: 169580
2012-12-07 03:10:18 +00:00
97e179f9e4
[mips] Shorten predicate name.
...
llvm-svn: 169579
2012-12-07 03:06:09 +00:00
02a346d11f
[mips] Remove unnecessary predicates.
...
llvm-svn: 169577
2012-12-07 03:01:24 +00:00
bb6e74a2f1
[mips] Generate big GOT code.
...
llvm-svn: 168460
2012-11-21 20:40:38 +00:00
3bc1beb696
[mips] Add predicate HasFPIdx for floating-point indexed load instruction
...
support and use it in place of HasMips32r2Or64.
llvm-svn: 168089
2012-11-15 21:17:13 +00:00
da1980f697
[mips] Set flag neverHasSideEffects flag on floating point conversion
...
instructions.
llvm-svn: 167348
2012-11-03 00:53:12 +00:00
7828331329
[mips] Set flag isAsCheapAsAMove flag on instruction LUi.
...
llvm-svn: 167345
2012-11-03 00:26:02 +00:00
4f5ef21869
[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
...
re-materialization of immediate loads.
llvm-svn: 167153
2012-10-31 18:37:55 +00:00
59a32e91f9
[mips] Fix TAILCALL's operand node type.
...
llvm-svn: 166341
2012-10-19 21:30:15 +00:00
d03d68a3ba
[mips] Add tail call instructions.
...
llvm-svn: 166338
2012-10-19 21:14:34 +00:00
0c5e357d87
[mips] Make the branch nodes used in jump instructions a template parameter.
...
llvm-svn: 166337
2012-10-19 21:11:03 +00:00
91318df0cc
Add node and enum for mips tail call.
...
llvm-svn: 166318
2012-10-19 20:59:39 +00:00
543fdf8544
Initial assembler implementation of Mips load address macro
...
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
llvm-svn: 165561
2012-10-09 23:29:45 +00:00
e948ec52d1
Adding support for instructions mfc0, mfc2, mtc0, mtc2
...
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
llvm-svn: 165351
2012-10-06 01:17:37 +00:00
30a5982e75
Implement methods that enable expansion of load immediate
...
macro instruction (li) in the assembler.
We have identified three possible expansions depending on
the size of immediate operand:
1) for 0 ≤ j ≤ 65535.
li d,j =>
ori d,$zero,j
2) for −32768 ≤ j < 0.
li d,j =>
addiu d,$zero,j
3) for any other value of j that is representable as a 32-bit integer.
li d,j =>
lui d,hi16(j)
ori d,d,lo16(j)
All of the above have been implemented in ths patch.
Contributer: Vladimir Medic
llvm-svn: 165199
2012-10-04 04:03:53 +00:00
5eeac4f813
MIPS DSP: add vector load/store patterns.
...
llvm-svn: 164744
2012-09-27 01:50:59 +00:00
3e7ba76157
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
...
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
llvm-svn: 163960
2012-09-15 01:52:08 +00:00
97158ca5c2
The Mips standalone assembler aliased instruction support.
...
The assembler can alias one instruction into another based
on the operands. For example the jump instruction "J" takes
and immediate operand, but if the operand is a register the
assembler will change it into a jump register "JR" instruction.
These changes are in the instruction td file.
Test cases included
Contributer: Vladimir Medic
llvm-svn: 163368
2012-09-07 01:42:38 +00:00
a954e92053
Add missing SDNPSideEffect flags.
...
llvm-svn: 162557
2012-08-24 14:43:27 +00:00
7605630c48
Add stub methods for mips assembly matcher.
...
Patch by Vladimir Medic.
llvm-svn: 162124
2012-08-17 20:16:42 +00:00
612c66314c
The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64
...
were using a class defined for 32 bit instructions and
thus the instruction was for addiu instead of daddiu.
This was corrected by adding the instruction opcode as a
field in the base class to be filled in by the defs.
llvm-svn: 161359
2012-08-06 23:29:06 +00:00
a66d676b20
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
...
or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
llvm-svn: 161071
2012-07-31 19:13:07 +00:00
3a810eda91
Change name of class MipsInst to InstSE to distinguish it from mips16's
...
instruction class. SE stands for standard encoding.
llvm-svn: 161069
2012-07-31 18:55:01 +00:00
f72efdb62f
Fix Mips long branch pass.
...
This pass no longer requires that the global pointer value be saved to the
stack or register since it uses bal instruction to compute branch distance.
llvm-svn: 160601
2012-07-21 03:30:44 +00:00
ed6c0408fa
Remove variable_ops from call instructions in most targets.
...
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
llvm-svn: 160189
2012-07-13 20:44:29 +00:00
efff7b763b
Make register Mips::RA allocatable if not in mips16 mode.
...
llvm-svn: 159971
2012-07-10 00:19:06 +00:00
ef40238a0e
This allows hello world to be compiled for Mips 64 direct object.
...
It takes advantage of r159299 which introduces relocation support for N64.
elf-dump needed to be upgraded to support N64 relocations as well.
This passes make check.
Jack
llvm-svn: 159302
2012-06-27 23:13:42 +00:00
d8ab16b86f
1. introduce MipsPat in place of Pat in order to exclude those from
...
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
llvm-svn: 158470
2012-06-14 21:03:23 +00:00
64f8df28ed
Add AT to the list of registers clobbered by branches so that it is available
...
as a scratch register when they are expanded to long branches.
llvm-svn: 158432
2012-06-14 01:17:59 +00:00
f11571d90d
Add definitions of 32/64-bit unaligned load/store instructions for Mips.
...
llvm-svn: 157865
2012-06-02 00:04:19 +00:00
b9ebf8d644
Define Mips specific unaligned load/store nodes.
...
llvm-svn: 157863
2012-06-02 00:03:12 +00:00
5cec9007bb
Fix predicate HasStandardEncoding in MipsInstrInfo.td per suggestion of
...
Benjamin Kramer.
llvm-svn: 157504
2012-05-25 22:15:15 +00:00
4d9b017ef2
Remove pseudo instructions that are no longer used.
...
llvm-svn: 157492
2012-05-25 20:37:40 +00:00
df98a7a34d
Enable Mips16 compiler to compile a null program.
...
First code from the Mips16 compiler. Includes trivial test program.
Patch by Reed Kotler.
llvm-svn: 157408
2012-05-24 18:32:33 +00:00
cdf4fd8267
This patch adds a predicate to existing mips32 and mips64 so that those
...
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
llvm-svn: 157234
2012-05-22 03:10:09 +00:00
c515bfb9e7
Define mips16 instruction formats.
...
Patch by Reed Kotler.
llvm-svn: 156408
2012-05-08 19:08:58 +00:00
fc1d00bbd6
Mark instruction classes ArithLogicR, ArithLogicI and LoadUpper as isRematerializable.
...
llvm-svn: 155031
2012-04-18 18:52:10 +00:00
71928e681b
Add disassembler to MIPS.
...
Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
55059262aa
Revert r153924. There were buildbot failures.
...
llvm-svn: 153925
2012-04-03 02:51:09 +00:00
e2498d014b
MIPS disassembler support.
...
Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
34ee3ff83d
Emit all directives except for ".cprestore" during asm printing rather than emit
...
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.
Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
determine whether an instruction is an unaligned load or store.
- Define helper function CreateMCInst which generates an instance of an MCInst
from an opcode and a list of operands.
llvm-svn: 153552
2012-03-28 00:22:50 +00:00
1518a5fa9c
Mark flag neverHasSideEffects of pattern-less instructions that do not have
...
any side effects.
llvm-svn: 153551
2012-03-28 00:21:37 +00:00
5350c24509
Changes for migrating to using register mask operands.
...
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
f54f60f3ce
remove blanks, and some code format
...
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
b2b980e628
Add comments.
...
llvm-svn: 151615
2012-02-28 03:18:43 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
...
load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
60f7a8e710
Add definitions of floating point multiply add/sub and negative multiply
...
add/sub instructions.
llvm-svn: 151415
2012-02-25 00:21:52 +00:00
b049aef2d1
Add an option to use a virtual register as the global base register instead of
...
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
llvm-svn: 151402
2012-02-24 22:34:47 +00:00
9f7ec1538f
64-bit sign extension in register instructions.
...
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
3b775b8cc3
Rename immLUiOpnd.
...
llvm-svn: 147519
2012-01-04 03:09:26 +00:00
b89a4bfe41
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
...
versions derive from them.
- JALR64 is not needed since N64 does not emit jal.
- Add template parameter to BranchLink that sets the rt field.
- Fix the set of temporary registers for O32 and N64.
llvm-svn: 147518
2012-01-04 03:02:47 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
43c1ff4db3
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
...
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
llvm-svn: 147015
2011-12-20 23:47:44 +00:00
0cee2045c9
Add patterns for matching extloads with 64-bit address. The patterns are enabled
...
only when the target ABI is N64.
llvm-svn: 147001
2011-12-20 22:33:53 +00:00
9b9bd1cc15
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
...
only when the target ABI is N64.
llvm-svn: 146992
2011-12-20 21:50:49 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
9e1d369e3c
Tidy up. Simplify logic. No functional change intended.
...
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
5d5e0d819d
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when
...
-relocation-model=static.
llvm-svn: 146432
2011-12-12 22:39:35 +00:00
5ee8464e48
Rename WrapperPIC. It is now used for both pic and static.
...
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
dee6c8275c
Implement 64-bit support for thread local storage handling.
...
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
llvm-svn: 146175
2011-12-08 20:34:32 +00:00
4350c183d4
Modify class ReadHardware and add definition of 64-bit version of instruction
...
RDHWR.
llvm-svn: 146101
2011-12-07 23:31:26 +00:00
6820eebde1
Define base class for WrapperPICPat.
...
llvm-svn: 146081
2011-12-07 21:54:54 +00:00
4a04a56a36
Fix 64-bit immediate patterns.
...
llvm-svn: 146059
2011-12-07 20:10:24 +00:00
0c24d8a406
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter
...
llvm-svn: 145912
2011-12-06 03:34:48 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
...
them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
049e9e4d22
This patch makes the following changes necessary for MIPS' direct code emission.
...
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).
llvm-svn: 145113
2011-11-23 22:19:28 +00:00
7b8547c4d0
Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
...
nodes.
llvm-svn: 144841
2011-11-16 22:39:56 +00:00
6d617ceca2
64-bit jump register instruction.
...
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
...
llvm-svn: 144368
2011-11-11 04:03:54 +00:00
2b8d1f163f
Add definition of 64-bit load upper immediate.
...
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
770f0646db
Make the type of shift amount i32 in order to reduce the number of shift
...
instruction definitions.
llvm-svn: 143989
2011-11-07 18:59:49 +00:00
2312a3aaa0
Final patch that completes old JIT support for Mips:
...
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
...
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
...
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
0317b65367
Redefine multiply and divide instructions.
...
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
...
source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
...
and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
...
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
...
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
6d8c039ab1
Add isIndirectBranch flag.
...
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
170581488f
Change name of class.
...
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
969edcdf74
Define classes for definitions of atomic instructions.
...
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
28d6677a53
Remove unnecessary newline.
...
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
9f6f6f6ecc
Rather than having printMemOperand change the way memory operands are printed
...
based on a modifier, split it into two functions.
llvm-svn: 134637
2011-07-07 20:54:20 +00:00
2e766ed2f8
Reverse order of operands of address operand mem so that the base operand comes
...
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
...
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
d8373a4680
Add comments for wrapper node patterns in MipsInstrInfo.td.
...
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
46662e0f91
Coding style fixes. Added comments.
...
llvm-svn: 132063
2011-05-25 17:32:06 +00:00
2db176c4c1
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
...
offsets that are larger than 0x10000.
llvm-svn: 132003
2011-05-24 21:22:21 +00:00
e50a3d16e9
Fix setting of isCommutable flag.
...
llvm-svn: 131233
2011-05-12 17:42:08 +00:00
5dc19f916c
Fix td file comments for Mips.
...
Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
...
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
...
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
...
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
a744ef3f90
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
...
llvm-svn: 127032
2011-03-04 20:48:08 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
db93ddb41b
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
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llvm-svn: 127005
2011-03-04 17:59:18 +00:00
ed874eff93
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
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llvm-svn: 127003
2011-03-04 17:51:39 +00:00
4dc73fa075
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
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llvm-svn: 123760
2011-01-18 19:29:17 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
d47180e45e
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
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llvm-svn: 121377
2010-12-09 17:32:30 +00:00
b9bfd0945a
Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
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llvm-svn: 121164
2010-12-07 19:04:14 +00:00
f0c6e3780d
Match a pattern generated by a dag combiner opt where:
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(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))
Thanks to Akira for pointing that.
llvm-svn: 121163
2010-12-07 19:00:20 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
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llvm-svn: 118864
2010-11-12 00:38:32 +00:00
67fc18a493
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
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llvm-svn: 118667
2010-11-10 02:13:22 +00:00
9c5c829d9a
Fix trailing whitespace and style, no functionality change
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llvm-svn: 118515
2010-11-09 17:25:34 +00:00
92d57cee61
Don't call Predicate_* in Mips.
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llvm-svn: 111468
2010-08-18 23:56:46 +00:00
72a364c107
fix emacs language spec's, patch by Edmund Grimley-Evans!
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llvm-svn: 111241
2010-08-17 16:20:04 +00:00
c7927f2013
Remove isTwoAddress from Mips.
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llvm-svn: 106465
2010-06-21 20:19:21 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
56c50da3f6
remove redundant instruction.
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llvm-svn: 97374
2010-02-28 07:23:21 +00:00
34d6a4ff17
Remember to define super registers in mips calls.
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llvm-svn: 96504
2010-02-17 20:18:50 +00:00
4aa57ba3ef
mark "addr" as having type "iPTR", eliminating some type comparisons
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in hte generated dag isel fil.
llvm-svn: 96193
2010-02-14 21:53:19 +00:00
4f34432d09
On pic function calls some arguments were marked dead and
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the instruction to load those args removed. This fix PR6071
llvm-svn: 93880
2010-01-19 17:00:43 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
a72a505a80
Added support for fround, fextend and FP_TO_SINT
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llvm-svn: 72483
2009-05-27 17:23:44 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Jack Carter