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620 Commits

Author SHA1 Message Date
Hao Liu d6b40b51c7 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions. 
llvm-svn: 193992
 2013-11-04 14:53:22 +00:00
Chad Rosier 74b65cd811 [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier 20e1f20d69 [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson f80f95fcc7 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Artyom Skrobov c1be9c16bc [ARM] NEON instructions were erroneously decoded from certain invalid encodings 
llvm-svn: 193705
 2013-10-30 18:10:09 +00:00
Chad Rosier be020d0309 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions 
llvm-svn: 193623
 2013-10-29 16:38:59 +00:00
Artyom Skrobov fc12e7016c Make ARM hint ranges consistent, and add tests for these ranges 
llvm-svn: 193238
 2013-10-23 10:14:40 +00:00
Tim Northover 08a8660260 ARM: provide diagnostics on more writeback LDM/STM instructions 
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
 2013-10-22 19:00:39 +00:00
Richard Barton 87dacc38b8 Add hint disassembly syntax for 16-bit Thumb hint instructions. 
Patch by Artyom Skrobov

llvm-svn: 192972
 2013-10-18 14:09:49 +00:00
Chad Rosier fe2f58c8a1 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00
Chad Rosier 37d29173aa [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
 2013-10-17 18:12:29 +00:00
Chad Rosier 846a72539c [AArch64] Add support for NEON scalar negate instruction. 
llvm-svn: 192843
 2013-10-16 21:04:39 +00:00
Chad Rosier 175601d997 [AArch64] Add support for NEON scalar absolute value instruction. 
llvm-svn: 192842
 2013-10-16 21:04:34 +00:00
Chad Rosier abe458d0bf Update comment. 
llvm-svn: 192806
 2013-10-16 16:30:10 +00:00
Chad Rosier 178b1cefc7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
 2013-10-16 16:09:02 +00:00
Chad Rosier 9d51708677 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

llvm-svn: 192733
 2013-10-15 21:18:44 +00:00
Chad Rosier d1f40d760a [AArch64] Add support for NEON scalar integer compare instructions. 
llvm-svn: 192596
 2013-10-14 14:37:20 +00:00
Craig Topper 4432208884 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 
llvm-svn: 192566
 2013-10-14 01:42:32 +00:00
Benjamin Kramer 8a37f63714 Mips: Disassemble sign-extended 64 bit immediates properly. 
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
 2013-10-11 19:05:08 +00:00
Chad Rosier 9849cc6696 [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
 2013-10-08 22:09:04 +00:00
Chad Rosier f7ed96ef76 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

llvm-svn: 192231
 2013-10-08 20:43:30 +00:00
Craig Topper 72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
llvm-svn: 192171
 2013-10-08 05:53:50 +00:00
Chad Rosier b6ceeb9126 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
 2013-10-07 16:36:15 +00:00
Joey Gouly 5aec0598ad [ARMv8] Add some disassembly tests for Thumb sevl/sevl.w 
llvm-svn: 192106
 2013-10-07 16:13:03 +00:00
Craig Topper 07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
llvm-svn: 192090
 2013-10-07 07:19:47 +00:00
Craig Topper 2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
llvm-svn: 192086
 2013-10-07 04:28:06 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Richard Sandiford b63e300b67 [SystemZ] Add comparisons of high words and memory 
llvm-svn: 191777
 2013-10-01 15:00:44 +00:00
Richard Sandiford a9ac0e0f75 [SystemZ] Add comparisons of large immediates using high words 
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
 2013-10-01 14:56:23 +00:00
Richard Sandiford 42a694f44e [SystemZ] Add immediate addition involving high words 
llvm-svn: 191774
 2013-10-01 14:53:46 +00:00
Joey Gouly ad98f1671d [ARM] Introduce the 'sevl' instruction in ARMv8. 
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
 2013-10-01 12:39:11 +00:00
Richard Sandiford 5469c39a26 [SystemZ] Add truncating high-word stores (STCH and STHH) 
llvm-svn: 191743
 2013-10-01 12:22:49 +00:00
Richard Sandiford 0d46b1a30f [SystemZ] Add zero-extending high-word loads (LLCH and LLHH) 
llvm-svn: 191742
 2013-10-01 12:19:08 +00:00
Richard Sandiford 89e160d975 [SystemZ] Add sign-extending high-word loads (LBH and LHH) 
llvm-svn: 191740
 2013-10-01 12:11:47 +00:00
Richard Sandiford a26a4b4f60 [SystemZ] Reapply: Add definitions of LFH and STFH 
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738
 2013-10-01 10:31:04 +00:00
Richard Sandiford a25f268c25 [SystemZ] Revert r191661: Add definitions of LFH and STFH 
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.

llvm-svn: 191663
 2013-09-30 12:01:35 +00:00
Richard Sandiford d30ac3a125 [SystemZ] Add definitions of LFH and STFH 
llvm-svn: 191661
 2013-09-30 10:50:33 +00:00
Craig Topper 93a3d5973d Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits. 
llvm-svn: 191650
 2013-09-30 02:50:51 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes. 
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
 2013-09-30 02:46:36 +00:00
Robert Wilhelm f0cfb83bb4 Fix spelling intruction -> instruction. 
llvm-svn: 191610
 2013-09-28 11:46:15 +00:00
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction. 
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
 2013-09-27 01:44:23 +00:00
Amara Emerson 3308909508 [ARMv8] Add support for the v8 cryptography extensions. 
llvm-svn: 190996
 2013-09-19 11:59:01 +00:00
Richard Sandiford 93183ee78c [SystemZ] Add unsigned compare-and-branch instructions 
For some reason I never got around to adding these at the same time as
the signed versions.  No idea why.

I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether
it should just be replaced with an "is normal" flag.  I'll leave that
for later though.

There are some boundary conditions that can be tweaked, such as preferring
unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256",
but again I'll leave those for a separate patch.

llvm-svn: 190930
 2013-09-18 09:56:40 +00:00
Joey Gouly 36b2e5de3c 'svn add' the test cases. 
llvm-svn: 190929
 2013-09-18 09:46:49 +00:00
Ben Langmuir 8eb45a4ef6 Add the remaining Intel SHA instructions 
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.

llvm-svn: 190754
 2013-09-14 15:03:21 +00:00
Zoran Jovanovic fc26cfcde7 Fixed bug when generating Load Upper Immediate microMIPS instruction. 
llvm-svn: 190746
 2013-09-14 07:35:41 +00:00
Zoran Jovanovic 3671a5441a Support for microMIPS DIV instructions. 
llvm-svn: 190745
 2013-09-14 07:15:21 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions. 
llvm-svn: 190744
 2013-09-14 06:49:25 +00:00