Commit Graph

301705 Commits

Author SHA1 Message Date
Evandro Menezes 769d4cebad [AArch64] Refactor Exynos machine model (NFC)
llvm-svn: 345187
2018-10-24 20:03:24 +00:00
Evandro Menezes 80bc136732 [AArch64] Fix overlapping instructions
Fix overlapping instruction descriptions in the machine model for Exynos M3.
Effectively, NFC.

llvm-svn: 345186
2018-10-24 20:03:20 +00:00
Andrea Di Biagio cd4deea1c4 [llvm-mca] Simplify the logic in FetchStage. NFCI
Only method 'getNextInstruction()' needs to interact with the SourceMgr.

llvm-svn: 345185
2018-10-24 19:37:45 +00:00
Simon Pilgrim 5369168983 Fix MSVC "truncation from 'double' to 'float'" warnings. NFCI.
llvm-svn: 345184
2018-10-24 19:31:24 +00:00
Craig Topper 7bb8c2e6e5 [X86] Explicitly list all KNL features of inheriting from IVB. NFC
I'm not sure all the microarchitectural tuning flags that have been added to IVBFeatures are relevant for KNL. Separating will allow us to see and audit them. There might even be some simplification opportunities in the Sandy Bridge through Icelake inheritance line without KNL using the same chain.

llvm-svn: 345183
2018-10-24 19:24:44 +00:00
Simon Pilgrim c5bb362b13 [X86][SSE] Add SimplifyDemandedBitsForTargetNode PMULDQ/PMULUDQ handling
Add X86 SimplifyDemandedBitsForTargetNode and use it to simplify PMULDQ/PMULUDQ target nodes.

This enables us to repeatedly simplify the node's arguments after the previous approach had to be reverted due to PR39398.

Differential Revision: https://reviews.llvm.org/D53643

llvm-svn: 345182
2018-10-24 19:11:28 +00:00
Konstantin Zhuravlyov 06570954e2 AMDGPU: Handle gfx909 in AMDGPUTargetInfo::initFeatureMap
+ add required tests

llvm-svn: 345181
2018-10-24 19:07:56 +00:00
Alexey Bataev ac6e4de714 Do not always request an implicit taskgroup region inside the kmpc_taskloop function
Summary:
For the following code:
```
    int i;
    #pragma omp taskloop
    for (i = 0; i < 100; ++i)
    {}

    #pragma omp taskloop nogroup
    for (i = 0; i < 100; ++i)
    {}
```

Clang emits the following LLVM IR:

```
 ...
  call void @__kmpc_taskgroup(%struct.ident_t* @0, i32 %0)
  %2 = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 %0, i32 1, i64 80, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
  ...
  call void @__kmpc_taskloop(%struct.ident_t* @0, i32 %0, i8* %2, i32 1, i64* %8, i64* %9, i64 %13, i32 0, i32 0, i64 0, i8* null)
  call void @__kmpc_end_taskgroup(%struct.ident_t* @0, i32 %0)

  ...
  %15 = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 %0, i32 1, i64 80, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.1*)* @.omp_task_entry..2 to i32 (i32, i8*)*))
  ...
  call void @__kmpc_taskloop(%struct.ident_t* @0, i32 %0, i8* %15, i32 1, i64* %21, i64* %22, i64 %26, i32 0, i32 0, i64 0, i8* null)

```

The first set of instructions corresponds to the first taskloop construct. It is important to note that the implicit taskgroup region associated with the taskloop construct has been materialized in our IR:  the `__kmpc_taskloop` occurs inside a taskgroup region. Note also that this taskgroup region does not exist in our second taskloop because we are using the `nogroup` clause.

The issue here is the 4th argument of the kmpc_taskloop call, starting from the end,  is always a zero. Checking the LLVM OpenMP RT implementation, we see that this argument corresponds to the nogroup parameter:

```
void __kmpc_taskloop(ident_t *loc, int gtid, kmp_task_t *task, int if_val,
                     kmp_uint64 *lb, kmp_uint64 *ub, kmp_int64 st, int nogroup,
                     int sched, kmp_uint64 grainsize, void *task_dup);
```

So basically we always tell to the RT to do another taskgroup region. For the first taskloop, this means that we create two taskgroup regions. For the second example, it means that despite the fact we had a nogroup clause we are going to have a taskgroup region, so we unnecessary wait until all descendant tasks have been executed.

Reviewers: ABataev

Reviewed By: ABataev

Subscribers: rogfer01, cfe-commits

Differential Revision: https://reviews.llvm.org/D53636

llvm-svn: 345180
2018-10-24 19:06:37 +00:00
Simon Pilgrim 6f53b38fd4 [TargetLowering] Add SimplifyDemandedBitsForTargetNode callback
Add a SimplifyDemandedBitsForTargetNode callback to handle target nodes.

Differential Revision: https://reviews.llvm.org/D53643

llvm-svn: 345179
2018-10-24 19:00:56 +00:00
Teresa Johnson c8dba682bb [hot-cold-split] Name split functions with ".cold" suffix
Summary:
The current default of appending "_"+entry block label to the new
extracted cold function breaks demangling. Change the deliminator from
"_" to "." to enable demangling. Because the header block label will
be empty for release compile code, use "extracted" after the "." when
the label is empty.

Additionally, add a mechanism for the client to pass in an alternate
suffix applied after the ".", and have the hot cold split pass use
"cold."+Count, where the Count is currently 1 but can be used to
uniquely number multiple cold functions split out from the same function
with D53588.

Reviewers: sebpop, hiraditya

Subscribers: llvm-commits, erik.pilkington

Differential Revision: https://reviews.llvm.org/D53534

llvm-svn: 345178
2018-10-24 18:53:47 +00:00
Alexey Bataev b40e0520e1 [OPENMP]Fix PR39366: do not try to private field if it is not captured.
The compiler is crashing if we trying to post-capture the fields
implicitly captured inside of the task constructs. Seems, this kind of
processing is not supported and such fields should not be
firstprivatized.

llvm-svn: 345177
2018-10-24 18:53:12 +00:00
Craig Topper 5dd94e50c9 [CodeGen] Update test checks missed in r345168.
These tests don't run unless the aarch64 target is registered and my testing had been on an x86 only build directory.

llvm-svn: 345176
2018-10-24 18:45:44 +00:00
Simon Pilgrim ac84005841 [CostModel][X86] Add vXi8 vector division by constants costs.
ISD::MULHS/ISD::MULHU lowering of vXi8 types means we expand these in TargetLowering BuildSDIV/BuildUDIV.

llvm-svn: 345175
2018-10-24 18:44:12 +00:00
Kuba Mracek 6b6d9bbd48 [sanitizer] Avoid calling a nullptr in MonotonicNanoTime if interceptors are not yet initialized
There's a TSan startup crash on Linux when used in Swift programs, where MonotonicNanoTime will try to call real_clock_gettime and then jump to NULL because interceptors are not yet initialized. This is on Ubuntu 18.04. Looks like TSan's main Initialize() function is called at a point where __progname is already set, but interceptors aren't yet set up. Let's fix this by checking whether interceptors are initialized in MonotonicNanoTime.

Differential Revision: https://reviews.llvm.org/D53528

llvm-svn: 345174
2018-10-24 18:40:08 +00:00
Eric Fiselier 5efe8ec4cd Fix use of libc++ specific macro in support/test_macros.h
llvm-svn: 345173
2018-10-24 18:37:42 +00:00
Rui Ueyama aa2948776a Include input section name and output section name in an error message.
Differential Revision: https://reviews.llvm.org/D53645

llvm-svn: 345172
2018-10-24 18:15:40 +00:00
Peter Collingbourne 4bb928c110 ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.
The BKPT instruction is specified to cause a software breakpoint,
and at least on Linux results in a SIGTRAP. This makes it more
suitable for implementing debugtrap than TRAP (aka UDF #254), which
is specified to cause an undefined instruction exception and results
in a SIGILL on Linux.

Moreover, BKPT is not marked as a terminator, which is not only
consistent with the IR instruction but allows the analyzeBlock
function to correctly analyze a basic block containing the instruction,
which fixes an assertion failure in the machine block placement pass
previously triggered by the included test case.

Because BKPT is only supported starting with ARMv5T, we continue to
use UDF #254 when targeting v4T.

Differential Revision: https://reviews.llvm.org/D53614

llvm-svn: 345171
2018-10-24 18:10:38 +00:00
Krzysztof Parzyszek f124275cf9 [Hexagon] Flip hexagon-autohvx to be true by default
This will allow other generators of LLVM IR to use the auto-vectorizer
without having to change that flag.

Note: on its own, this patch will disable auto-vectorization on Hexagon
in all cases, regardless of the -fvectorize flag. There is a companion
LLVM patch that together with this one forms an NFC for clang users.

llvm-svn: 345170
2018-10-24 17:55:18 +00:00
Krzysztof Parzyszek 57b5ac1431 [Hexagon] Flip hexagon-autohvx to be true by default
This will allow other generators of LLVM IR to use the auto-vectorizer
without having to change that flag.

Note: on its own, this patch will enable auto-vectorization on Hexagon
in all cases, regardless of the -fvectorize flag. There is a companion
clang patch that together with this one forms an NFC for clang users.

llvm-svn: 345169
2018-10-24 17:55:13 +00:00
Craig Topper 3113ec3dc7 [CodeGen] Update min-legal-vector width based on function argument and return types
This is a continuation of my patches to inform the X86 backend about what the largest IR types are in the function so that we can restrict the backend type legalizer to prevent 512-bit vectors on SKX when -mprefer-vector-width=256 is specified if no explicit 512 bit vectors were specified by the user.

This patch updates the vector width based on the argument and return types of the current function and from the types of any functions it calls. This is intended to make sure the backend type legalizer doesn't disturb any types that are required for ABI.

Differential Revision: https://reviews.llvm.org/D52441

llvm-svn: 345168
2018-10-24 17:42:17 +00:00
Jonas Toth 618c0bc363 [clang-tidy] Add the abseil-duration-factory-float check
Summary:
This check finds cases where calls to an absl::Duration factory could use the more efficient integer overload.

For example:
// Original - Providing a floating-point literal.
absl::Duration d = absl::Seconds(10.0);

// Suggested - Use an integer instead.
absl::Duration d = absl::Seconds(10);

Patch by hwright.

Reviewers: alexfh, hokein, aaron.ballman, JonasToth

Reviewed By: hokein, JonasToth

Subscribers: zturner, xazax.hun, Eugene.Zelenko, mgorny, cfe-commits

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D53339

llvm-svn: 345167
2018-10-24 17:40:50 +00:00
Michael Kruse c342c8b87e [docs] Add rawspeed to test-suite proposals.
rawspeed was suggested by Simon Pilgrim and Roman Lebedev in
llvm.org/PR34216 and reviews.llvm.org/D46714.

llvm-svn: 345166
2018-10-24 17:35:35 +00:00
Craig Topper 2417273255 [X86] Bring back the MOV64r0 pseudo instruction
This patch brings back the MOV64r0 pseudo instruction for zeroing a 64-bit register. This replaces the SUBREG_TO_REG MOV32r0 sequence we use today. Post register allocation we will rewrite the MOV64r0 to a 32-bit xor with an implicit def of the 64-bit register similar to what we do for the various XMM/YMM/ZMM zeroing pseudos.

My main motivation is to enable the spill optimization in foldMemoryOperandImpl. As we were seeing some code that repeatedly did "xor eax, eax; store eax;" to spill several registers with a new xor for each store. With this optimization enabled we get a store of a 0 immediate instead of an xor. Though I admit the ideal solution would be one xor where there are multiple spills. I don't believe we have a test case that shows this optimization in here. I'll see if I can try to reduce one from the code were looking at.

There's definitely some other machine CSE(and maybe other passes) behavior changes exposed by this patch. So it seems like there might be some other deficiencies in SUBREG_TO_REG handling.

Differential Revision: https://reviews.llvm.org/D52757

llvm-svn: 345165
2018-10-24 17:32:09 +00:00
Simon Pilgrim 2cce074e8c [CostModel][X86] Enable non-uniform vector division by constants costs.
Non-uniform division/remainder handling was added back at D49248/D50765 - so share the 'mul+sub' costs that already exist for uniform cases.

llvm-svn: 345164
2018-10-24 17:30:29 +00:00
Robert Lougher 18bfb3a5ec [CodeGen] skip lifetime end marker in isInTailCallPosition
A lifetime end intrinsic between a tail call and the return should not
prevent the call from being tail call optimized.

Differential Revision: https://reviews.llvm.org/D53519

llvm-svn: 345163
2018-10-24 17:03:19 +00:00
Sanjay Patel d1fe437cf1 [InstCombine] add test for ComputeNumSignBits with shuffle; NFC
llvm-svn: 345162
2018-10-24 17:01:42 +00:00
Andrea Di Biagio 65c77d7283 [llvm-mca] Remove dependency from InstrBuilder in class InstructionTables.
Also, removed the initialization of vectors used for processor resource masks.
Support function 'computeProcResourceMasks()' already calls method resize on
those vectors.
No functional change intended.

llvm-svn: 345161
2018-10-24 16:56:43 +00:00
Saleem Abdulrasool d5a27884b1 CodeGen: extract some local variables in CFConstantString creation (NFC)
Extract the reference to the ASTContext and Triple and use them throughout the
function.  This is simply a cosmetic cleanup while in the area.  NFC.

llvm-svn: 345160
2018-10-24 16:56:36 +00:00
Saleem Abdulrasool ef9b88a1d4 AST: unindent CFConstantStringDecl by inverting condition (NFC)
Unindent the body of the function by inverting check at the top.  This is in
preparation for supporting CFString's new ABI with swift.  NFC.

llvm-svn: 345159
2018-10-24 16:38:16 +00:00
Simon Pilgrim c8c7451063 [LegalizeDAG] ExpandLegalINT_TO_FP - cleanup UINT_TO_FP i64 -> f32 expansion.
Use SrcVT/DestVT types and correct shift type.

Part of prep work for D52965

llvm-svn: 345158
2018-10-24 16:35:01 +00:00
George Rimar 8c58a6e7d6 Revert rL345127: [LLDB] - Add support for DW_RLE_base_address and DW_RLE_offset_pair entries
It broke BB:
http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/11671/consoleFull#434797663d489585b-5106-414a-ac11-3ff90657619c

llvm-svn: 345157
2018-10-24 16:21:56 +00:00
Sanjay Patel 2169b9c976 [InstCombine] add test for select with shuffled condition (PR37549); NFC
llvm-svn: 345156
2018-10-24 16:21:23 +00:00
Kuba Mracek d0243aa3e5 [lldb] Remove enableThreadSanitizer from shared Xcode schemes
This was probably committed accidentally and default Xcode builds of LLDB now have TSan on. Let's turn it off.

llvm-svn: 345155
2018-10-24 15:59:31 +00:00
Rui Ueyama 8d76024916 Refactor assignFileOffsets. NFC.
llvm-svn: 345154
2018-10-24 15:47:46 +00:00
Kadir Cetinkaya b915790385 [clangd] Do not query index for new name completions.
Reviewers: sammccall

Reviewed By: sammccall

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, cfe-commits

Differential Revision: https://reviews.llvm.org/D53192

llvm-svn: 345153
2018-10-24 15:24:29 +00:00
Kadir Cetinkaya b006e0995f [clang] Introduce new completion context types
Summary: New name suggestions were being used in places where existing names should have been used, this patch tries to fix some of those situations.

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: arphaman, cfe-commits

Differential Revision: https://reviews.llvm.org/D53191

llvm-svn: 345152
2018-10-24 15:23:49 +00:00
Krasimir Georgiev 09ea204964 IR: Optimize FunctionType::get to perform one hash lookup instead of two, NFCI
Summary: This function was performing two hash lookups when a new function type was requested: first checking if it exists and second to insert it. This patch updates the function to perform a single hash lookup in this case by updating the value in the hash table in-place in case the function type was not there before.

Reviewers: bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D53471

llvm-svn: 345151
2018-10-24 15:18:51 +00:00
Sam McCall d7babe4e12 [clangd] When replying, log the method name and latency.
Summary:
This information is strictly available in the log (you can find the original
call) but it makes the log easier to follow in practice.

Reviewers: kadircet

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, cfe-commits

Differential Revision: https://reviews.llvm.org/D53647

llvm-svn: 345150
2018-10-24 15:18:40 +00:00
Sanjay Patel 3b206305fd [InstCombine] try harder to form select from logic ops (2nd try)
The original patch was committed here:
rL344609
...and reverted:
rL344612
...because it did not properly check/test data types before calling
ComputeNumSignBits(). 

The tests that caused bot failures for the previous commit are 
over-reaching front-end tests that run the entire -O optimizer 
pipeline: 
    Clang :: CodeGen/builtins-systemz-zvector.c
    Clang :: CodeGen/builtins-systemz-zvector2.c

I've added a negative test here to ensure coverage for that case.
The new early exit check also tests the type of the 'B' parameter,
so we don't waste time on matching if either value is unsuitable.

Original commit message:

This is part of solving PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549

The patterns shown here are a special case of something
that we already convert to select. Using ComputeNumSignBits()
catches that case (but not the more complicated motivating
patterns yet).

The backend has hooks/logic to convert back to logic ops
if that's better for the target.

llvm-svn: 345149
2018-10-24 15:17:56 +00:00
Mikhail Maltsev b7e43df3c2 Adjust unsupported C++ versions in some tests
Summary:
Some tests (mainly the new C++20 calendar library) fail when libc++ is
tested with '--param=std=c++98'. The failures happen because the tests
actually don't support C++98, but don't mention C++98 in the
'UNSUPPORTED:' line.

This change fixes the issue.

Reviewers: mclow.lists, ldionne

Reviewed By: ldionne

Subscribers: arphaman, michaelplatings, libcxx-commits

Differential Revision: https://reviews.llvm.org/D53640

llvm-svn: 345148
2018-10-24 15:09:08 +00:00
Andrea Di Biagio 7be45b0f85 [llvm-mca] Refactor class SourceMgr. NFCI
Added begin()/end() methods to allow the usage of SourceMgr in foreach loops.
With this change, method getMCInstFromIndex() (as well as a couple of other
methods) are now redundant, and can be removed from the public interface.

llvm-svn: 345147
2018-10-24 15:06:27 +00:00
Cameron McInally 678f43f666 [FPEnv] Convert more BinaryOperator::isFNeg(...) to m_FNeg(...)
This work is to avoid regressions when we seperate FNeg from the FSub IR instruction. 

Differential Revision: https://reviews.llvm.org/D53205

llvm-svn: 345146
2018-10-24 14:45:18 +00:00
Erich Keane dafdd049fc Remove a pair of unused dispatch multiversion declarations.
These declarations somehow survived a cleanup that combined them with the target
multiversioning functions.  This patch removes them as they are no
longer necessary or used.

Change-Id: I318286401ace63bef1aa48018dabb25be0117ca0
llvm-svn: 345145
2018-10-24 14:33:30 +00:00
Sam McCall e2f3a7348d [clangd] Ensure that we reply to each call exactly once. NFC (I think!)
Summary:
In debug builds, getting this wrong will trigger asserts.
In production builds, it will send an error reply if none was sent,
and drop redundant replies. (And log).

No tests because this is always a programming error.
(We did have some cases of this, but I fixed them with the new dispatcher).

Reviewers: ioeric

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, jfb, kadircet, cfe-commits

Differential Revision: https://reviews.llvm.org/D53399

llvm-svn: 345144
2018-10-24 14:26:26 +00:00
Rui Ueyama 6d26ed92cc Split a function. NFC.
llvm-svn: 345143
2018-10-24 14:24:01 +00:00
Alexey Bataev c15c853c3a [DEBUGINFO, NVPTX] Try to pack bytes data into a single string.
Summary:
If the target does not support `.asciz` and `.ascii` directives, the
strings are represented as bytes and each byte is placed on the new line
as a separate byte directive `.b8 <data>`. NVPTX target allows to
represent the vector of the data of the same type as a vector, where
values are separated using `,` symbol: `.b8 <data1>,<data2>,...`. This
allows to reduce the size of the final PTX file. Ptxas tool includes ptx
files into the resulting binary object, so reducing the size of the PTX
file is important.

Reviewers: tra, jlebar, echristo

Subscribers: jholewinski, llvm-commits

Differential Revision: https://reviews.llvm.org/D45822

llvm-svn: 345142
2018-10-24 14:04:00 +00:00
Sam McCall e8437cbf5e [clangd] Don't show base class versions of members as completions.
Summary:
These are available via qualifiers, but signal to noise level is low.
Keep required quailifier machinery around though, for cross-ns completion.

Reviewers: ioeric

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Differential Revision: https://reviews.llvm.org/D53571

llvm-svn: 345141
2018-10-24 13:51:44 +00:00
Eric Liu 52a11b5662 [clangd] Downrank members from base class
Reviewers: sammccall, ilya-biryukov

Reviewed By: sammccall

Subscribers: MaskRay, jkorous, arphaman, kadircet, cfe-commits

Differential Revision: https://reviews.llvm.org/D53638

llvm-svn: 345140
2018-10-24 13:45:17 +00:00
Rui Ueyama 6e763a36c6 Add parenthese around a bitand.
llvm-svn: 345139
2018-10-24 13:44:51 +00:00
Rui Ueyama ee2b61cfd3 Make a local variable scope narrower. NFC.
llvm-svn: 345138
2018-10-24 13:42:33 +00:00