c313d94068
Saving files before committing is overrated.
...
Add a RUN line to this test.
llvm-svn: 127520
2011-03-12 01:36:23 +00:00
174d872702
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
6d371ce37e
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
338d362200
Roll r127459 back in:
...
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127498
2011-03-11 21:52:04 +00:00
4d7d728594
Fix the GCC test suite issue exposed by r127477, which was caused by stack
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protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.
llvm-svn: 127497
2011-03-11 21:51:56 +00:00
94ccb27b43
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
...
created from the", it broke some GCC test suite tests.
llvm-svn: 127477
2011-03-11 19:30:30 +00:00
cc27b3acc4
Optimize trivial branches in CodeGenPrepare, which often get created from the
...
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
llvm-svn: 127459
2011-03-11 04:54:27 +00:00
cf56a5034f
Change the x86 32-bit scheduler to register pressure and fix up the
...
corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
llvm-svn: 127441
2011-03-11 01:05:58 +00:00
adb9c03e41
Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
...
llvm-svn: 127440
2011-03-11 00:48:56 +00:00
62a7b473af
Properly pseudo-ize MOVCCr and MOVCCs.
...
llvm-svn: 127434
2011-03-10 23:56:09 +00:00
72ff7e4fa9
PTX: Add preliminary support for floating-point divide and multiply-and-add
...
llvm-svn: 127410
2011-03-10 16:57:18 +00:00
6e9fb0d056
ptx: add the rest of special registers of ISA version 2.0
...
llvm-svn: 127397
2011-03-10 04:05:57 +00:00
d17ae4e939
Revert 127359; it broke lencod.
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llvm-svn: 127382
2011-03-10 00:25:53 +00:00
66559ba79a
Revert "Re-enable test and hope to silence the buildbots", still broken.
...
llvm-svn: 127369
2011-03-09 22:48:46 +00:00
1885d21700
Fix mistyped CHECK lines.
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llvm-svn: 127366
2011-03-09 22:07:31 +00:00
3d8584f60e
Tweak test to work on Linux.
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llvm-svn: 127364
2011-03-09 21:35:10 +00:00
9ba3013ed9
Disable this test temporarily to reduce BuildBot complaints.
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llvm-svn: 127363
2011-03-09 21:33:47 +00:00
9955e2f912
X86 byval copies no longer always_inline. <rdar://problem/8706628>
...
llvm-svn: 127359
2011-03-09 21:10:30 +00:00
6492ef1237
Add a testcase for the addc improvements introduced some commits ago. Patch by Akira Hatanaka
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llvm-svn: 127358
2011-03-09 21:05:32 +00:00
961908982f
Re-enable test and hope to silence the buildbots
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llvm-svn: 127357
2011-03-09 21:00:16 +00:00
bd2f81c87b
try to make o32 cc tests less specific to silence some buildbots. The test isn't enabled yet, this is will be done in a subsequent commit. Patch by Akira Hatanaka.
...
llvm-svn: 127356
2011-03-09 20:59:05 +00:00
d0db705256
Make physreg coalescing independent on the number of uses of the virtual register.
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The damage done by physreg coalescing only depends on the number of instructions
the extended physreg live range covers. This fixes PR9438.
The heuristic is still luck-based, and physreg coalescing really should be
disabled completely. We need a register allocator with better hinting support
before that is possible.
Convert a test to FileCheck and force spilling by inserting an extra call. The
previous spilling behavior was dependent on misguided physreg coalescing
decisions.
llvm-svn: 127351
2011-03-09 19:27:06 +00:00
456e104c13
Delete a test case that is very sensitive to coalescer behavior.
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The test is derived from an old miscompilation of
MultiSource/Benchmarks/VersaBench/8b10b which is run regularly, so we are not
losing coverage.
llvm-svn: 127350
2011-03-09 19:27:02 +00:00
048ffabe78
Improve varags handling, with testcases. Patch by Sasa Stankovic
...
llvm-svn: 127349
2011-03-09 19:22:22 +00:00
0f6d098bd1
This test case should work with list-ilp or list-burr.
...
llvm-svn: 127348
2011-03-09 19:17:10 +00:00
58d1f93b03
Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4.
...
llvm-svn: 127328
2011-03-09 11:33:15 +00:00
4fa0f3040d
Fix testcase.
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llvm-svn: 127298
2011-03-09 00:41:41 +00:00
128e9f0fe9
Strip cruft.
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llvm-svn: 127269
2011-03-08 20:19:10 +00:00
eee5413f3b
Add a testcase for r127263.
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llvm-svn: 127266
2011-03-08 19:49:15 +00:00
679cfb54ec
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1.
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Found by inspection.
llvm-svn: 127247
2011-03-08 15:20:20 +00:00
42e9aaa4b1
PTX: Add intrinsic support for ntid, ctaid, and nctaid registers
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llvm-svn: 127246
2011-03-08 14:10:18 +00:00
eb19e9e9fc
Turn on list-ilp scheduling by default on x86 and x86-64, fix up
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testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
llvm-svn: 127208
2011-03-08 02:42:25 +00:00
45acbd03db
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
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llvm-svn: 127198
2011-03-08 01:17:20 +00:00
369ea3fdb4
ptx: add basic intrinsic support
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llvm-svn: 127084
2011-03-05 14:17:37 +00:00
6f9a8f85d7
test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424.
...
llvm-svn: 127060
2011-03-05 02:38:02 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
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llvm-svn: 127034
2011-03-04 21:03:24 +00:00
d631599e38
Add testcase for r127032
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llvm-svn: 127033
2011-03-04 20:48:39 +00:00
aa036eedb8
When decling to reuse existing expressions that involve casts, ignore
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bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.
llvm-svn: 127031
2011-03-04 20:46:46 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
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that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
906df92d5c
XFAIL for all. These tests are darwin specific anyway.
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llvm-svn: 127022
2011-03-04 19:38:10 +00:00
a0d73fd65e
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
...
llvm-svn: 127019
2011-03-04 19:11:05 +00:00
a1d947dd14
Allow vector shifts (shl,lshr,ashr) on SPU.
...
There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
llvm-svn: 126998
2011-03-04 13:19:18 +00:00
3531e9b0d9
Allow load from constant on SPU.
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A 'load <4 x i32>* null' crashes llc before this fix.
llvm-svn: 126995
2011-03-04 12:00:11 +00:00
d8a555bb3b
Revert r123908; the code in question is completely untested and wrong.
...
llvm-svn: 126964
2011-03-03 22:33:23 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
3e7f2366fb
Test case for r126864. Radar 9056407.
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llvm-svn: 126900
2011-03-02 23:41:40 +00:00
dd567b214b
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
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missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
llvm-svn: 126845
2011-03-02 17:23:43 +00:00
5dd2aa2615
Eliminate the unused CodeGenPrepare option to split critical edges.
...
llvm-svn: 126825
2011-03-02 03:31:46 +00:00
65b1476031
Extend initial support for primitive types in PTX backend
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- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
llvm-svn: 126824
2011-03-02 03:20:28 +00:00
7290868a1b
Don't re-use existing addrec expansions if they contain casts.
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This fixes PR9259.
llvm-svn: 126812
2011-03-02 01:34:10 +00:00
15fed7af3c
Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648.
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llvm-svn: 126811
2011-03-02 01:08:17 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
87d7408f29
Fix typo introduced by r126661: "Fix a typo which ..."
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llvm-svn: 126666
2011-02-28 19:18:59 +00:00
6e3d443646
Fix a typo which cause dag combine crash. rdar://9059537.
...
llvm-svn: 126661
2011-02-28 18:45:27 +00:00
f66e4611f9
Windows codegen also dies on this, so restrict to the platform it was
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actually tested on.
llvm-svn: 126652
2011-02-28 14:22:08 +00:00
feb9926a59
Make this test x86 specific because the ARM backend can't handle it.
...
llvm-svn: 126650
2011-02-28 12:30:47 +00:00
75a800d3bf
Add preliminary support for .f32 in the PTX backend.
...
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
llvm-svn: 126636
2011-02-28 06:34:09 +00:00
f571290d1e
Legalize support for fpextend of vector. PR9309.
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llvm-svn: 126574
2011-02-27 14:41:27 +00:00
d4e5003a3f
Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.
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It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
llvm-svn: 126568
2011-02-27 08:47:19 +00:00
68f677a612
Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses.
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llvm-svn: 126567
2011-02-27 08:06:01 +00:00
baeb5f1431
Give a test file a more sensible name so that it can hold more test cases.
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llvm-svn: 126566
2011-02-27 08:05:57 +00:00
26691d9660
Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
...
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
llvm-svn: 126557
2011-02-26 22:48:07 +00:00
e3ecd5fb9b
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
...
llvm-svn: 126477
2011-02-25 06:42:42 +00:00
502f1b943f
Enable support for vector sext and trunc:
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Limit the folding of any_ext and sext into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.
Similar to commit 126080 (for enabling zext).
llvm-svn: 126424
2011-02-24 21:01:34 +00:00
b52040da17
Move arch specific tests in arch specific directories.
...
llvm-svn: 126401
2011-02-24 19:06:27 +00:00
42f52e737e
Add XCore intrinsic for eeu instruction.
...
llvm-svn: 126384
2011-02-24 13:39:18 +00:00
a62fc89a04
Merge information about the number of zero, one, and sign bits of live-out
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registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.
llvm-svn: 126380
2011-02-24 10:00:25 +00:00
3923466e82
Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory
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operands starts at index 2, not 1.
rdar://9045024
PR9305
llvm-svn: 126359
2011-02-24 02:36:52 +00:00
7b0f796c55
Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range.
...
llvm-svn: 126339
2011-02-23 22:37:04 +00:00
37e056e455
Check only relevant strings in output to increase stability of the tests.
...
llvm-svn: 126338
2011-02-23 22:35:57 +00:00
bfa5cc0e08
Add XCore intrinsic for clre instruction.
...
llvm-svn: 126322
2011-02-23 18:52:05 +00:00
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
2c610aa3ed
Add XCore intrinsic for the setv instruction.
...
llvm-svn: 126315
2011-02-23 16:46:37 +00:00
aab96995f6
Add XCore intrinsic for settw instruction.
...
llvm-svn: 126313
2011-02-23 14:45:03 +00:00
d6b641e5bc
More fcopysign correctness and performance fix.
...
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
llvm-svn: 126295
2011-02-23 02:24:55 +00:00
7f5aa90d62
Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311."
...
It seems it affected configuration --target=i686-pc-mingw32, I don't know and will investigate why.
llvm-svn: 126217
2011-02-22 08:22:54 +00:00
bced59bba7
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126216
2011-02-22 07:21:59 +00:00
384490cbe1
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126215
2011-02-22 07:21:51 +00:00
2a1ca28203
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126214
2011-02-22 07:21:42 +00:00
fae5813d40
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126213
2011-02-22 07:21:33 +00:00
4d9d6ed377
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126212
2011-02-22 07:21:25 +00:00
af669e5a4e
Relax expressions and add explicit triplets -linux and -win32.
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On @foobar(double %d, double* %x),
AMD64: (%xmm0, %rdi)
Win64: (%xmm0, %rdx) (not %rcx!)
llvm-svn: 126211
2011-02-22 07:21:17 +00:00
a1e2ed5f1b
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126210
2011-02-22 07:21:08 +00:00
e38080bd8e
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126209
2011-02-22 07:21:01 +00:00
e463e07bd5
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126208
2011-02-22 07:20:52 +00:00
0e9c4e50ac
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126207
2011-02-22 07:20:44 +00:00
3632cf8e6b
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126206
2011-02-22 07:20:35 +00:00
09ee8a7f92
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126205
2011-02-22 07:20:26 +00:00
a403732301
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126204
2011-02-22 07:20:18 +00:00
3940b8fd65
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126203
2011-02-22 07:20:10 +00:00
eaf128bde6
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126202
2011-02-22 07:20:02 +00:00
82cd8e9ebb
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126201
2011-02-22 07:19:54 +00:00
83c40bc7ad
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126200
2011-02-22 07:19:46 +00:00
3bfc830a9a
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126199
2011-02-22 07:19:37 +00:00
46e7e345e2
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126198
2011-02-22 07:19:28 +00:00
eff7bdb792
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126197
2011-02-22 07:19:20 +00:00
6df04c2d20
Relax expressions and add explicit triplets -linux and -win32.
...
llvm-svn: 126196
2011-02-22 07:19:12 +00:00
f4e6f323cb
test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311.
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llvm-svn: 126195
2011-02-22 07:19:03 +00:00
9cb20ac2e8
test/CodeGen/X86/red-zone.ll: Add explicit -mtriple=x86_64-linux.
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Redzone is not applicable on Win64.
llvm-svn: 126194
2011-02-22 07:18:55 +00:00
Eric Christopher