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10 Commits

Author SHA1 Message Date
Simon Dardis 730fdb73a1 [mips] Correct c.cond.fmt instruction definition. 
Permit explicit $fcc<X> operand in c.cond.fmt instruction.

Add c.cond.fmt to the MIPS to microMIPS instruction mapping table.

Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for
c.cond.fmt, bc1t, bc1f.

Reviewers: seanbruno, zoran.jovanovic, vkalintiris

Differential Revision: https://reviews.llvm.org/D24510

llvm-svn: 292117
 2017-01-16 13:55:58 +00:00
Simon Dardis f45a59f80b Recommit: "[mips] Add rsqrt, recip for MIPS" 
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Reviewers: vkalintiris, zoran.jovanoic

Differential Review: https://reviews.llvm.org/D24499

llvm-svn: 283334
 2016-10-05 16:11:01 +00:00
Simon Dardis bbfd528748 Revert "[mips] Add rsqrt, recip for MIPS" 
This reverts commit r282485 which contain two patches instead of
one.

llvm-svn: 283327
 2016-10-05 15:28:33 +00:00
Simon Dardis 0486d585c5 [mips] Add rsqrt, recip for MIPS 
Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Reviewers: vkalintiris, zoran.jovanoic

Differential Review: https://reviews.llvm.org/D24499

llvm-svn: 282485
 2016-09-27 12:25:15 +00:00
Simon Dardis ba92b034bf Revert "[mips] Fix c.<cc>.<fmt> instruction definition." 
This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.

llvm-svn: 281033
 2016-09-09 11:06:01 +00:00
Simon Dardis 8efa979029 [mips] Fix c.<cc>.<fmt> instruction definition. 
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Reviewers: dsanders, vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D23118

llvm-svn: 281022
 2016-09-09 09:22:52 +00:00
Daniel Sanders 1493e37f34 [mips][ias] Removed DSP/DSPr2 instructions from base architecture valid-xfail.s's. 
Summary:
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. DSP/DSPr2 instructions are correct to fail since DSP/DSPr2 is
not enabled.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15072

llvm-svn: 254911
 2015-12-07 14:12:44 +00:00
Daniel Sanders d32db286a0 [mips][ias] Removed MSA instructions from base architecture valid-xfail.s's. 
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. MSA instructions are correct to fail since MSA is not enabled.

llvm-svn: 254293
 2015-11-30 09:52:00 +00:00
Vladimir Medic bcb7467540 [MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. 
llvm-svn: 230500
 2015-02-25 15:24:37 +00:00
Daniel Sanders 1779314e3c [mips] Add backend support for Mips32r[35] and Mips64r[35]. 
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381

llvm-svn: 229695
 2015-02-18 16:24:50 +00:00