Commit Graph

177412 Commits

Author SHA1 Message Date
Diana Picus 3533ad6801 [ARM GlobalISel] Select G_FCONSTANT into pools
Put all floating point constants into constant pools and load their
values from there.

llvm-svn: 358062
2019-04-10 09:14:24 +00:00
Diana Picus 165846b031 [ARM GlobalISel] Map G_FCONSTANT
llvm-svn: 358061
2019-04-10 09:14:16 +00:00
David Stenberg 6feef56d1b [DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFC
Summary:
In an upcoming commit the history map will be changed so that it
contains explicit entries for instructions that clobber preceding debug
values, rather than Begin- End range pairs, so generalize the name to
"Entry".

Also, prefix the iterator variable names in buildLocationList() with
"E". In an upcoming commit the entry will have query functions such as
"isD(e)b(u)gValue", which could at a glance make one confuse it for
iterations over MachineInstrs, so make the iterator names a bit more
distinct to avoid that.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59939

llvm-svn: 358060
2019-04-10 09:07:43 +00:00
David Stenberg 3739979c20 [DebugInfo] Make InstrRange into a class, NFC
Summary:
Replace use of std::pair by creating a class for the debug value
instruction ranges instead. This is a preparatory refactoring for
improving handling of clobbered fragments.

In an upcoming commit the Begin pointer will become a PointerIntPair, so
it will be cleaner to have a getter for that.

Reviewers: aprantl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59938

llvm-svn: 358059
2019-04-10 09:07:32 +00:00
Florian Hahn 83443c9a9e [ScheduleDAG] Add statistics for maintaining the topological order.
This is helpful to measure the impact of D60125 on maintaining
topological orders.

Reviewers: MatzeB, atrick, efriedma, niravd

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D60187

llvm-svn: 358058
2019-04-10 09:03:03 +00:00
David Stenberg fab4bdf4b9 Add REQUIRES: asserts to test using -debug-only
llvm-svn: 358057
2019-04-10 08:44:57 +00:00
Florian Hahn db1a69c250 [VPLAN] Minor improvement to testing and debug messages.
1. Use computed VF for stress testing.
2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4.
3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX).

Patch by Francesco Petrogalli <francesco.petrogalli@arm.com>

Differential Revision: https://reviews.llvm.org/D59952

llvm-svn: 358056
2019-04-10 08:17:28 +00:00
Fangrui Song b3be23d334 [DWARF] Simplify LineTable::findRowInSeq
We want the last row whose address is less than or equal to Address.
This can be computed as upper_bound - 1, which is simpler than
lower_bound followed by skipping equal rows in a loop.

Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress)
while LastRow-1 (HighPC) satisfies the predicate. We can decrease the
search range by two, i.e.

upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1)

llvm-svn: 358053
2019-04-10 07:44:23 +00:00
Nikita Popov 09020ec2a7 [InstCombine] Handle usubo always overflow
Check AlwaysOverflow condition for usubo. The implementation is the
same as the existing handling for uaddo and umulo. Handling for saddo
and ssubo will follow (smulo doesn't have the necessary ValueTracking
support).

Differential Revision: https://reviews.llvm.org/D60483

llvm-svn: 358052
2019-04-10 07:10:53 +00:00
Nikita Popov 596cbeb705 [InstCombine] Directly call computeOverflow methods in OptimizeOverflowCheck; NFC
Instead of using the willOverflow helpers. This makes it easier to
extend handling of AlwaysOverflows.

llvm-svn: 358051
2019-04-10 07:10:44 +00:00
Chen Zheng 5e13ff1da2 [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).
Differential Revision: https://reviews.llvm.org/D60395

llvm-svn: 358050
2019-04-10 06:52:09 +00:00
Akira Hatanaka 9ca9d32b6b [ObjC][ARC] Convert the retainRV marker that is passed as a named
metadata into a module flag in the auto-upgrader and make the ARC
contract pass read the marker as a module flag.

This is needed to fix a bug where ARC contract wasn't inserting the
retainRV marker when LTO was enabled, which caused objects returned
from a function to be auto-released.

rdar://problem/49464214

Differential Revision: https://reviews.llvm.org/D60303

llvm-svn: 358047
2019-04-10 06:20:20 +00:00
Craig Topper 391d5caa10 [X86] Move the 2 byte VEX optimization for MOV instructions back to the X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present.
Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior.

llvm-svn: 358046
2019-04-10 05:43:20 +00:00
Fangrui Song 7d4ad14371 [llvm-objdump] Don't print trailing space in dumpBytes
In disassembly output, dumpBytes prints a space, followed by a tab
printed by printInstr. Remove the extra space.

llvm-svn: 358045
2019-04-10 05:31:21 +00:00
Fangrui Song 5f2b5cd85e [llvm-objdump] Accept and ignore --wide/-w
This is similar to what we do for llvm-readobj (--wide/-W is for GNU
readelf compatibility).

The test will be added in D60376.

llvm-svn: 358043
2019-04-10 04:46:01 +00:00
Jim Lin a49c95e02a [Sparc] Fix incorrect MI insertion position for spilling f128.
Summary:
Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.

before fixed:

std %f0, [%g1+80]
sethi 4, %g1        <<<
add %g1, %sp, %g1   <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

after fixed:

sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]

Reviewers: venkatra, jyknight

Reviewed By: jyknight

Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60397

llvm-svn: 358042
2019-04-10 01:56:32 +00:00
Craig Topper 9ca3a95f79 [X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the {evex} pseudo prefix in the assembler.
The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped
them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before
their VEX counterparts. This is different how the prioritization normally works.

To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen.

llvm-svn: 358041
2019-04-10 01:29:59 +00:00
Craig Topper 7143224272 [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.
Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either.
So we should ignore it in our disassembler.

The missing instructions here were found by grepping the raw tablegen class definitions in
the tablegen debug output.

llvm-svn: 358040
2019-04-09 23:30:36 +00:00
Robert Widmann 50f726d73a [LLVM-C] Correct The Current Debug Location Accessors
Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder.  The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned.  Provide direct metadata-based accessors instead.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60484

llvm-svn: 358039
2019-04-09 22:31:56 +00:00
Robert Widmann bec0a45ddc [LLVM-C] Add Bindings to Access an Instruction's DebugLoc
Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation.  In addition, properly accept and return the NULL location.  The old accessors provided no way to do this, so the current debug location cannot currently be cleared.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60481

llvm-svn: 358038
2019-04-09 22:27:51 +00:00
Robert Widmann d1ba3b13f8 [LLVM-C] Add Section and Symbol Iterator Accessors for Object File Binaries
Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests.  I'll do a follow-up patch to do some more cleanup and documentation work in this header.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60407

llvm-svn: 358037
2019-04-09 21:53:31 +00:00
Craig Topper 60f83544bb [X86] Fix a dangling StringRef issue introduced in r358029.
I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory.

Add FIXMEs for the lower case issue which also exists in the prefix parsing code.

llvm-svn: 358036
2019-04-09 21:37:21 +00:00
Amara Emerson 9bf092d719 [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHL
The selection for G_ICMP is unfortunately not currently importable from SDAG
due to the use of custom SDNodes. To support this, this selection method has an
opcode table which has been generated by a script, indexed by various
instruction properties. Ideally in future we will have a GISel native selection
patterns that we can write in tablegen to improve on this.

For selection of some types we also need support for G_ASHR and G_SHL which are
generated as a result of legalization. This patch also adds support for them,
generating the same code as SelectionDAG currently does.

Differential Revision: https://reviews.llvm.org/D60436

llvm-svn: 358035
2019-04-09 21:22:43 +00:00
Amara Emerson 888dd5d198 [AArch64][GlobalISel] Legalize vector G_ICMP.
Selection support will be coming in a later patch.

Differential Revision: https://reviews.llvm.org/D60435

llvm-svn: 358034
2019-04-09 21:22:40 +00:00
Amara Emerson 92d74f19cf [AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.
This is needed for some future support for vector ICMP.

Differential Revision: https://reviews.llvm.org/D60433

llvm-svn: 358033
2019-04-09 21:22:37 +00:00
Amara Emerson 2b523f8162 [GlobalISel][AArch64] Allow CallLowering to handle types which are normally
required to be passed as different register types. E.g. <2 x i16> may need to
be passed as a larger <2 x i32> type, so formal arg lowering needs to be able
truncate it back. Likewise, when dealing with returns of these types, they need
to be widened in the appropriate way back.

Differential Revision: https://reviews.llvm.org/D60425

llvm-svn: 358032
2019-04-09 21:22:33 +00:00
Nikita Popov c176b708e4 [InstCombine] Add with.overflow always overflow tests; NFC
The uadd and umul cases are currently handled, the usub, sadd, ssub
and smul cases are not. usub, sadd and ssub already have the
necessary ValueTracking support, smul doesn't.

llvm-svn: 358031
2019-04-09 20:02:23 +00:00
Craig Topper ba55a40fd0 [AArch64] Add test case to show missed opportunity to remove a shift before tbnz when the shift has been zero extended from i32 to i64. NFC
This pattern showed up in D60358 and it was suggested I had a test and fix that separately.

llvm-svn: 358030
2019-04-09 19:23:37 +00:00
Craig Topper 8e2871cd2c [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match gas. Use {evex} to improve the one our 32-bit AVX512 tests.
These can be used to force the encoding used for instructions.

{vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet.

{vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form.

{evex} will force the instruction to use the EVEX version or fail if there is no EVEX version.

Differential Revision: https://reviews.llvm.org/D59266

llvm-svn: 358029
2019-04-09 18:45:15 +00:00
Craig Topper 61e77b11d1 [DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO by negating the immediate.
This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate.

Differential Revision: https://reviews.llvm.org/D60020

llvm-svn: 358027
2019-04-09 18:33:56 +00:00
Nikita Popov 2f5e9de8d1 Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)."
This reverts commit 1383a91689.

sdiv-canonicalize.ll fails after this revision. The fold needs to be
moved outside the branch handling constant operands. However when this
is done there are further test changes, so I'm reverting this in the
meantime.

llvm-svn: 358026
2019-04-09 18:32:38 +00:00
Nikita Popov eda3b9326e [InstCombine] Restructure OptimizeOverflowCheck; NFC
Change the code to always handle the unsigned+signed cases together
with the same basic structure for add/sub/mul. The simple folds are
always handled first and then the ValueTracking overflow checks are
used.

llvm-svn: 358025
2019-04-09 18:32:28 +00:00
Eric Christopher 202c9b99e0 Remove the unit at a time option
Removes the code from opt and the pass manager builder.
The code was unused - even by the C library code that was supposed to set
it and had been removed previously.

llvm-svn: 358024
2019-04-09 18:29:22 +00:00
Zachary Turner 6bafd5b3f7 [PDB Docs] Clarifications and fixes for DBI Stream.
llvm-svn: 358022
2019-04-09 17:38:34 +00:00
Kristina Brooks a1c44941f3 Update modulemaps for Analysis/VecFuncs.def.
Avoid a warning while building modular LLVM due to a new
textual header missing in the modulemap:

TargetLibraryInfo.cpp:1485:6: warning: missing submodule
  'LLVM_Analysis.VecFuncs' [-Wincomplete-umbrella]

Added VecFuncs.def as a textual header in LLVM_Analysis.

llvm-svn: 358021
2019-04-09 17:05:36 +00:00
Nikita Popov 4b2323d1a3 [ValueTracking] Use computeConstantRange() for signed sub overflow determination
This is the same change as D60420 but for signed sub rather than
signed add: Range information is intersected into the known bits
result, allows to detect more no/always overflow conditions.

Differential Revision: https://reviews.llvm.org/D60469

llvm-svn: 358020
2019-04-09 17:01:49 +00:00
Simon Pilgrim d7cc0ec581 [TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR support
llvm-svn: 358019
2019-04-09 16:52:21 +00:00
Chen Zheng 1383a91689 [InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).
Differential Revision: https://reviews.llvm.org/D60395

llvm-svn: 358017
2019-04-09 16:34:31 +00:00
Stanislav Mekhanoshin 913ba8eeb4 Revert LIS handling in MachineDCE
One of out of tree targets has regressed with this patch. Reverting
it for now and let liveness to be fully reconstructed in case pass
was used after the LIS is created to resolve the regression.

Differential Revision: https://reviews.llvm.org/D60466

llvm-svn: 358015
2019-04-09 16:13:53 +00:00
Nikita Popov 10edd2b79d [ValueTracking] Use computeConstantRange() in signed add overflow determination
This is D59386 for the signed add case. The computeConstantRange()
result is now intersected into the existing known bits information,
allowing to detect additional no-overflow/always-overflow conditions
(though the latter isn't used yet).

This (finally...) covers the motivating case from D59071.

Differential Revision: https://reviews.llvm.org/D60420

llvm-svn: 358014
2019-04-09 16:12:59 +00:00
Sanjay Patel 49d9d17a77 [InstCombine] prevent possible miscompile with sdiv+negate of vector op
Similar to:
rL358005

Forego folding arbitrary vector constants to fix a possible miscompile bug.
We can enhance the transform if we do want to handle the more complicated
vector case.

llvm-svn: 358013
2019-04-09 15:13:03 +00:00
Fangrui Song 9b22c469ca [DWARF] DWARFDebugLine: replace Sequence::orderByLowPC with orderByHighPC
In a sorted list of non-overlapping [LowPC,HighPC) ranges, locating an address with
upper_bound on HighPC is simpler than lower_bound on LowPC.

llvm-svn: 358012
2019-04-09 15:08:32 +00:00
Sanjay Patel d5173f5acf [InstCombine] add tests for sdiv with negated dividend and constant divisor; NFC
llvm-svn: 358010
2019-04-09 14:48:44 +00:00
Sanjay Patel 7563b65ad4 [InstCombine] add tests for sdiv-by-int-min; NFC
llvm-svn: 358008
2019-04-09 14:27:07 +00:00
Sanjay Patel d469954d61 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 358007
2019-04-09 14:27:03 +00:00
Sanjay Patel f62dcea7ed [InstCombine] prevent possible miscompile with negate+sdiv of vector op
// 0 - (X sdiv C)  -> (X sdiv -C)  provided the negation doesn't overflow.

This fold has been around for many years and nobody noticed the potential
vector miscompile from overflow until recently...
So it seems unlikely that there's much demand for a vector sdiv optimization
on arbitrary vector constants, so just limit the matching to splat constants
to avoid the possible bug.

Differential Revision: https://reviews.llvm.org/D60426

llvm-svn: 358005
2019-04-09 14:09:06 +00:00
Nico Weber af5834596b gn build: Fix Windows builds after r357797
llvm-svn: 358004
2019-04-09 14:02:02 +00:00
Sanjay Patel a230bb5fc0 [InstCombine] add tests/comments for negate+sdiv; NFC
llvm-svn: 358003
2019-04-09 13:41:29 +00:00
Nemanja Ivanovic 820b90318f NFC: Refactor library-specific mappings of scalar maths functions to their vector counterparts
This patch factors out mappings of scalar maths functions to their vector
counterparts from TargetLibraryInfo.cpp to a separate VecFuncs.def file. Such
mappings are currently available for Accelerate framework, and SVML library.

This is in support of the follow-up: https://reviews.llvm.org/D59881

Patch by pjeeva01

Differential revision: https://reviews.llvm.org/D60211

llvm-svn: 358001
2019-04-09 13:21:11 +00:00
Chen Zheng 11cf397292 [InstCombine] add more testcases for canonicalize (-X s/ Y) to -(X s/ Y).
llvm-svn: 358000
2019-04-09 12:47:29 +00:00
Simon Pilgrim 55f79ef9fe [TargetLowering] SimplifyDemandedBits - Remove GetDemandedSrcMask lambda. NFCI.
An older version of this could return false but now that this always succeeds we can just inline and simplify it.

llvm-svn: 357999
2019-04-09 12:29:26 +00:00
Anton Afanasyev 03c3e0d3bf Improve hashing for time profiler
Summary:
Use optimized hashing while writing time trace by join two hashes to one.
Used for -ftime-trace option.

Reviewers: rnk, takuto.ikuta

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60404

llvm-svn: 357998
2019-04-09 12:18:44 +00:00
Simon Pilgrim 345eacd555 [TargetLowering] SimplifyDemandedBits - call SimplifyDemandedBits in bitcast handling
When bitcasting from a source op to a larger bitwidth op, split the demanded bits and OR them on top of one another and demand those merged bits in the SimplifyDemandedBits call on the source op.

llvm-svn: 357992
2019-04-09 10:27:59 +00:00
Simon Pilgrim 563f35ab2d [llvm-rtdyld] Fix missing include on MSVC builds.
llvm-svn: 357990
2019-04-09 10:15:10 +00:00
David Stenberg 2028ae975c [DebugInfo] Pass all values in DebugLocEntry's constructor, NFC
Summary:
With MergeValues() removed, amend DebugLocEntry's constructor so that it
takes multiple values rather than a single, and keep non-fragment values
in OpenRanges, as this allows some cleanup of the code in
buildLocationList().

Reviewers: aprantl, dblaikie, loladiro

Reviewed By: aprantl

Subscribers: hiraditya, llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59303

llvm-svn: 357988
2019-04-09 10:08:26 +00:00
Simon Pilgrim a30ba452c6 Fix Wdocumentation warning. NFCI.
llvm-svn: 357987
2019-04-09 09:38:25 +00:00
Hiroshi Inoue 30d3c58b81 [PowerPC] fix trivial typos in comment, NFC
llvm-svn: 357981
2019-04-09 08:40:02 +00:00
Martin Storsjo e16434a049 [CMake] Fix accidentally swapped input/output parameters of string(REPLACE) for mingw
llvm-svn: 357979
2019-04-09 08:31:25 +00:00
Justin Bogner c60d09597c [CMake] Move configuration of LLVM_CXX_STD to HandleLLVMOptions.cmake
Standalone builds of projects other than llvm itself (lldb, libcxx,
etc) include HandleLLVMOptions but not the top level llvm CMakeLists,
so we need to set this variable here to ensure that it always has a
value.

This should fix the build issues some folks have been seeing.

llvm-svn: 357976
2019-04-09 08:14:32 +00:00
David Stenberg 93b497a61d [DebugInfo] Remove redundant DebugLocEntry::MergeValues() function, NFC
Summary:
The MergeValues() function would try to merge two entries if they shared
the same beginning label. Having the same beginning label means that the
former entry's range would be empty; however, after D55919 we no longer
create entries for empty ranges, so we can no longer land in a situation
where that check in MergeValues would succeed. Instead, the "merging" is
done by keeping the live values from the preceding empty ranges in
OpenRanges, and adding them to the first non-empty range.

Reviewers: aprantl, dblaikie, loladiro

Reviewed By: aprantl

Subscribers: llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D59301

llvm-svn: 357974
2019-04-09 07:46:09 +00:00
Craig Topper e043dadcad [X86] Remove check on isAsmParserOnly from EVEX2VEX tablegenerator. NFCI
There are no instructions VEX or EVEX instructions that set this field.

llvm-svn: 357973
2019-04-09 07:40:19 +00:00
Craig Topper 53ee783c6e [X86] Have EVEX2VEX tablegenerator use HasVEX_L and HasEVEX_L2 fields instead of the composite EVEX_LL field. Remove the EVEX_LL field. NFCI
The composite existed to simplify some other tablegen code and not really in an
important way. Remove the combined field and just calculate the vector size
using two ifs.

llvm-svn: 357972
2019-04-09 07:40:14 +00:00
Craig Topper f19f991b7f [X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX.
The instruction's document this as W0 for the VEX encoding. But there's a
footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX
encoding description says the VEX.W bit is ignored for instructions that are
equivalent to a legacy SSE instruction that uses REX.W to select a GPR which
would apply here.

By making this match EVEX we can remove a special case of allowing EVEX2VEX to
turn an EVEX.WIG instruction into VEX.W0.

llvm-svn: 357971
2019-04-09 07:40:10 +00:00
Craig Topper 2f9c1732b8 [X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields with clear meanings.
llvm-svn: 357970
2019-04-09 07:40:06 +00:00
Nikita Popov 6e9157d588 [ValueTracking] Use ConstantRange methods; NFC
Switch part of the computeOverflowForSignedAdd() implementation to
use Range.isAllNegative() rather than KnownBits.isNegative() and
similar. They do the same thing, but using the ConstantRange methods
allows dropping the KnownBits variables more easily in D60420.

llvm-svn: 357969
2019-04-09 07:13:09 +00:00
Nikita Popov 7bd7878d22 [ValueTracking] Explicitly specify intersection type; NFC
Preparation for D60420.

llvm-svn: 357968
2019-04-09 07:13:03 +00:00
Eric Christopher 88c70ec68e Include omitted word in comment.
llvm-svn: 357967
2019-04-09 06:35:47 +00:00
Fangrui Song 3f2096833a [llvm-objdump] Migrate some functions from std::error_code to Error
llvm-svn: 357965
2019-04-09 05:41:24 +00:00
Tom Stellard 206b9927f8 AMDGPU/GlobalISel: Implement call lowering for shaders returning values
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, llvm-commits

Differential Revision: https://reviews.llvm.org/D57166

llvm-svn: 357964
2019-04-09 02:26:03 +00:00
Chen Zheng 19ce6719bc [PowerPC] initialize SchedModel according to platform.
Differential Revision: https://reviews.llvm.org/D60177

llvm-svn: 357962
2019-04-09 01:25:25 +00:00
Peter Collingbourne df57979ba7 hwasan: Enable -hwasan-allow-ifunc by default.
It's been on in Android for a while without causing problems, so it's time
to make it the default and remove the flag.

Differential Revision: https://reviews.llvm.org/D60355

llvm-svn: 357960
2019-04-09 00:25:59 +00:00
Craig Topper 6c11a31bce [X86] Derive ssmem and sdmem from X86MemOperand. NFCI
This changes the operand type from v4f32/v2f64 to iPTR which seems more correct. But that doesn't seem to do anything other than change the comments in X86GenDAGISel.inc. Probably because we use a ComplexPattern to do the matching so there's no autogenerated code to change.

llvm-svn: 357959
2019-04-09 00:24:17 +00:00
Sanjay Patel 74ccef1f4f [InstCombine] add tests for negate+sdiv; NFC
PR41425:
https://bugs.llvm.org/show_bug.cgi?id=41425

llvm-svn: 357953
2019-04-08 22:55:10 +00:00
Lang Hames d250238abd [RuntimeDyld] Fix an ambiguous make_unique call.
llvm-svn: 357950
2019-04-08 22:19:05 +00:00
Lang Hames 941f247d30 [RuntimeDyld] Decouple RuntimeDyldChecker from RuntimeDyld.
This will allow RuntimeDyldChecker (and rtdyld-check tests) to test a new JIT
linker: JITLink (https://reviews.llvm.org/D58704).

llvm-svn: 357947
2019-04-08 21:50:48 +00:00
Shoaib Meenai 867131a96c [BinaryFormat] Update Mach-O ARM64E CPU subtype and dumping
The new value is taken from <mach/machine.h> in the MacOSX10.14 SDK from
Xcode 10.1. Update llvm-objdump and llvm-readobj accordingly.

Differential Revision: https://reviews.llvm.org/D58636

llvm-svn: 357945
2019-04-08 21:37:08 +00:00
Sanjay Patel 773e04c883 [InstCombine] peek through fdiv to find a squared sqrt
A more general canonicalization between fdiv and fmul would not
handle this case because that would have to be limited by uses
to prevent 2 values from becoming 3 values:
(x/y) * (x/y) --> (x*x) / (y*y)

(But we probably should still have that limited -- but more general --
canonicalization independently of this change.)

llvm-svn: 357943
2019-04-08 21:23:50 +00:00
Simon Pilgrim 9f74df7d5b [TargetLowering] SimplifyDemandedBits - use DemandedElts in bitcast handling
Be more selective in the SimplifyDemandedBits -> SimplifyDemandedVectorElts bitcast call based on the demanded elts.

llvm-svn: 357942
2019-04-08 20:59:38 +00:00
Sanjay Patel bf1417d7e4 [InstCombine] add extra-use tests for fmul+sqrt; NFC
llvm-svn: 357939
2019-04-08 20:37:34 +00:00
Nikita Popov 15abd74de7 [InstCombine] Add more tests for signed saturing math overflow; NFC
Overflow conditions for sadd.sat and ssub.sat which can be determined
based on constant ranges, but not necessarily known bits.

llvm-svn: 357938
2019-04-08 20:02:47 +00:00
Nico Weber 63b97d2a67 llvm-undname: Fix more crashes and asserts on invalid inputs
For functions whose callers don't check that enough input is present,
add checks at the start of the function that enough input is there and
set Error otherwise.

For functions that return AST objects, return nullptr instead of
incomplete AST objects with nullptr fields if an error occurred during
the function.

Introduce a new function demangleDeclarator() for the sequence
demangleFullyQualifiedSymbolName(); demangleEncodedSymbol() and
use it in the two places that had this sequence. Let this new function
check that ConversionOperatorIdentifiers have a valid TargetType.

Some of the bad inputs found by oss-fuzz, others by inspection.

Differential Revision: https://reviews.llvm.org/D60354

llvm-svn: 357936
2019-04-08 19:46:53 +00:00
Craig Topper 3a4c2192a4 [X86] Fix a couple lowering functions that called ReplaceAllUsesOfValueWith for the newly created code and then return SDValue(). Use MERGE_VALUES instead.
Returning SDValue() makes the caller think custom lowering was unsuccessful and then it will fall back to trying to expand the original node. This expanded code will end up with no users and end up being pruned later. But it was useless unnecessary work to create it.

Instead return a MERGE_VALUES with all the results so the caller knows something changed. The caller can handle the replacements.

For one of the cases I had to use UNDEF has a dummy value for a result we know is unused. This should get pruned later.

llvm-svn: 357935
2019-04-08 19:44:07 +00:00
Adrian Prantl 6ed5706a2b Add LLVM IR debug info support for Fortran COMMON blocks
COMMON blocks are a feature of Fortran that has no direct analog in C languages, but they are similar to data sections in assembly language programming. A COMMON block is a named area of memory that holds a collection of variables. Fortran subprograms may map the COMMON block memory area to their own, possibly distinct, non-empty list of variables. A Fortran COMMON block might look like the following example.

    COMMON /ALPHA/ I, J

    For this construct, the compiler generates a new scope-like DI construct (!DICommonBlock) into which variables (see I, J above) can be placed. As the common block implies a range of storage with global lifetime, the !DICommonBlock refers to a !DIGlobalVariable. The Fortran variable that comprise the COMMON block are also linked via metadata to offsets within the global variable that stands for the entire common block.

    @alpha_ = common global %alphabytes_ zeroinitializer, align 64, !dbg !27, !dbg !30, !dbg !33
    !14 = distinct !DISubprogram(…)
    !20 = distinct !DICommonBlock(scope: !14, declaration: !25, name: "alpha")
    !25 = distinct !DIGlobalVariable(scope: !20, name: "common alpha", type: !24)
    !27 = !DIGlobalVariableExpression(var: !25, expr: !DIExpression())
    !29 = distinct !DIGlobalVariable(scope: !20, name: "i", file: !3, type: !28)
    !30 = !DIGlobalVariableExpression(var: !29, expr: !DIExpression())
    !31 = distinct !DIGlobalVariable(scope: !20, name: "j", file: !3, type: !28)
    !32 = !DIExpression(DW_OP_plus_uconst, 4)
    !33 = !DIGlobalVariableExpression(var: !31, expr: !32)

    The DWARF generated for this is as follows.

    DW_TAG_common_block:
    DW_AT_name: alpha
    DW_AT_location: @alpha_+0
    DW_TAG_variable:
    DW_AT_name: common alpha
    DW_AT_type: array of 8 bytes
    DW_AT_location: @alpha_+0
    DW_TAG_variable:
    DW_AT_name: i
    DW_AT_type: integer*4
    DW_AT_location: @Alpha+0
    DW_TAG_variable:
    DW_AT_name: j
    DW_AT_type: integer*4
    DW_AT_location: @Alpha+4

Patch by Eric Schweitz!

Differential Revision: https://reviews.llvm.org/D54327

llvm-svn: 357934
2019-04-08 19:13:55 +00:00
Steven Wu f41e70d6eb Revert [ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols
This reverts r357931 (git commit 8b70a5c11e)

llvm-svn: 357932
2019-04-08 18:53:21 +00:00
Steven Wu 8b70a5c11e [ThinLTO] Fix ThinLTOCodegenerator to export llvm.used symbols
Summary:
ThinLTOCodeGenerator currently does not preserve llvm.used symbols and
it can internalize them. In order to pass the necessary information to the
legacy ThinLTOCodeGenerator, the input to the code generator is
rewritten to be based on lto::InputFile.

This fixes: PR41236
rdar://problem/49293439

Reviewers: tejohnson, pcc, dexonsmith

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, eraman, hiraditya, jkorous, dang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60226

llvm-svn: 357931
2019-04-08 18:24:10 +00:00
Brian M. Rzycki 887865c1ad [JumpThreading] Fix incorrect fold conditional after indirectbr/callbr
Fixes bug 40992: https://bugs.llvm.org/show_bug.cgi?id=40992

There is potential for miscompiled code emitted from JumpThreading when
analyzing a block with one or more indirectbr or callbr predecessors. The
ProcessThreadableEdges() function incorrectly folds conditional branches
into an unconditional branch.

This patch prevents incorrect branch folding without fully pessimizing
other potential threading opportunities through the same basic block.

This IR shape was manually fed in via opt and is unclear if clang and the
full pass pipeline will ever emit similar code shapes.

Thanks to Matthias Liedtke for the bug report and simplified IR example.

Differential Revision: https://reviews.llvm.org/D60284

llvm-svn: 357930
2019-04-08 18:20:35 +00:00
Fangrui Song f67de6c940 [llvm-objdump] Migrate relocation handling functions from error_code to Error
llvm-svn: 357920
2019-04-08 16:24:08 +00:00
Andrea Di Biagio f6a60f1f80 [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI
It makes more sense to print out the number of micro opcodes that are issued
every cycle rather than the number of instructions issued per cycle.
This behavior is also consistent with the dispatch-stats: numbers from the two
views can now be easily compared.

llvm-svn: 357919
2019-04-08 16:05:54 +00:00
Simon Pilgrim 86844a865e [X86][AVX] Add PR34380 shuffle test cases
llvm-svn: 357914
2019-04-08 14:05:42 +00:00
Sanjay Patel 50c3b290ed [x86] make 8-bit shl undesirable
I was looking at a potential DAGCombiner fix for 1 of the regressions in D60278, and it caused severe regression test pain because x86 TLI lies about the desirability of 8-bit shift ops.

We've hinted at making all 8-bit ops undesirable for the reason in the code comment:

// TODO: Almost no 8-bit ops are desirable because they have no actual
//       size/speed advantages vs. 32-bit ops, but they do have a major
//       potential disadvantage by causing partial register stalls.

...but that leads to massive diffs and exposes all kinds of optimization holes itself.

Differential Revision: https://reviews.llvm.org/D60286

llvm-svn: 357912
2019-04-08 13:58:50 +00:00
Eugene Leviant 7671a1daa7 Use llvm::crc32 instead of crc32. NFC
llvm-svn: 357911
2019-04-08 13:40:58 +00:00
Sanjay Patel b33938df7a [InstCombine] remove overzealous assert for shuffles (PR41419)
As the TODO indicates, instsimplify could be improved.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=41419

llvm-svn: 357910
2019-04-08 13:28:29 +00:00
Simon Pilgrim b4f1bfa659 [InstCombine][X86] Expand MOVMSK to generic IR (PR39927)
First step towards removing the MOVMSK intrinsics completely - this patch expands MOVMSK to the pattern:

e.g. PMOVMSKB(v16i8 x):
%cmp = icmp slt <16 x i8> %x, zeroinitializer
%int = bitcast <16 x i8> %cmp to i16
%res = zext i16 %int to i32

Which is correctly handled by ISel and FastIsel (give or take an annoying movzx move....): https://godbolt.org/z/rkrSFW

Differential Revision: https://reviews.llvm.org/D60256

llvm-svn: 357909
2019-04-08 13:17:51 +00:00
Nico Weber b743b45ebf gn build: Merge r357905
llvm-svn: 357907
2019-04-08 12:43:46 +00:00
Nico Weber c83ef47c63 gn-build: Re-run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
llvm-svn: 357906
2019-04-08 12:42:37 +00:00
Eugene Leviant 18873b22be Attempt to recommit r357901
llvm-svn: 357905
2019-04-08 12:31:12 +00:00
Chen Zheng 923c7c9daa [InstCombine] sdiv exact flag fixup.
Differential Revision: https://reviews.llvm.org/D60396

llvm-svn: 357904
2019-04-08 12:08:03 +00:00
Xing GUO 0df95d2d31 [llvm-readobj] Use `reinterpret_cast` instead of C-style casting. NFC.
llvm-svn: 357903
2019-04-08 11:48:36 +00:00
Eugene Leviant 03d28a4490 Reverting r357901 as fails to build on some of the buildbots
llvm-svn: 357902
2019-04-08 11:37:20 +00:00
Eugene Leviant ad69bd6870 [Support] Add zlib independent CRC32
Differential revision: https://reviews.llvm.org/D59816

llvm-svn: 357901
2019-04-08 11:25:48 +00:00
Roman Lebedev eb1a156d7f [llvm-exegesis] benchmarkMain(): less cryptic error if built w/o libpfm
Wanted to check if inablility to measure latency of CMOV32rm
is a regression from D60041 / D60138, but unable to do that
because the llvm-exegesis-{8,9} from debian sid fails
with that cryptic, unhelpful error.

I suspect this will be a better error.

llvm-svn: 357900
2019-04-08 10:50:31 +00:00
Justin Bogner 25de7691a0 [CMake] Replace LLVM_ENABLE_CXX1Y and friends with LLVM_CXX_STD
Simplify building with particular C++ standards by replacing the
specific "enable standard X" flags with a flag that allows specifying
the standard you want directly.

We preserve compatibility with the existing flags so that anyone with
those flags in existing caches won't break mysteriously.

Differential Revision: https://reviews.llvm.org/D60399

llvm-svn: 357899
2019-04-08 10:19:17 +00:00
Roman Lebedev a82235843b [llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes
Reviewers: courbet, gchatelet

Reviewed By: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60066

llvm-svn: 357898
2019-04-08 10:11:00 +00:00
Pavel Labath aaff480c68 Object/Minidump: Add support for reading the ModuleList stream
Summary:
The ModuleList stream consists of an integer giving the number of
entries in the list, followed by the list itself. Each entry in the list
describes a module (dynamically loaded objects which were loaded in the
process when it crashed (or when the minidump was generated).

The code for reading the list is relatively straight-forward, with a
single gotcha. Some minidump writers are emitting padding after the
"count" field in order to align the subsequent list on 8 byte boundary
(this depends on how their ModuleList type was defined and the native
alignment of various types on their platform). Fortunately, the minidump
format contains enough redundancy (in the form of the stream length
field in the stream directory), which allows us to detect this situation
and correct it.

This patch just adds the ability to parse the stream. Code for
conversion to/from yaml will come in a follow-up patch.

Reviewers: zturner, amccarth, jhenderson, clayborg

Subscribers: jdoerfert, markmentovai, lldb-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60121

llvm-svn: 357897
2019-04-08 09:57:29 +00:00
Chen Zheng edf91ed855 [InstCombine] add more testcases for sdiv exact flag fixup.
llvm-svn: 357894
2019-04-08 09:19:42 +00:00
Craig Topper 6a6da233b9 [X86] Make LowerOperationWrapper more robust. Remove now unnecessary ReplaceAllUsesWith from LowerMSCATTER.
Previously LowerOperationWrapper took the number of results from the original
node and counted that many results from the new node. This was intended to drop
chain operands from FP_TO_SINT lowering that uses X87 with memory operations to
stack temporaries. The final load had an extra chain output that needs to be
ignored.

Unfortunately, it didn't work with scatter which has 2 result operands, the
mask output which is discarded and a chain output. The chain output is the one
that is needed but it comes second and it would be dropped by the previous
logic here. To workaround this we were doing a ReplaceAllUses in the lowering
code so that the generic legalization code wouldn't see any uses to replace
since it had been given the wrong result/type.

After this change we take the LowerOperation result directly if the original
node has one result. This allows us to directly return the chain from scatter
or the load data from the FP_TO_SINT case. When the original node has multiple
results we'll ensure the returned node has the same number and copy them over.
For cases where the original node has multiple results and the new code for some
reason has even more results, MERGE_VALUES can be used to pass only the needed
results.

llvm-svn: 357887
2019-04-08 07:39:17 +00:00
Fangrui Song dc1f4a6764 [ConstantRange] Delete redundnt {z,s}extOrSelf for multiplication
These calls are redundant because the quotients have the same BitWidth
as MinValue/MaxValue.

llvm-svn: 357886
2019-04-08 07:29:24 +00:00
Chen Zheng d3b1d74624 [InstCombine] add testcases for sdiv exact flag fixing - NFC.
llvm-svn: 357884
2019-04-08 05:49:15 +00:00
Chen Zheng c84107612a [InstCombine]add testcase for sdiv canonicalizetion - NFC
llvm-svn: 357883
2019-04-08 03:07:32 +00:00
Craig Topper afb6b42691 [X86] Split floating point tests out of atomic-mi.ll into atomic-fp.ll. Add avx and avx512f command lines. NFC
llvm-svn: 357882
2019-04-08 01:54:27 +00:00
Craig Topper 8aeefe3149 [X86] Add avx and avx512f command lines to atomic-non-integer.ll. NFC
llvm-svn: 357881
2019-04-08 01:54:24 +00:00
Fangrui Song 996b90932a [llvm-objdump] Fix MC/ARM/arm-macho-calls.s
llvm-svn: 357880
2019-04-08 01:22:38 +00:00
Nikita Popov f38b46ffca [ConstantRange] Add signed/unsigned unionWith()
This extends D59959 to unionWith(), allowing to specify that a
non-wrapping unsigned/signed range is preferred. This is somewhat
less useful than the intersect case, because union operations are
rarer. An example use would the the phi union computed in SCEV.

The implementation is mostly a straightforward use of getPreferredRange(),
but I also had to adjust some <=/< checks to make sure that no ranges with
lower==upper get constructed before they're passed to getPreferredRange(),
as these have additional constraints.

Differential Revision: https://reviews.llvm.org/D60377

llvm-svn: 357876
2019-04-07 20:20:24 +00:00
Craig Topper 424417da79 [X86] Use (SUBREG_TO_REG (MOV32rm)) for extloadi64i8/extloadi64i16 when the load is 4 byte aligned or better and not volatile.
Summary:
Previously we would use MOVZXrm8/MOVZXrm16, but those are longer encodings.

This is similar to what we do in the loadi32 predicate.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60341

llvm-svn: 357875
2019-04-07 19:19:44 +00:00
Nikita Popov c664c2a5ec [ConstantRangeTest] Generalize intersection testing code; NFC
Extract the exhaustive intersection tests into a separate function,
so that it may be reused for unions as well.

llvm-svn: 357874
2019-04-07 18:55:45 +00:00
Nikita Popov 4246106aba [ConstantRange] Add unsigned and signed intersection types
The intersection of two ConstantRanges may consist of two disjoint
ranges. As we can only return one range as the result, we need to
return one of the two possible ranges that cover both. Currently the
result is picked based on set size. However, this is not always
optimal: If we're in an unsigned context, we'd prefer to get a large
unsigned range over a small signed range -- the latter effectively
becomes a full set in the unsigned domain.

This revision adds a PreferredRangeType, which can be either Smallest,
Unsigned or Signed. Smallest is the current behavior and Unsigned and
Signed are new variants that prefer not to wrap the unsigned/signed
domain. The new type isn't used anywhere yet (but SCEV will be a good
first user, see D60035).

I've also added some comments to illustrate the various cases in
intersectWith(), which should hopefully make it more obvious what is
going on.

Differential Revision: https://reviews.llvm.org/D59959

llvm-svn: 357873
2019-04-07 18:44:36 +00:00
Robert Widmann a51883cfab [LLVM-C] Allow Access to the Type of a Binary
Summary:  Add an accessor for the type of a binary file.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: hiraditya, aheejin, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60366

llvm-svn: 357872
2019-04-07 18:18:42 +00:00
Nikita Popov bad648a23e [ConstantRange] Add isAllNegative() and isAllNonNegative() methods
Add isAllNegative() and isAllNonNegative() methods to ConstantRange,
which determine whether all values in the constant range are
negative/non-negative.

This is useful for replacing KnownBits isNegative() and isNonNegative()
calls when changing code to use constant ranges.

Differential Revision: https://reviews.llvm.org/D60264

llvm-svn: 357871
2019-04-07 17:52:40 +00:00
Nikita Popov 3db93ac5d6 Reapply [ValueTracking] Support min/max selects in computeConstantRange()
Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold comparisons of a min/max against a constant
in InstSimplify. This fixes an infinite InstCombine loop, with the
test case taken from D59378.

Relative to the previous iteration, this contains some adjustments for
AMDGPU med3 tests: The AMDGPU target runs InstSimplify prior to codegen,
which ends up constant folding some existing med3 tests after this
change. To preserve these tests a hidden -amdgpu-scalar-ir-passes option
is added, which allows disabling scalar IR passes (that use InstSimplify)
for testing purposes.

Differential Revision: https://reviews.llvm.org/D59506

llvm-svn: 357870
2019-04-07 17:22:16 +00:00
Fangrui Song 32087b65e7 [llvm-objdump] Split disassembleObject and simplify --{start,stop}-address handling
The main disassembly loop is hard to read due to special handling of ARM
ELF data & ELF data. Split off the logic into two functions
dumpARMELFData and dumpELFData. Hoist some checks outside of the loop.

--start-address --stop-address have redundant checks and minor off-by-1
issues. Fix them.

llvm-svn: 357869
2019-04-07 16:33:24 +00:00
Chris Lattner 32a8e742e2 last changes for now
llvm-svn: 357868
2019-04-07 14:34:24 +00:00
Chris Lattner 0fa6c15873 various improvements in wording, also unbreak the bot
llvm-svn: 357867
2019-04-07 14:23:11 +00:00
Fangrui Song c4c8bcaeec [DWARF] DWARFDebugLine: delete unused parameter `Offset`
llvm-svn: 357866
2019-04-07 13:56:14 +00:00
Chris Lattner 13d3505a86 make a bunch of cleanups in wording and tone
llvm-svn: 357865
2019-04-07 13:42:29 +00:00
Simon Pilgrim 6d7fdd9ab7 [CostModel][X86] Masked load legalization requires an binary-shuffle not a select (PR39812)
Expansion/truncation is better described by SK_PermuteTwoSrc than SK_Select

llvm-svn: 357864
2019-04-07 13:26:09 +00:00
Chris Lattner 2243a165b1 remove some unhelpful language from the tutorial
llvm-svn: 357863
2019-04-07 13:17:16 +00:00
Chris Lattner d80f118e52 Copy the C++ kaleidoscope tutorial into a subdirectory and clean up various things, aligning with the direction of the WiCT workshop, and Meike Baumgärtner's view of how this should work. The old version of the documentation is unmodified, this is an experiment.
llvm-svn: 357862
2019-04-07 13:14:23 +00:00
Simon Pilgrim 561ba38623 [DAG] Pull out ComputeNumSignBits call to make debugging easier. NFCI.
llvm-svn: 357861
2019-04-07 11:49:33 +00:00
Simon Pilgrim 07adb6abda [X86][SSE] SimplifyDemandedBitsForTargetNode - Add initial PACKSS support
In the case where we only want the sign bit (e.g. when using PACKSS truncation of comparison results for MOVMSK) then we can just demand the sign bit of the source operands.

This makes use of the fact that PACKSS saturates out of range values to the min/max int values - so the sign bit is always preserved.

Differential Revision: https://reviews.llvm.org/D60333

llvm-svn: 357859
2019-04-07 10:40:01 +00:00
Fangrui Song 47a7662e29 [llvm-objdump] Fix split of source lines; don't ltrim source lines
If the file does not end with a newline, it may be dropped. Fix the
splitting algorithm.

Also delete an unnecessary SourceCache lookup.

llvm-svn: 357858
2019-04-07 10:16:46 +00:00
Fangrui Song af7314b317 [llvm-objdump] Simplify some ELF typename: ELFFile<ELFT>::Elf_xxx -> ELFT::xxx
llvm-svn: 357857
2019-04-07 08:29:04 +00:00
Fangrui Song 454a7bb372 .
llvm-svn: 357856
2019-04-07 08:28:56 +00:00
Fangrui Song e7834bd159 [llvm-objdump] Simplify Expected<T> handling with unwrapOrError
llvm-svn: 357855
2019-04-07 08:19:55 +00:00
Marcello Maggioni 30eb575811 [ConstantRange] Shl considers full-set shifting to last bit position.
if we do SHL of two 16-bit ranges like [0, 30000) with [1,2) we get
"full-set" instead of what I would have expected [0, 60000) which is
still in the 16-bit unsigned range.

This patch changes the SHL algorithm to allow getting a usable range
even in this case.

Differential Revision: https://reviews.llvm.org/D57983

llvm-svn: 357854
2019-04-07 06:12:44 +00:00
Fangrui Song 545ed223a6 [llvm-objdump] Simplify disassembleObject
* Use std::binary_search to replace some std::lower_bound
* Use llvm::upper_bound to replace some std::upper_bound
* Use format_hex and support::endian::read{16,32}

llvm-svn: 357853
2019-04-07 05:32:16 +00:00
Fangrui Song 6a0746a92f Change some StringRef::data() reinterpret_cast to bytes_begin() or arrayRefFromStringRef()
llvm-svn: 357852
2019-04-07 03:58:42 +00:00
Petr Hosek bcb29cb748 [gn] Support for per-target runtime directory layout
This change also introduces the clang_enable_per_target_runtime_dir
to enable the use of per-target runtime directory layout which is the
equivalent of LLVM_ENABLE_PER_TARGET_RUNTIME_DIR CMake option.

Differential Revision: https://reviews.llvm.org/D60332

llvm-svn: 357850
2019-04-06 23:05:56 +00:00
Nick Lewycky 383419f707 [NFC] Fix typo in comment.
llvm-svn: 357849
2019-04-06 22:05:24 +00:00
Craig Topper 399102b464 [X86] When converting (x << C1) AND C2 to (x AND (C2>>C1)) << C1 during isel, try using andl over andq by favoring 32-bit unsigned immediates.
llvm-svn: 357848
2019-04-06 19:00:11 +00:00
Simon Pilgrim d0a53d4914 [X86] combineBitcastvxi1 - provide dst VT and src SDValue directly. NFCI.
Prep work to make it easier to reuse the BITCAST->MOVSMK combine in other cases.

llvm-svn: 357847
2019-04-06 18:54:17 +00:00
Craig Topper f9b9f8d2e4 [X86] Use a signed mask in foldMaskedShiftToScaledMask to enable a shorter immediate encoding.
This function reorders AND and SHL to enable the SHL to fold into an LEA. The
upper bits of the AND will be shifted out by the SHL so it doesn't matter what
mask value we use for these bits. By using sign bits from the original mask in
these upper bits we might enable a shorter immediate encoding to be used.

llvm-svn: 357846
2019-04-06 18:00:50 +00:00
Craig Topper 82448bc09e [X86] Add test cases to show missed opportunities to use a sign extended 8 or 32 bit immediate AND when reversing SHL+AND to form an LEA.
When we shift the AND mask over we should shift in sign bits instead of zero bits. The scale in the LEA will shift these bits out so it doesn't matter whether we mask the bits off or not. Using sign bits will potentially allow a sign extended immediate to be used.

Also add some other test cases for cases that are currently optimal.

llvm-svn: 357845
2019-04-06 18:00:45 +00:00
Craig Topper 9d7379c250 [X86] Autogenerate complete checks. NFC
llvm-svn: 357844
2019-04-06 18:00:41 +00:00
Simon Pilgrim af1cbdd3ba Fix spelling mistake. NFCI.
llvm-svn: 357843
2019-04-06 15:38:34 +00:00
Simon Pilgrim ec28615f7f [X86] Add AVX-target expandload and compressstore tests
llvm-svn: 357842
2019-04-06 14:40:52 +00:00
Roman Lebedev 404bdb1c9e [llvm-exegesis][X86] Handle CMOVcc/SETcc OPERAND_COND_CODE OperandType
Summary:
D60041 / D60138 refactoring changed how CMOV/SETcc opcodes
are handled. concode is now an immediate, with it's own operand type.

This at least allows to not crash on the opcode.
However, this still won't generate all the snippets
with all the condcode enumerators. D60066 does that.

Reviewers: courbet, gchatelet

Reviewed By: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60057

llvm-svn: 357841
2019-04-06 14:16:26 +00:00
Simon Pilgrim d23611f9ad [X86] Split expandload and compressstore tests
llvm-svn: 357840
2019-04-06 14:14:54 +00:00
Simon Pilgrim 18a8a64c9f [X86][SSE] Add more exhaustive masked load/store tests
Reordered/renamed some existing tests to match the cleaned up order

llvm-svn: 357839
2019-04-06 14:01:37 +00:00
Simon Pilgrim 2ea8dbf564 [CostModel][X86] Add more exhaustive masked load/store/gather/scatter/expand/compress cost tests
llvm-svn: 357838
2019-04-06 12:08:37 +00:00
Stanislav Mekhanoshin 5182302a37 [AMDGPU] Sort out and rename multiple CI/VI predicates
Differential Revision: https://reviews.llvm.org/D60346

llvm-svn: 357835
2019-04-06 09:20:48 +00:00