register coalescing. This fixes many crashes and
places where debug info affects codegen (when
dbg.value is lowered to machine instructions, which
it isn't yet in TOT).
llvm-svn: 95739
The major win of this is that the code is simpler and they
print on the same line as the instruction again:
movl %eax, 96(%esp) ## 4-byte Spill
movl 96(%esp), %eax ## 4-byte Reload
cmpl 92(%esp), %eax ## 4-byte Folded Reload
jl LBB7_86
llvm-svn: 95738
Enhance the x86 backend to show the hex values of immediates in
comments when they are large. For example:
movl $1072693248, 4(%esp) ## imm = 0x3FF00000
llvm-svn: 95728
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files. We will use this for
the AVX specification to help with the transition from the current
SSE specification.
llvm-svn: 95727
Both zero cost example domain specific, and C++ foreign exception handling are
shown. The example's documentation fully explains how to run the example.
Notes:
1) The code uses an extremely simple type info model.
2) Only a single landing pad is used per unwind edge
(one call to llvm.eh.selector)
3) llvm.eh.selector support for filter arguments is not given.
4) llvm.eh.typeid.for is not used.
5) Forced unwind behavior is not supported.
6) Very little if any error handling is given.
7) __attribute__((__aligned__)) is used.
8) The code uses parts from the llvm compiler-rt project and
the llvm Kaleidoscope example.
9) The code has not been ported or tested on WINDOWS.
10) The code was not tested with a cmake build.
11) The code was tested for a debug build on 32bit X86 CentOS LINUX,
and both a debug and release build on OS X 10.6.2 (64bit).
llvm-svn: 95723
It fails with a release build only, for reasons
as yet unknown. (If there's a better way to Xfail
things here let me know, doesn't seem to be any
prior art in unittests.)
llvm-svn: 95700
out of the AsmWriterEmitter. This patch does the physical
code movement, but leaves the implementation unchanged. I'll
make any changes necessary to generalize the code in a
separate patch.
llvm-svn: 95697
in X86-32 mode. This is still required in x86-64 mode to avoid
forming [disp+rip] encoding. Rewrite the SIB byte decision logic
to be actually understandable.
llvm-svn: 95693
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
Daniel Dunbar