9d287358a8
[AMDGPU] gfx1010 SOP instructions
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Differential Revision: https://reviews.llvm.org/D61080
llvm-svn: 359139
2019-04-24 20:44:34 +00:00
ef92035827
[AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode
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See bug 39331: https://bugs.llvm.org/show_bug.cgi?id=39331
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D58288
llvm-svn: 354969
2019-02-27 13:12:12 +00:00
61105bab29
[AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions
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See bug 39319: https://bugs.llvm.org/show_bug.cgi?id=39319
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D56847
llvm-svn: 351549
2019-01-18 13:57:43 +00:00
cc88ce36ed
AMDGPU: Add instruction definitions for VGPR indexing
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VI added a second method of indexing into VGPRs
besides using v_movrel*
llvm-svn: 284027
2016-10-12 18:00:51 +00:00
7b1dc2c983
AMDGPU: Use i64 scalar compare instructions
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VI added eq/ne for i64, so use them.
llvm-svn: 281800
2016-09-17 02:02:19 +00:00
cb9dddb1d7
[AMDGPU] Assembler: Update SOP* tests
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Add VI encodings.
Reformat sopp.s to match style of other files.
Differential Revision: http://reviews.llvm.org/D18084
llvm-svn: 263540
2016-03-15 07:44:57 +00:00
79af6b33e0
[AMDGPU] Assembler: SOP* instruction fixes
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s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)
Differential Revision: http://reviews.llvm.org/D18040
llvm-svn: 263420
2016-03-14 11:17:19 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Stanislav Mekhanoshin